From b0d6df2b29c30462093e41418b36111551363efc Mon Sep 17 00:00:00 2001 From: James Hughes Date: Mon, 24 Mar 2025 10:50:11 -0300 Subject: [PATCH 1/6] create first part of lab --- site/index.rst | 1 + site/labs/esap/esap-and-or-not.rst | 80 ++++++++++++++++++++++++++++++ 2 files changed, 81 insertions(+) create mode 100644 site/labs/esap/esap-and-or-not.rst diff --git a/site/index.rst b/site/index.rst index 7e0aaee5..01142e13 100644 --- a/site/index.rst +++ b/site/index.rst @@ -105,6 +105,7 @@ Office Hours labs/comparisons/comparisons labs/decoding-instructions/decoding-instructions labs/decoding-instructions/decoding-instructions-registers + labs/esap/esap-and-or-not diff --git a/site/labs/esap/esap-and-or-not.rst b/site/labs/esap/esap-and-or-not.rst new file mode 100644 index 00000000..09ab9ff8 --- /dev/null +++ b/site/labs/esap/esap-and-or-not.rst @@ -0,0 +1,80 @@ +************** +Enhancing ESAP +************** + +* Feel free to use your laptop +* You are strongly encourage to work with others + + * When you get stuck, ask those sitting around you for help + * Get used to working together in the labs + * Peer teaching and peer learning has been empirically shown to be very effective + + +For these questions, feel free to use a single Digital workspace for all the circuits. However, label each circuit with +labelled rectangles. These are components that can be found under **Components -> Misc. -> Decoration -> Rectangle**. + +Where possible, each question should have complete tests. The test component can be found under +**Components -> Misc. -> Test case**. Once a test component is placed on the workspace, right click on the component to +edit the test data. + +Questions may have restrictions on the logic gates that may be used. When restrictions are stated, they only apply to +the gates; inputs, outputs, wires, etc. may be still be used. + + + +Including Hardware +================== + +For this part of the lab, use the ESAP digital file +:download:`from here. <../../topics/control-logic/esap_alu_ram_output_pc_instruction_control.dig>` + + +#. Include the hardware for ``AND``, ``OR``, and ``NOT`` operations to the ESAP system + + * These operators will work similar to addition to subtraction in how they work + * Apply the operator to the contents of the A and B registers, and store the result in the A register + + * ``NOT`` only works on the contents of the A register + + +#. These new operators require control signals + + * Connect these new control signals to the control logic loop up table + + + +Control Logic +============= + +For this part of the lab, use the script for generating the control logic patterns +:download:`from here. <../../topics/control-logic/create_control_logic_patterns_for_look_up_table.py>` + + +#. Although the new control logic is connected, ensure the look up table has the correct number of outputs + + * Ensure the number of outputs from the look up table includes the new control signals + + +#. Update the contents of the look up table to allow for three new machine code instructions + + * An instruction for each of the operators allowed by the new hardware + * Use the 3 unused patterns for these instructions + * Use the Python script to create a new hex file for the look up table + + +#. Write machine code programs to ensure each of these new instructions work properly + + + + + + + + + + + + + + + From 11ece8b280b2740df5206767808470e9baea2b8d Mon Sep 17 00:00:00 2001 From: James Hughes Date: Mon, 24 Mar 2025 11:27:31 -0300 Subject: [PATCH 2/6] enhancing last bit --- site/labs/esap/esap-and-or-not.rst | 26 ++++++++++++++++++++++++++ 1 file changed, 26 insertions(+) diff --git a/site/labs/esap/esap-and-or-not.rst b/site/labs/esap/esap-and-or-not.rst index 09ab9ff8..fce3a74d 100644 --- a/site/labs/esap/esap-and-or-not.rst +++ b/site/labs/esap/esap-and-or-not.rst @@ -66,9 +66,35 @@ For this part of the lab, use the script for generating the control logic patter +Enhancing the Previous Lab +========================== +#. If not already completed, finish the design from the previous lab +16 Bit Bus +---------- + +#. In a separate circuit, create a design for a 16 bit bus using + + * RAM with an 8 bit address space and 8 bit addressability (:math:`265 \times 8` bits) + * A counter + * Two 8 bit instruction registers + + * Even counter values retrieve data from even RAM addresses, and odd values retrieve from odd memory addresses + * Fetching from RAM takes 2 clock cycles + * One of the two 8 bit registers will always store bit patterns from the even or odd memory addresses + * The output from these two 8 bit registers make up the 16 bit bus + + +#. Add this design to the larger design from the previous labs + + * Include it in the design such that bit patterns can be written to RAM and executed automatically + + * The bit patterns as discussed in previous labs + + + * Not all of the 16 bits will be needed when interfacing with the previous design From 7c9ac7a9c084fe9eb05ad257faf384f4eeb0bfd6 Mon Sep 17 00:00:00 2001 From: James Hughes Date: Mon, 24 Mar 2025 11:36:27 -0300 Subject: [PATCH 3/6] clean --- site/labs/esap/esap-and-or-not.rst | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/site/labs/esap/esap-and-or-not.rst b/site/labs/esap/esap-and-or-not.rst index fce3a74d..027e5a5e 100644 --- a/site/labs/esap/esap-and-or-not.rst +++ b/site/labs/esap/esap-and-or-not.rst @@ -1,6 +1,6 @@ -************** -Enhancing ESAP -************** +***************** +Enhancing Designs +***************** * Feel free to use your laptop * You are strongly encourage to work with others @@ -31,9 +31,9 @@ For this part of the lab, use the ESAP digital file #. Include the hardware for ``AND``, ``OR``, and ``NOT`` operations to the ESAP system - * These operators will work similar to addition to subtraction in how they work - * Apply the operator to the contents of the A and B registers, and store the result in the A register + * These operators will work similar to addition to subtraction in the existing design + * Apply the operator to the contents of the A and B registers, and store the result in the A register * ``NOT`` only works on the contents of the A register @@ -87,7 +87,7 @@ Enhancing the Previous Lab * The output from these two 8 bit registers make up the 16 bit bus -#. Add this design to the larger design from the previous labs +#. Add this 16 bit bus to the design from the previous labs * Include it in the design such that bit patterns can be written to RAM and executed automatically @@ -95,6 +95,7 @@ Enhancing the Previous Lab * Not all of the 16 bits will be needed when interfacing with the previous design + * The program counter enable will likely need to be controlled carefully From e48b4e183b7e2697a54f83a9ac771aa972a0dcb0 Mon Sep 17 00:00:00 2001 From: James Hughes Date: Mon, 24 Mar 2025 11:38:12 -0300 Subject: [PATCH 4/6] more clean --- site/index.rst | 2 +- .../esap-and-or-not.rst => system-design/enhancing-designs.rst} | 0 2 files changed, 1 insertion(+), 1 deletion(-) rename site/labs/{esap/esap-and-or-not.rst => system-design/enhancing-designs.rst} (100%) diff --git a/site/index.rst b/site/index.rst index 01142e13..ce13dc8b 100644 --- a/site/index.rst +++ b/site/index.rst @@ -105,7 +105,7 @@ Office Hours labs/comparisons/comparisons labs/decoding-instructions/decoding-instructions labs/decoding-instructions/decoding-instructions-registers - labs/esap/esap-and-or-not + labs/system-design/enhancing-designs diff --git a/site/labs/esap/esap-and-or-not.rst b/site/labs/system-design/enhancing-designs.rst similarity index 100% rename from site/labs/esap/esap-and-or-not.rst rename to site/labs/system-design/enhancing-designs.rst From b292c4c76e515d3a36ce5e8ce4a2e24ce4ef7ff9 Mon Sep 17 00:00:00 2001 From: James Hughes Date: Mon, 24 Mar 2025 12:44:50 -0300 Subject: [PATCH 5/6] clean intro --- site/labs/system-design/enhancing-designs.rst | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/site/labs/system-design/enhancing-designs.rst b/site/labs/system-design/enhancing-designs.rst index 027e5a5e..d9b92da4 100644 --- a/site/labs/system-design/enhancing-designs.rst +++ b/site/labs/system-design/enhancing-designs.rst @@ -10,17 +10,6 @@ Enhancing Designs * Peer teaching and peer learning has been empirically shown to be very effective -For these questions, feel free to use a single Digital workspace for all the circuits. However, label each circuit with -labelled rectangles. These are components that can be found under **Components -> Misc. -> Decoration -> Rectangle**. - -Where possible, each question should have complete tests. The test component can be found under -**Components -> Misc. -> Test case**. Once a test component is placed on the workspace, right click on the component to -edit the test data. - -Questions may have restrictions on the logic gates that may be used. When restrictions are stated, they only apply to -the gates; inputs, outputs, wires, etc. may be still be used. - - Including Hardware ================== From d393cee604c8971760bd614ae4cbd188223f1777 Mon Sep 17 00:00:00 2001 From: James Alexander Hughes Date: Mon, 24 Mar 2025 13:00:26 -0300 Subject: [PATCH 6/6] Update site/labs/system-design/enhancing-designs.rst Co-authored-by: Taras Mychaskiw --- site/labs/system-design/enhancing-designs.rst | 9 --------- 1 file changed, 9 deletions(-) diff --git a/site/labs/system-design/enhancing-designs.rst b/site/labs/system-design/enhancing-designs.rst index d9b92da4..2c1c2791 100644 --- a/site/labs/system-design/enhancing-designs.rst +++ b/site/labs/system-design/enhancing-designs.rst @@ -85,12 +85,3 @@ Enhancing the Previous Lab * Not all of the 16 bits will be needed when interfacing with the previous design * The program counter enable will likely need to be controlled carefully - - - - - - - - -