repositories Search Results · repo:jimwang99/parser-for-chip-design language:Python

Filter by

• • Code... (...)results
  • Issues
    results
  • Pull requests
    results
  • Discussions
    results
  • Commits
    results
  • Packages
    results
  • Wikis
    results

• Advanced

  • Owner
  • Size
  • Number of followers
  • Number of forks
  • Number of stars
  • Date created
  • Date pushed
  • Topic
  • License
  • Archived
  • Public
  • Private
• Advanced search

Code... (...)

0 files

 (47 ms)

0 files

injimwang99/parser-for-chip-design (press backspace or delete to remove)

Sort by: Best match

Filter

jimwang99/parser-for-chip-design

A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).

python

verilog

liberty

netlist

• Python
·
• 32
·
• Updated
  on Jun 13, 2015

Star

Sponsor open source projects you depend on

Contributors are working behind the scenes to make open source better for everyone—give them the help and recognition they deserve.Explore sponsorable projects

ProTip! 

Press the

/

key to activate the search input again and adjust your query.

Sponsor open source projects you depend on

Contributors are working behind the scenes to make open source better for everyone—give them the help and recognition they deserve.Explore sponsorable projects

ProTip! 

Press the

/

key to activate the search input again and adjust your query.