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Last changes removing python 2.7
1 parent 7dc5ebd commit 02588ca

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5 files changed

+11
-16
lines changed

5 files changed

+11
-16
lines changed

myhdl/conversion/_toVerilog.py

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -799,7 +799,7 @@ def visit_Call(self, node):
799799
self.write(opening)
800800
self.visit(fn.value)
801801
self.write(closing)
802-
elif (type(f) in type) and issubclass(f, Exception):
802+
elif (type(f) is type) and issubclass(f, Exception):
803803
self.write(f.__name__)
804804
elif f in (posedge, negedge):
805805
opening, closing = ' ', ''

myhdl/numeric/_sintba.py

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -346,10 +346,7 @@ def __ifloordiv__(self, other):
346346
return self
347347

348348
def __imod__(self, other):
349-
right = copy(other)
350-
if self.high > other.high:
351-
right = right.resize(self.high, other.low)
352-
result = self % right
349+
result = self % other
353350
if self.is_signed:
354351
value = result.resize(self.high, self.low)
355352
else:

myhdl/test/conversion/toVHDL/test_interfaces5.py

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,3 @@
1-
from __future__ import absolute_import, print_function
2-
31
from myhdl import Signal, intbv, always_seq, ResetSignal, now, \
42
instance, delay, StopSimulation, Simulation, toVHDL
53
from myhdl.conversion import analyze, verify

myhdl/test/numeric/test_sfixba.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -619,8 +619,8 @@ def testSetSlice(self):
619619
ba[i:j] = val
620620
except RuntimeWarning:
621621
if isinstance(val, int):
622-
self.assertTrue((bit_length(val) > (i - j)) or
623-
(bit_length(-1 - val) >
622+
self.assertTrue((val.bit_length() > (i - j)) or
623+
((-1 - val).bit_length() >
624624
(i - j)))
625625
else:
626626
self.assertTrue((len(val) != (i - j)) or \
@@ -651,9 +651,9 @@ def testSetSliceLeftOpen(self):
651651
bai[:j] = -1 - val
652652
except RuntimeWarning:
653653
if isinstance(val, int):
654-
self.assertTrue((bit_length(val) >
654+
self.assertTrue((val.bit_length() >
655655
(ba.high - j)) or
656-
(bit_length(-1-val) >
656+
((-1-val).bit_length() >
657657
(bai.high - j - 1)))
658658
else:
659659
self.assertTrue((len(val) != (ba.high - j)) or

myhdl/test/numeric/test_sintba.py

Lines changed: 5 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -268,8 +268,8 @@ def testSetSlice(self):
268268
ba[i:j] = val
269269
except RuntimeWarning:
270270
if isinstance(val, int):
271-
self.assertTrue((bit_length(val) > (i - j)) \
272-
or (bit_length(-1 - val) > \
271+
self.assertTrue((val.bit_length() > (i - j)) \
272+
or ((-1 - val).bit_length() > \
273273
(i - j)))
274274
else:
275275
self.assertTrue((len(val) != (i - j)) or \
@@ -299,9 +299,9 @@ def testSetSliceLeftOpen(self):
299299
bai[:j] = -1 - val
300300
except RuntimeWarning:
301301
if isinstance(val, int):
302-
self.assertTrue((bit_length(val) > \
302+
self.assertTrue((val.bit_length() > \
303303
(len(ba) - j)) or \
304-
(bit_length(-1-val) > \
304+
((-1-val).bit_length() > \
305305
(len(bai) - j - 1)))
306306
else:
307307
self.assertTrue((len(val) != (len(ba) - j)) or \
@@ -639,7 +639,7 @@ def testSliceAssign(self):
639639
try:
640640
a[:] = v
641641
except RuntimeWarning:
642-
self.assertTrue((bit_length(v) > len(a)) or (v < 0))
642+
self.assertTrue((v.bit_length() > len(a)) or (v < 0))
643643
warnings.resetwarnings()
644644

645645
def checkBounds(self, i, j, op):

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