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1 parent 76cf970 commit 44c5d14

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14 files changed

+168
-156
lines changed

14 files changed

+168
-156
lines changed

‎include/pb/utils_def.h‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@
1818
/* Compute the number of elements in the given array */
1919
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
2020

21-
#define IS_POWER_OF_TWO(x) (((x) & ((x)-1)) == 0)
21+
#define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0)
2222

2323
#define SIZE_FROM_LOG2_WORDS(n) (4 << (n))
2424

@@ -56,7 +56,7 @@
5656
* This variant of div_round_up can be used in macro definition but should not
5757
* be used in C code as the `div` parameter is evaluated twice.
5858
*/
59-
#define DIV_ROUND_UP_2EVAL(n, d) (((n) + (d)-1) / (d))
59+
#define DIV_ROUND_UP_2EVAL(n, d) (((n) + (d) - 1) / (d))
6060

6161
#define div_round_up(val, div) \
6262
__extension__({ \
@@ -88,9 +88,9 @@
8888
*
8989
* round_down() is similar but rounds the value down instead.
9090
*/
91-
#define round_boundary(value, boundary) ((__typeof__(value))((boundary)-1))
91+
#define round_boundary(value, boundary) ((__typeof__(value))((boundary) - 1))
9292

93-
#define round_up(value, boundary) ((((value)-1) | round_boundary(value, boundary)) + 1)
93+
#define round_up(value, boundary) ((((value) - 1) | round_boundary(value, boundary)) + 1)
9494

9595
#define round_down(value, boundary) ((value) & ~round_boundary(value, boundary))
9696

‎include/plat/imx8x/imx8dxl_pads.h‎

Lines changed: 18 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -26,12 +26,14 @@
2626
#define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3U /* */
2727
#define SC_P_USB_SS3_TC0 \
2828
4U /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03, LSIO.GPIO7.IO03 */
29-
#define SC_P_USB_SS3_TC1 5U /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04, LSIO.GPIO7.IO04 \
30-
*/
29+
#define SC_P_USB_SS3_TC1 \
30+
5U /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04, LSIO.GPIO7.IO04 \
31+
*/
3132
#define SC_P_USB_SS3_TC2 \
3233
6U /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05, LSIO.GPIO7.IO05 */
33-
#define SC_P_USB_SS3_TC3 7U /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06, LSIO.GPIO7.IO06 \
34-
*/
34+
#define SC_P_USB_SS3_TC3 \
35+
7U /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06, LSIO.GPIO7.IO06 \
36+
*/
3537
#define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8U /* */
3638
#define SC_P_EMMC0_CLK 9U /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */
3739
#define SC_P_EMMC0_CMD 10U /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */
@@ -78,10 +80,11 @@
7880
#define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35U /* */
7981
#define SC_P_ENET0_RGMII_RXC \
8082
36U /* CONN.ENET0.RGMII_RXC, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */
81-
#define SC_P_ENET0_RGMII_RX_CTL 37U /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 \
82-
*/
83-
#define SC_P_ENET0_RGMII_RXD0 38U /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
84-
#define SC_P_ENET0_RGMII_RXD1 39U /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
83+
#define SC_P_ENET0_RGMII_RX_CTL \
84+
37U /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 \
85+
*/
86+
#define SC_P_ENET0_RGMII_RXD0 38U /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */
87+
#define SC_P_ENET0_RGMII_RXD1 39U /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */
8588
#define SC_P_ENET0_RGMII_RXD2 \
8689
40U /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */
8790
#define SC_P_ENET0_RGMII_RXD3 \
@@ -98,12 +101,13 @@
98101
#define SC_P_ENET1_RGMII_TXC \
99102
47U /* LSIO.GPIO0.IO00, CONN.EQOS.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.EQOS.RGMII_TXC, \
100103
CONN.EQOS.RCLK50M_IN */
101-
#define SC_P_ENET1_RGMII_TXD2 48U /* , ADMA.LCDIF.D01, CONN.EQOS.RGMII_TXD2, LSIO.GPIO0.IO01 */
102-
#define SC_P_ENET1_RGMII_TX_CTL 49U /* , ADMA.LCDIF.D02, CONN.EQOS.RGMII_TX_CTL, LSIO.GPIO0.IO02 \
103-
*/
104-
#define SC_P_ENET1_RGMII_TXD3 50U /* , ADMA.LCDIF.D03, CONN.EQOS.RGMII_TXD3, LSIO.GPIO0.IO03 */
105-
#define SC_P_ENET1_RGMII_RXC 51U /* , ADMA.LCDIF.D04, CONN.EQOS.RGMII_RXC, LSIO.GPIO0.IO04 */
106-
#define SC_P_ENET1_RGMII_RXD3 52U /* , ADMA.LCDIF.D05, CONN.EQOS.RGMII_RXD3, LSIO.GPIO0.IO05 */
104+
#define SC_P_ENET1_RGMII_TXD2 48U /* , ADMA.LCDIF.D01, CONN.EQOS.RGMII_TXD2, LSIO.GPIO0.IO01 */
105+
#define SC_P_ENET1_RGMII_TX_CTL \
106+
49U /* , ADMA.LCDIF.D02, CONN.EQOS.RGMII_TX_CTL, LSIO.GPIO0.IO02 \
107+
*/
108+
#define SC_P_ENET1_RGMII_TXD3 50U /* , ADMA.LCDIF.D03, CONN.EQOS.RGMII_TXD3, LSIO.GPIO0.IO03 */
109+
#define SC_P_ENET1_RGMII_RXC 51U /* , ADMA.LCDIF.D04, CONN.EQOS.RGMII_RXC, LSIO.GPIO0.IO04 */
110+
#define SC_P_ENET1_RGMII_RXD3 52U /* , ADMA.LCDIF.D05, CONN.EQOS.RGMII_RXD3, LSIO.GPIO0.IO05 */
107111
#define SC_P_ENET1_RGMII_RXD2 \
108112
53U /* , ADMA.LCDIF.D06, CONN.EQOS.RGMII_RXD2, LSIO.GPIO0.IO06, LSIO.GPIO6.IO00 */
109113
#define SC_P_ENET1_RGMII_RXD1 \

‎include/plat/imx8x/imx8qm_pads.h‎

Lines changed: 65 additions & 57 deletions
Original file line numberDiff line numberDiff line change
@@ -36,13 +36,15 @@
3636
#define SC_P_M41_GPIO0_00 13U /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */
3737
#define SC_P_M41_GPIO0_01 14U /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */
3838
#define SC_P_GPT0_CLK 15U /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */
39-
#define SC_P_GPT0_CAPTURE 16U /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 \
40-
*/
39+
#define SC_P_GPT0_CAPTURE \
40+
16U /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 \
41+
*/
4142
#define SC_P_GPT0_COMPARE \
4243
17U /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */
43-
#define SC_P_GPT1_CLK 18U /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
44-
#define SC_P_GPT1_CAPTURE 19U /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 \
45-
*/
44+
#define SC_P_GPT1_CLK 18U /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */
45+
#define SC_P_GPT1_CAPTURE \
46+
19U /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 \
47+
*/
4648
#define SC_P_GPT1_COMPARE \
4749
20U /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */
4850
#define SC_P_UART0_RX 21U /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */
@@ -69,34 +71,36 @@
6971
#define SC_P_SCU_GPIO0_06 42U /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */
7072
#define SC_P_SCU_GPIO0_07 \
7173
43U /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */
72-
#define SC_P_SCU_BOOT_MODE0 44U /* SCU.DSC.BOOT_MODE0 */
73-
#define SC_P_SCU_BOOT_MODE1 45U /* SCU.DSC.BOOT_MODE1 */
74-
#define SC_P_SCU_BOOT_MODE2 46U /* SCU.DSC.BOOT_MODE2 */
75-
#define SC_P_SCU_BOOT_MODE3 47U /* SCU.DSC.BOOT_MODE3 */
76-
#define SC_P_SCU_BOOT_MODE4 48U /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
77-
#define SC_P_SCU_BOOT_MODE5 49U /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
78-
#define SC_P_LVDS0_GPIO00 50U /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
79-
#define SC_P_LVDS0_GPIO01 51U /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
80-
#define SC_P_LVDS0_I2C0_SCL 52U /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
81-
#define SC_P_LVDS0_I2C0_SDA 53U /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
82-
#define SC_P_LVDS0_I2C1_SCL 54U /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
83-
#define SC_P_LVDS0_I2C1_SDA 55U /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
84-
#define SC_P_LVDS1_GPIO00 56U /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
85-
#define SC_P_LVDS1_GPIO01 57U /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
86-
#define SC_P_LVDS1_I2C0_SCL 58U /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
87-
#define SC_P_LVDS1_I2C0_SDA 59U /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
88-
#define SC_P_LVDS1_I2C1_SCL 60U /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
89-
#define SC_P_LVDS1_I2C1_SDA 61U /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
90-
#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62U /* */
91-
#define SC_P_MIPI_DSI0_I2C0_SCL 63U /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
92-
#define SC_P_MIPI_DSI0_I2C0_SDA 64U /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
93-
#define SC_P_MIPI_DSI0_GPIO0_00 65U /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 \
94-
*/
95-
#define SC_P_MIPI_DSI0_GPIO0_01 66U /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
96-
#define SC_P_MIPI_DSI1_I2C0_SCL 67U /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
97-
#define SC_P_MIPI_DSI1_I2C0_SDA 68U /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
98-
#define SC_P_MIPI_DSI1_GPIO0_00 69U /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 \
99-
*/
74+
#define SC_P_SCU_BOOT_MODE0 44U /* SCU.DSC.BOOT_MODE0 */
75+
#define SC_P_SCU_BOOT_MODE1 45U /* SCU.DSC.BOOT_MODE1 */
76+
#define SC_P_SCU_BOOT_MODE2 46U /* SCU.DSC.BOOT_MODE2 */
77+
#define SC_P_SCU_BOOT_MODE3 47U /* SCU.DSC.BOOT_MODE3 */
78+
#define SC_P_SCU_BOOT_MODE4 48U /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */
79+
#define SC_P_SCU_BOOT_MODE5 49U /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */
80+
#define SC_P_LVDS0_GPIO00 50U /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */
81+
#define SC_P_LVDS0_GPIO01 51U /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */
82+
#define SC_P_LVDS0_I2C0_SCL 52U /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */
83+
#define SC_P_LVDS0_I2C0_SDA 53U /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */
84+
#define SC_P_LVDS0_I2C1_SCL 54U /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */
85+
#define SC_P_LVDS0_I2C1_SDA 55U /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */
86+
#define SC_P_LVDS1_GPIO00 56U /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */
87+
#define SC_P_LVDS1_GPIO01 57U /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */
88+
#define SC_P_LVDS1_I2C0_SCL 58U /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */
89+
#define SC_P_LVDS1_I2C0_SDA 59U /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */
90+
#define SC_P_LVDS1_I2C1_SCL 60U /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */
91+
#define SC_P_LVDS1_I2C1_SDA 61U /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */
92+
#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62U /* */
93+
#define SC_P_MIPI_DSI0_I2C0_SCL 63U /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */
94+
#define SC_P_MIPI_DSI0_I2C0_SDA 64U /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */
95+
#define SC_P_MIPI_DSI0_GPIO0_00 \
96+
65U /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 \
97+
*/
98+
#define SC_P_MIPI_DSI0_GPIO0_01 66U /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */
99+
#define SC_P_MIPI_DSI1_I2C0_SCL 67U /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */
100+
#define SC_P_MIPI_DSI1_I2C0_SDA 68U /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */
101+
#define SC_P_MIPI_DSI1_GPIO0_00 \
102+
69U /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 \
103+
*/
100104
#define SC_P_MIPI_DSI1_GPIO0_01 70U /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */
101105
#define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71U /* */
102106
#define SC_P_MIPI_CSI0_MCLK_OUT 72U /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */
@@ -106,19 +110,20 @@
106110
75U /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */
107111
#define SC_P_MIPI_CSI0_GPIO0_01 \
108112
76U /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */
109-
#define SC_P_MIPI_CSI1_MCLK_OUT 77U /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
110-
#define SC_P_MIPI_CSI1_GPIO0_00 78U /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
111-
#define SC_P_MIPI_CSI1_GPIO0_01 79U /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
112-
#define SC_P_MIPI_CSI1_I2C0_SCL 80U /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
113-
#define SC_P_MIPI_CSI1_I2C0_SDA 81U /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
114-
#define SC_P_HDMI_TX0_TS_SCL 82U /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
115-
#define SC_P_HDMI_TX0_TS_SDA 83U /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
116-
#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84U /* */
117-
#define SC_P_ESAI1_FSR 85U /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
118-
#define SC_P_ESAI1_FST 86U /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
119-
#define SC_P_ESAI1_SCKR 87U /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
120-
#define SC_P_ESAI1_SCKT 88U /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 \
121-
*/
113+
#define SC_P_MIPI_CSI1_MCLK_OUT 77U /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */
114+
#define SC_P_MIPI_CSI1_GPIO0_00 78U /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */
115+
#define SC_P_MIPI_CSI1_GPIO0_01 79U /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */
116+
#define SC_P_MIPI_CSI1_I2C0_SCL 80U /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */
117+
#define SC_P_MIPI_CSI1_I2C0_SDA 81U /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */
118+
#define SC_P_HDMI_TX0_TS_SCL 82U /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */
119+
#define SC_P_HDMI_TX0_TS_SDA 83U /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */
120+
#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84U /* */
121+
#define SC_P_ESAI1_FSR 85U /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */
122+
#define SC_P_ESAI1_FST 86U /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */
123+
#define SC_P_ESAI1_SCKR 87U /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */
124+
#define SC_P_ESAI1_SCKT \
125+
88U /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 \
126+
*/
122127
#define SC_P_ESAI1_TX0 89U /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */
123128
#define SC_P_ESAI1_TX1 90U /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */
124129
#define SC_P_ESAI1_TX2_RX3 91U /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */
@@ -271,9 +276,10 @@
271276
#define SC_P_USDHC1_DATA2 227U /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */
272277
#define SC_P_USDHC1_DATA3 228U /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */
273278
#define SC_P_CTL_NAND_DQS_P_N 229U /* */
274-
#define SC_P_USDHC1_DATA4 230U /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 \
275-
*/
276-
#define SC_P_USDHC1_DATA5 231U /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
279+
#define SC_P_USDHC1_DATA4 \
280+
230U /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 \
281+
*/
282+
#define SC_P_USDHC1_DATA5 231U /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */
277283
#define SC_P_USDHC1_DATA6 \
278284
232U /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */
279285
#define SC_P_USDHC1_DATA7 \
@@ -300,10 +306,11 @@
300306
248U /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */
301307
#define SC_P_ENET0_RGMII_RXC \
302308
249U /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */
303-
#define SC_P_ENET0_RGMII_RX_CTL 250U /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 \
304-
*/
305-
#define SC_P_ENET0_RGMII_RXD0 251U /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
306-
#define SC_P_ENET0_RGMII_RXD1 252U /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
309+
#define SC_P_ENET0_RGMII_RX_CTL \
310+
250U /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 \
311+
*/
312+
#define SC_P_ENET0_RGMII_RXD0 251U /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */
313+
#define SC_P_ENET0_RGMII_RXD1 252U /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */
307314
#define SC_P_ENET0_RGMII_RXD2 \
308315
253U /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */
309316
#define SC_P_ENET0_RGMII_RXD3 \
@@ -321,10 +328,11 @@
321328
261U /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */
322329
#define SC_P_ENET1_RGMII_RXC \
323330
262U /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */
324-
#define SC_P_ENET1_RGMII_RX_CTL 263U /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 \
325-
*/
326-
#define SC_P_ENET1_RGMII_RXD0 264U /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
327-
#define SC_P_ENET1_RGMII_RXD1 265U /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
331+
#define SC_P_ENET1_RGMII_RX_CTL \
332+
263U /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 \
333+
*/
334+
#define SC_P_ENET1_RGMII_RXD0 264U /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */
335+
#define SC_P_ENET1_RGMII_RXD1 265U /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */
328336
#define SC_P_ENET1_RGMII_RXD2 \
329337
266U /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */
330338
#define SC_P_ENET1_RGMII_RXD3 \

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