From 76cf970dc2aaba8b6087b93dff97d941ff651373 Mon Sep 17 00:00:00 2001 From: "pre-commit-ci[bot]" <66853113+pre-commit-ci[bot]@users.noreply.github.com> Date: Mon, 20 Oct 2025 23:25:53 +0000 Subject: [PATCH 1/2] [pre-commit.ci] pre-commit autoupdate MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit updates: - [github.com/pre-commit/pre-commit-hooks: v4.5.0 → v6.0.0](https://github.com/pre-commit/pre-commit-hooks/compare/v4.5.0...v6.0.0) - [github.com/pre-commit/mirrors-mypy: v1.8.0 → v1.18.2](https://github.com/pre-commit/mirrors-mypy/compare/v1.8.0...v1.18.2) - [github.com/astral-sh/ruff-pre-commit: v0.2.1 → v0.14.1](https://github.com/astral-sh/ruff-pre-commit/compare/v0.2.1...v0.14.1) - [github.com/pre-commit/mirrors-clang-format: v17.0.6 → v21.1.2](https://github.com/pre-commit/mirrors-clang-format/compare/v17.0.6...v21.1.2) --- .pre-commit-config.yaml | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 50ff39b2..450de0a2 100644 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -1,7 +1,7 @@ exclude: ^(src/plat/imx8x/sci|include/plat/imx8x/sci) repos: - repo: https://github.com/pre-commit/pre-commit-hooks - rev: v4.5.0 + rev: v6.0.0 hooks: - id: check-added-large-files - id: check-case-conflict @@ -15,7 +15,7 @@ repos: - id: trailing-whitespace - repo: https://github.com/pre-commit/mirrors-mypy - rev: v1.8.0 + rev: v1.18.2 hooks: - id: mypy additional_dependencies: @@ -26,12 +26,12 @@ repos: args: ["."] - repo: https://github.com/astral-sh/ruff-pre-commit - rev: v0.2.1 + rev: v0.14.1 hooks: - id: ruff args: [ --fix ] - repo: https://github.com/pre-commit/mirrors-clang-format - rev: v17.0.6 + rev: v21.1.2 hooks: - id: clang-format From 44c5d14c0e2c2efb6c03e1eb47eb6e45384920bf Mon Sep 17 00:00:00 2001 From: "pre-commit-ci[bot]" <66853113+pre-commit-ci[bot]@users.noreply.github.com> Date: Mon, 20 Oct 2025 23:26:04 +0000 Subject: [PATCH 2/2] [pre-commit.ci] auto fixes from pre-commit.com hooks for more information, see https://pre-commit.ci --- include/pb/utils_def.h | 8 +- include/plat/imx8x/imx8dxl_pads.h | 32 ++++--- include/plat/imx8x/imx8qm_pads.h | 122 +++++++++++++------------ include/plat/imx8x/imx8qxp_pads.h | 103 ++++++++++++--------- src/arch/armv7a/include/arch/arch.h | 2 +- src/arch/armv8a/include/arch/mmu.h | 2 +- src/drivers/fs/lfs.c | 4 +- src/lib/bpak.c | 2 +- src/plat/imx6ul/plat.h | 17 +--- src/plat/imx8m/plat.h | 17 +--- src/plat/qemu/gcov.c | 4 +- tools/punchboot/punchboot/__init__.py | 6 +- tools/punchboot/punchboot/partition.py | 2 +- tools/punchboot/punchboot/session.py | 3 +- 14 files changed, 168 insertions(+), 156 deletions(-) diff --git a/include/pb/utils_def.h b/include/pb/utils_def.h index 7218ed34..bf7d10f7 100644 --- a/include/pb/utils_def.h +++ b/include/pb/utils_def.h @@ -18,7 +18,7 @@ /* Compute the number of elements in the given array */ #define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) -#define IS_POWER_OF_TWO(x) (((x) & ((x)-1)) == 0) +#define IS_POWER_OF_TWO(x) (((x) & ((x) - 1)) == 0) #define SIZE_FROM_LOG2_WORDS(n) (4 << (n)) @@ -56,7 +56,7 @@ * This variant of div_round_up can be used in macro definition but should not * be used in C code as the `div` parameter is evaluated twice. */ -#define DIV_ROUND_UP_2EVAL(n, d) (((n) + (d)-1) / (d)) +#define DIV_ROUND_UP_2EVAL(n, d) (((n) + (d) - 1) / (d)) #define div_round_up(val, div) \ __extension__({ \ @@ -88,9 +88,9 @@ * * round_down() is similar but rounds the value down instead. */ -#define round_boundary(value, boundary) ((__typeof__(value))((boundary)-1)) +#define round_boundary(value, boundary) ((__typeof__(value))((boundary) - 1)) -#define round_up(value, boundary) ((((value)-1) | round_boundary(value, boundary)) + 1) +#define round_up(value, boundary) ((((value) - 1) | round_boundary(value, boundary)) + 1) #define round_down(value, boundary) ((value) & ~round_boundary(value, boundary)) diff --git a/include/plat/imx8x/imx8dxl_pads.h b/include/plat/imx8x/imx8dxl_pads.h index 232d00ab..34de8d97 100644 --- a/include/plat/imx8x/imx8dxl_pads.h +++ b/include/plat/imx8x/imx8dxl_pads.h @@ -26,12 +26,14 @@ #define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3U /* */ #define SC_P_USB_SS3_TC0 \ 4U /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03, LSIO.GPIO7.IO03 */ -#define SC_P_USB_SS3_TC1 5U /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04, LSIO.GPIO7.IO04 \ - */ +#define SC_P_USB_SS3_TC1 \ + 5U /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04, LSIO.GPIO7.IO04 \ + */ #define SC_P_USB_SS3_TC2 \ 6U /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05, LSIO.GPIO7.IO05 */ -#define SC_P_USB_SS3_TC3 7U /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06, LSIO.GPIO7.IO06 \ - */ +#define SC_P_USB_SS3_TC3 \ + 7U /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06, LSIO.GPIO7.IO06 \ + */ #define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8U /* */ #define SC_P_EMMC0_CLK 9U /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ #define SC_P_EMMC0_CMD 10U /* CONN.EMMC0.CMD, CONN.NAND.DQS, LSIO.GPIO4.IO08 */ @@ -78,10 +80,11 @@ #define SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0 35U /* */ #define SC_P_ENET0_RGMII_RXC \ 36U /* CONN.ENET0.RGMII_RXC, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 */ -#define SC_P_ENET0_RGMII_RX_CTL 37U /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 \ - */ -#define SC_P_ENET0_RGMII_RXD0 38U /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ -#define SC_P_ENET0_RGMII_RXD1 39U /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RX_CTL \ + 37U /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 \ + */ +#define SC_P_ENET0_RGMII_RXD0 38U /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 39U /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ #define SC_P_ENET0_RGMII_RXD2 \ 40U /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ #define SC_P_ENET0_RGMII_RXD3 \ @@ -98,12 +101,13 @@ #define SC_P_ENET1_RGMII_TXC \ 47U /* LSIO.GPIO0.IO00, CONN.EQOS.RCLK50M_OUT, ADMA.LCDIF.D00, CONN.EQOS.RGMII_TXC, \ CONN.EQOS.RCLK50M_IN */ -#define SC_P_ENET1_RGMII_TXD2 48U /* , ADMA.LCDIF.D01, CONN.EQOS.RGMII_TXD2, LSIO.GPIO0.IO01 */ -#define SC_P_ENET1_RGMII_TX_CTL 49U /* , ADMA.LCDIF.D02, CONN.EQOS.RGMII_TX_CTL, LSIO.GPIO0.IO02 \ - */ -#define SC_P_ENET1_RGMII_TXD3 50U /* , ADMA.LCDIF.D03, CONN.EQOS.RGMII_TXD3, LSIO.GPIO0.IO03 */ -#define SC_P_ENET1_RGMII_RXC 51U /* , ADMA.LCDIF.D04, CONN.EQOS.RGMII_RXC, LSIO.GPIO0.IO04 */ -#define SC_P_ENET1_RGMII_RXD3 52U /* , ADMA.LCDIF.D05, CONN.EQOS.RGMII_RXD3, LSIO.GPIO0.IO05 */ +#define SC_P_ENET1_RGMII_TXD2 48U /* , ADMA.LCDIF.D01, CONN.EQOS.RGMII_TXD2, LSIO.GPIO0.IO01 */ +#define SC_P_ENET1_RGMII_TX_CTL \ + 49U /* , ADMA.LCDIF.D02, CONN.EQOS.RGMII_TX_CTL, LSIO.GPIO0.IO02 \ + */ +#define SC_P_ENET1_RGMII_TXD3 50U /* , ADMA.LCDIF.D03, CONN.EQOS.RGMII_TXD3, LSIO.GPIO0.IO03 */ +#define SC_P_ENET1_RGMII_RXC 51U /* , ADMA.LCDIF.D04, CONN.EQOS.RGMII_RXC, LSIO.GPIO0.IO04 */ +#define SC_P_ENET1_RGMII_RXD3 52U /* , ADMA.LCDIF.D05, CONN.EQOS.RGMII_RXD3, LSIO.GPIO0.IO05 */ #define SC_P_ENET1_RGMII_RXD2 \ 53U /* , ADMA.LCDIF.D06, CONN.EQOS.RGMII_RXD2, LSIO.GPIO0.IO06, LSIO.GPIO6.IO00 */ #define SC_P_ENET1_RGMII_RXD1 \ diff --git a/include/plat/imx8x/imx8qm_pads.h b/include/plat/imx8x/imx8qm_pads.h index a8a060a5..cf7189d0 100644 --- a/include/plat/imx8x/imx8qm_pads.h +++ b/include/plat/imx8x/imx8qm_pads.h @@ -36,13 +36,15 @@ #define SC_P_M41_GPIO0_00 13U /* M41.GPIO0.IO00, M41.TPM0.CH0, DMA.UART3.RX, LSIO.GPIO0.IO12 */ #define SC_P_M41_GPIO0_01 14U /* M41.GPIO0.IO01, M41.TPM0.CH1, DMA.UART3.TX, LSIO.GPIO0.IO13 */ #define SC_P_GPT0_CLK 15U /* LSIO.GPT0.CLK, DMA.I2C1.SCL, LSIO.KPP0.COL4, LSIO.GPIO0.IO14 */ -#define SC_P_GPT0_CAPTURE 16U /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 \ - */ +#define SC_P_GPT0_CAPTURE \ + 16U /* LSIO.GPT0.CAPTURE, DMA.I2C1.SDA, LSIO.KPP0.COL5, LSIO.GPIO0.IO15 \ + */ #define SC_P_GPT0_COMPARE \ 17U /* LSIO.GPT0.COMPARE, LSIO.PWM3.OUT, LSIO.KPP0.COL6, LSIO.GPIO0.IO16 */ -#define SC_P_GPT1_CLK 18U /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ -#define SC_P_GPT1_CAPTURE 19U /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 \ - */ +#define SC_P_GPT1_CLK 18U /* LSIO.GPT1.CLK, DMA.I2C2.SCL, LSIO.KPP0.COL7, LSIO.GPIO0.IO17 */ +#define SC_P_GPT1_CAPTURE \ + 19U /* LSIO.GPT1.CAPTURE, DMA.I2C2.SDA, LSIO.KPP0.ROW4, LSIO.GPIO0.IO18 \ + */ #define SC_P_GPT1_COMPARE \ 20U /* LSIO.GPT1.COMPARE, LSIO.PWM2.OUT, LSIO.KPP0.ROW5, LSIO.GPIO0.IO19 */ #define SC_P_UART0_RX 21U /* DMA.UART0.RX, SCU.UART0.RX, LSIO.GPIO0.IO20 */ @@ -69,34 +71,36 @@ #define SC_P_SCU_GPIO0_06 42U /* SCU.GPIO0.IO06, SCU.TPM0.CH0, LSIO.GPIO1.IO02 */ #define SC_P_SCU_GPIO0_07 \ 43U /* SCU.GPIO0.IO07, SCU.TPM0.CH1, SCU.DSC.RTC_CLOCK_OUTPUT_32K, LSIO.GPIO1.IO03 */ -#define SC_P_SCU_BOOT_MODE0 44U /* SCU.DSC.BOOT_MODE0 */ -#define SC_P_SCU_BOOT_MODE1 45U /* SCU.DSC.BOOT_MODE1 */ -#define SC_P_SCU_BOOT_MODE2 46U /* SCU.DSC.BOOT_MODE2 */ -#define SC_P_SCU_BOOT_MODE3 47U /* SCU.DSC.BOOT_MODE3 */ -#define SC_P_SCU_BOOT_MODE4 48U /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ -#define SC_P_SCU_BOOT_MODE5 49U /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ -#define SC_P_LVDS0_GPIO00 50U /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ -#define SC_P_LVDS0_GPIO01 51U /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ -#define SC_P_LVDS0_I2C0_SCL 52U /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ -#define SC_P_LVDS0_I2C0_SDA 53U /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ -#define SC_P_LVDS0_I2C1_SCL 54U /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ -#define SC_P_LVDS0_I2C1_SDA 55U /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ -#define SC_P_LVDS1_GPIO00 56U /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ -#define SC_P_LVDS1_GPIO01 57U /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ -#define SC_P_LVDS1_I2C0_SCL 58U /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ -#define SC_P_LVDS1_I2C0_SDA 59U /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ -#define SC_P_LVDS1_I2C1_SCL 60U /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ -#define SC_P_LVDS1_I2C1_SDA 61U /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ -#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62U /* */ -#define SC_P_MIPI_DSI0_I2C0_SCL 63U /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ -#define SC_P_MIPI_DSI0_I2C0_SDA 64U /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ -#define SC_P_MIPI_DSI0_GPIO0_00 65U /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 \ - */ -#define SC_P_MIPI_DSI0_GPIO0_01 66U /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ -#define SC_P_MIPI_DSI1_I2C0_SCL 67U /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ -#define SC_P_MIPI_DSI1_I2C0_SDA 68U /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ -#define SC_P_MIPI_DSI1_GPIO0_00 69U /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 \ - */ +#define SC_P_SCU_BOOT_MODE0 44U /* SCU.DSC.BOOT_MODE0 */ +#define SC_P_SCU_BOOT_MODE1 45U /* SCU.DSC.BOOT_MODE1 */ +#define SC_P_SCU_BOOT_MODE2 46U /* SCU.DSC.BOOT_MODE2 */ +#define SC_P_SCU_BOOT_MODE3 47U /* SCU.DSC.BOOT_MODE3 */ +#define SC_P_SCU_BOOT_MODE4 48U /* SCU.DSC.BOOT_MODE4, SCU.PMIC_I2C.SCL */ +#define SC_P_SCU_BOOT_MODE5 49U /* SCU.DSC.BOOT_MODE5, SCU.PMIC_I2C.SDA */ +#define SC_P_LVDS0_GPIO00 50U /* LVDS0.GPIO0.IO00, LVDS0.PWM0.OUT, LSIO.GPIO1.IO04 */ +#define SC_P_LVDS0_GPIO01 51U /* LVDS0.GPIO0.IO01, LSIO.GPIO1.IO05 */ +#define SC_P_LVDS0_I2C0_SCL 52U /* LVDS0.I2C0.SCL, LVDS0.GPIO0.IO02, LSIO.GPIO1.IO06 */ +#define SC_P_LVDS0_I2C0_SDA 53U /* LVDS0.I2C0.SDA, LVDS0.GPIO0.IO03, LSIO.GPIO1.IO07 */ +#define SC_P_LVDS0_I2C1_SCL 54U /* LVDS0.I2C1.SCL, DMA.UART2.TX, LSIO.GPIO1.IO08 */ +#define SC_P_LVDS0_I2C1_SDA 55U /* LVDS0.I2C1.SDA, DMA.UART2.RX, LSIO.GPIO1.IO09 */ +#define SC_P_LVDS1_GPIO00 56U /* LVDS1.GPIO0.IO00, LVDS1.PWM0.OUT, LSIO.GPIO1.IO10 */ +#define SC_P_LVDS1_GPIO01 57U /* LVDS1.GPIO0.IO01, LSIO.GPIO1.IO11 */ +#define SC_P_LVDS1_I2C0_SCL 58U /* LVDS1.I2C0.SCL, LVDS1.GPIO0.IO02, LSIO.GPIO1.IO12 */ +#define SC_P_LVDS1_I2C0_SDA 59U /* LVDS1.I2C0.SDA, LVDS1.GPIO0.IO03, LSIO.GPIO1.IO13 */ +#define SC_P_LVDS1_I2C1_SCL 60U /* LVDS1.I2C1.SCL, DMA.UART3.TX, LSIO.GPIO1.IO14 */ +#define SC_P_LVDS1_I2C1_SDA 61U /* LVDS1.I2C1.SDA, DMA.UART3.RX, LSIO.GPIO1.IO15 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_LVDSGPIO 62U /* */ +#define SC_P_MIPI_DSI0_I2C0_SCL 63U /* MIPI_DSI0.I2C0.SCL, LSIO.GPIO1.IO16 */ +#define SC_P_MIPI_DSI0_I2C0_SDA 64U /* MIPI_DSI0.I2C0.SDA, LSIO.GPIO1.IO17 */ +#define SC_P_MIPI_DSI0_GPIO0_00 \ + 65U /* MIPI_DSI0.GPIO0.IO00, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO18 \ + */ +#define SC_P_MIPI_DSI0_GPIO0_01 66U /* MIPI_DSI0.GPIO0.IO01, LSIO.GPIO1.IO19 */ +#define SC_P_MIPI_DSI1_I2C0_SCL 67U /* MIPI_DSI1.I2C0.SCL, LSIO.GPIO1.IO20 */ +#define SC_P_MIPI_DSI1_I2C0_SDA 68U /* MIPI_DSI1.I2C0.SDA, LSIO.GPIO1.IO21 */ +#define SC_P_MIPI_DSI1_GPIO0_00 \ + 69U /* MIPI_DSI1.GPIO0.IO00, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO22 \ + */ #define SC_P_MIPI_DSI1_GPIO0_01 70U /* MIPI_DSI1.GPIO0.IO01, LSIO.GPIO1.IO23 */ #define SC_P_COMP_CTL_GPIO_1V8_3V3_MIPIDSIGPIO 71U /* */ #define SC_P_MIPI_CSI0_MCLK_OUT 72U /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO1.IO24 */ @@ -106,19 +110,20 @@ 75U /* MIPI_CSI0.GPIO0.IO00, DMA.I2C0.SCL, MIPI_CSI1.I2C0.SCL, LSIO.GPIO1.IO27 */ #define SC_P_MIPI_CSI0_GPIO0_01 \ 76U /* MIPI_CSI0.GPIO0.IO01, DMA.I2C0.SDA, MIPI_CSI1.I2C0.SDA, LSIO.GPIO1.IO28 */ -#define SC_P_MIPI_CSI1_MCLK_OUT 77U /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ -#define SC_P_MIPI_CSI1_GPIO0_00 78U /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ -#define SC_P_MIPI_CSI1_GPIO0_01 79U /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ -#define SC_P_MIPI_CSI1_I2C0_SCL 80U /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ -#define SC_P_MIPI_CSI1_I2C0_SDA 81U /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ -#define SC_P_HDMI_TX0_TS_SCL 82U /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ -#define SC_P_HDMI_TX0_TS_SDA 83U /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ -#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84U /* */ -#define SC_P_ESAI1_FSR 85U /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ -#define SC_P_ESAI1_FST 86U /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ -#define SC_P_ESAI1_SCKR 87U /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ -#define SC_P_ESAI1_SCKT 88U /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 \ - */ +#define SC_P_MIPI_CSI1_MCLK_OUT 77U /* MIPI_CSI1.ACM.MCLK_OUT, LSIO.GPIO1.IO29 */ +#define SC_P_MIPI_CSI1_GPIO0_00 78U /* MIPI_CSI1.GPIO0.IO00, DMA.UART4.RX, LSIO.GPIO1.IO30 */ +#define SC_P_MIPI_CSI1_GPIO0_01 79U /* MIPI_CSI1.GPIO0.IO01, DMA.UART4.TX, LSIO.GPIO1.IO31 */ +#define SC_P_MIPI_CSI1_I2C0_SCL 80U /* MIPI_CSI1.I2C0.SCL, LSIO.GPIO2.IO00 */ +#define SC_P_MIPI_CSI1_I2C0_SDA 81U /* MIPI_CSI1.I2C0.SDA, LSIO.GPIO2.IO01 */ +#define SC_P_HDMI_TX0_TS_SCL 82U /* HDMI_TX0.I2C0.SCL, DMA.I2C0.SCL, LSIO.GPIO2.IO02 */ +#define SC_P_HDMI_TX0_TS_SDA 83U /* HDMI_TX0.I2C0.SDA, DMA.I2C0.SDA, LSIO.GPIO2.IO03 */ +#define SC_P_COMP_CTL_GPIO_3V3_HDMIGPIO 84U /* */ +#define SC_P_ESAI1_FSR 85U /* AUD.ESAI1.FSR, LSIO.GPIO2.IO04 */ +#define SC_P_ESAI1_FST 86U /* AUD.ESAI1.FST, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO05 */ +#define SC_P_ESAI1_SCKR 87U /* AUD.ESAI1.SCKR, LSIO.GPIO2.IO06 */ +#define SC_P_ESAI1_SCKT \ + 88U /* AUD.ESAI1.SCKT, AUD.SAI2.RXC, AUD.SPDIF0.EXT_CLK, LSIO.GPIO2.IO07 \ + */ #define SC_P_ESAI1_TX0 89U /* AUD.ESAI1.TX0, AUD.SAI2.RXD, AUD.SPDIF0.RX, LSIO.GPIO2.IO08 */ #define SC_P_ESAI1_TX1 90U /* AUD.ESAI1.TX1, AUD.SAI2.RXFS, AUD.SPDIF0.TX, LSIO.GPIO2.IO09 */ #define SC_P_ESAI1_TX2_RX3 91U /* AUD.ESAI1.TX2_RX3, AUD.SPDIF0.RX, LSIO.GPIO2.IO10 */ @@ -271,9 +276,10 @@ #define SC_P_USDHC1_DATA2 227U /* CONN.USDHC1.DATA2, CONN.NAND.DQS_N, LSIO.GPIO5.IO17 */ #define SC_P_USDHC1_DATA3 228U /* CONN.USDHC1.DATA3, CONN.NAND.DQS_P, LSIO.GPIO5.IO18 */ #define SC_P_CTL_NAND_DQS_P_N 229U /* */ -#define SC_P_USDHC1_DATA4 230U /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 \ - */ -#define SC_P_USDHC1_DATA5 231U /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ +#define SC_P_USDHC1_DATA4 \ + 230U /* CONN.USDHC1.DATA4, CONN.NAND.CE0_B, AUD.MQS.R, LSIO.GPIO5.IO19 \ + */ +#define SC_P_USDHC1_DATA5 231U /* CONN.USDHC1.DATA5, CONN.NAND.RE_B, AUD.MQS.L, LSIO.GPIO5.IO20 */ #define SC_P_USDHC1_DATA6 \ 232U /* CONN.USDHC1.DATA6, CONN.NAND.WE_B, CONN.USDHC1.WP, LSIO.GPIO5.IO21 */ #define SC_P_USDHC1_DATA7 \ @@ -300,10 +306,11 @@ 248U /* CONN.ENET0.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO03 */ #define SC_P_ENET0_RGMII_RXC \ 249U /* CONN.ENET0.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO04 */ -#define SC_P_ENET0_RGMII_RX_CTL 250U /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 \ - */ -#define SC_P_ENET0_RGMII_RXD0 251U /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ -#define SC_P_ENET0_RGMII_RXD1 252U /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ +#define SC_P_ENET0_RGMII_RX_CTL \ + 250U /* CONN.ENET0.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO05 \ + */ +#define SC_P_ENET0_RGMII_RXD0 251U /* CONN.ENET0.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO06 */ +#define SC_P_ENET0_RGMII_RXD1 252U /* CONN.ENET0.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO07 */ #define SC_P_ENET0_RGMII_RXD2 \ 253U /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO08 */ #define SC_P_ENET0_RGMII_RXD3 \ @@ -321,10 +328,11 @@ 261U /* CONN.ENET1.RGMII_TXD3, DMA.UART3.RTS_B, VPU.TSI_S1.SYNC, LSIO.GPIO6.IO15 */ #define SC_P_ENET1_RGMII_RXC \ 262U /* CONN.ENET1.RGMII_RXC, DMA.UART3.CTS_B, VPU.TSI_S1.DATA, LSIO.GPIO6.IO16 */ -#define SC_P_ENET1_RGMII_RX_CTL 263U /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 \ - */ -#define SC_P_ENET1_RGMII_RXD0 264U /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ -#define SC_P_ENET1_RGMII_RXD1 265U /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ +#define SC_P_ENET1_RGMII_RX_CTL \ + 263U /* CONN.ENET1.RGMII_RX_CTL, VPU.TSI_S0.VID, LSIO.GPIO6.IO17 \ + */ +#define SC_P_ENET1_RGMII_RXD0 264U /* CONN.ENET1.RGMII_RXD0, VPU.TSI_S0.SYNC, LSIO.GPIO6.IO18 */ +#define SC_P_ENET1_RGMII_RXD1 265U /* CONN.ENET1.RGMII_RXD1, VPU.TSI_S0.DATA, LSIO.GPIO6.IO19 */ #define SC_P_ENET1_RGMII_RXD2 \ 266U /* CONN.ENET1.RGMII_RXD2, CONN.ENET1.RMII_RX_ER, VPU.TSI_S0.CLK, LSIO.GPIO6.IO20 */ #define SC_P_ENET1_RGMII_RXD3 \ diff --git a/include/plat/imx8x/imx8qxp_pads.h b/include/plat/imx8x/imx8qxp_pads.h index 9659d394..24e19008 100644 --- a/include/plat/imx8x/imx8qxp_pads.h +++ b/include/plat/imx8x/imx8qxp_pads.h @@ -26,9 +26,10 @@ #define SC_P_COMP_CTL_GPIO_1V8_3V3_PCIESEP 3U /* */ #define SC_P_USB_SS3_TC0 \ 4U /* ADMA.I2C1.SCL, CONN.USB_OTG1.PWR, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO03 */ -#define SC_P_USB_SS3_TC1 5U /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ -#define SC_P_USB_SS3_TC2 6U /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 \ - */ +#define SC_P_USB_SS3_TC1 5U /* ADMA.I2C1.SCL, CONN.USB_OTG2.PWR, LSIO.GPIO4.IO04 */ +#define SC_P_USB_SS3_TC2 \ + 6U /* ADMA.I2C1.SDA, CONN.USB_OTG1.OC, CONN.USB_OTG2.OC, LSIO.GPIO4.IO05 \ + */ #define SC_P_USB_SS3_TC3 7U /* ADMA.I2C1.SDA, CONN.USB_OTG2.OC, LSIO.GPIO4.IO06 */ #define SC_P_COMP_CTL_GPIO_3V3_USB3IO 8U /* */ #define SC_P_EMMC0_CLK 9U /* CONN.EMMC0.CLK, CONN.NAND.READY_B, LSIO.GPIO4.IO07 */ @@ -42,12 +43,15 @@ 16U /* CONN.EMMC0.DATA4, CONN.NAND.DATA04, CONN.EMMC0.WP, LSIO.GPIO4.IO13 */ #define SC_P_EMMC0_DATA5 \ 17U /* CONN.EMMC0.DATA5, CONN.NAND.DATA05, CONN.EMMC0.VSELECT, LSIO.GPIO4.IO14 */ -#define SC_P_EMMC0_DATA6 18U /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 \ - */ -#define SC_P_EMMC0_DATA7 19U /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 \ - */ -#define SC_P_EMMC0_STROBE 20U /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 \ - */ +#define SC_P_EMMC0_DATA6 \ + 18U /* CONN.EMMC0.DATA6, CONN.NAND.DATA06, CONN.MLB.CLK, LSIO.GPIO4.IO15 \ + */ +#define SC_P_EMMC0_DATA7 \ + 19U /* CONN.EMMC0.DATA7, CONN.NAND.DATA07, CONN.MLB.SIG, LSIO.GPIO4.IO16 \ + */ +#define SC_P_EMMC0_STROBE \ + 20U /* CONN.EMMC0.STROBE, CONN.NAND.CLE, CONN.MLB.DATA, LSIO.GPIO4.IO17 \ + */ #define SC_P_EMMC0_RESET_B 21U /* CONN.EMMC0.RESET_B, CONN.NAND.WP_B, LSIO.GPIO4.IO18 */ #define SC_P_COMP_CTL_GPIO_1V8_3V3_SD1FIX1 22U /* */ #define SC_P_USDHC1_RESET_B \ @@ -62,8 +66,9 @@ #define SC_P_COMP_CTL_GPIO_1V8_3V3_VSELSEP 29U /* */ #define SC_P_USDHC1_CLK 30U /* CONN.USDHC1.CLK, ADMA.UART3.RX, LSIO.GPIO4.IO23 */ #define SC_P_USDHC1_CMD 31U /* CONN.USDHC1.CMD, CONN.NAND.CE0_B, ADMA.MQS.R, LSIO.GPIO4.IO24 */ -#define SC_P_USDHC1_DATA0 32U /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 \ - */ +#define SC_P_USDHC1_DATA0 \ + 32U /* CONN.USDHC1.DATA0, CONN.NAND.CE1_B, ADMA.MQS.L, LSIO.GPIO4.IO25 \ + */ #define SC_P_USDHC1_DATA1 \ 33U /* CONN.USDHC1.DATA1, CONN.NAND.RE_B, ADMA.UART3.TX, LSIO.GPIO4.IO26 */ #define SC_P_USDHC1_DATA2 \ @@ -76,8 +81,9 @@ LSIO.GPIO4.IO29 */ #define SC_P_ENET0_RGMII_TX_CTL \ 38U /* CONN.ENET0.RGMII_TX_CTL, CONN.USDHC1.RESET_B, LSIO.GPIO4.IO30 */ -#define SC_P_ENET0_RGMII_TXD0 39U /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 \ - */ +#define SC_P_ENET0_RGMII_TXD0 \ + 39U /* CONN.ENET0.RGMII_TXD0, CONN.USDHC1.VSELECT, LSIO.GPIO4.IO31 \ + */ #define SC_P_ENET0_RGMII_TXD1 40U /* CONN.ENET0.RGMII_TXD1, CONN.USDHC1.WP, LSIO.GPIO5.IO00 */ #define SC_P_ENET0_RGMII_TXD2 \ 41U /* CONN.ENET0.RGMII_TXD2, CONN.MLB.CLK, CONN.NAND.CE0_B, CONN.USDHC1.CD_B, LSIO.GPIO5.IO01 \ @@ -88,10 +94,11 @@ #define SC_P_ENET0_RGMII_RXC \ 44U /* CONN.ENET0.RGMII_RXC, CONN.MLB.DATA, CONN.NAND.WE_B, CONN.USDHC1.CLK, LSIO.GPIO5.IO03 \ */ -#define SC_P_ENET0_RGMII_RX_CTL 45U /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 \ - */ -#define SC_P_ENET0_RGMII_RXD0 46U /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ -#define SC_P_ENET0_RGMII_RXD1 47U /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ +#define SC_P_ENET0_RGMII_RX_CTL \ + 45U /* CONN.ENET0.RGMII_RX_CTL, CONN.USDHC1.CMD, LSIO.GPIO5.IO04 \ + */ +#define SC_P_ENET0_RGMII_RXD0 46U /* CONN.ENET0.RGMII_RXD0, CONN.USDHC1.DATA0, LSIO.GPIO5.IO05 */ +#define SC_P_ENET0_RGMII_RXD1 47U /* CONN.ENET0.RGMII_RXD1, CONN.USDHC1.DATA1, LSIO.GPIO5.IO06 */ #define SC_P_ENET0_RGMII_RXD2 \ 48U /* CONN.ENET0.RGMII_RXD2, CONN.ENET0.RMII_RX_ER, CONN.USDHC1.DATA2, LSIO.GPIO5.IO07 */ #define SC_P_ENET0_RGMII_RXD3 \ @@ -135,8 +142,9 @@ #define SC_P_SPI3_SCK 69U /* ADMA.SPI3.SCK, ADMA.LCDIF.D13, LSIO.GPIO0.IO13 */ #define SC_P_SPI3_SDO 70U /* ADMA.SPI3.SDO, ADMA.LCDIF.D14, LSIO.GPIO0.IO14 */ #define SC_P_SPI3_SDI 71U /* ADMA.SPI3.SDI, ADMA.LCDIF.D15, LSIO.GPIO0.IO15 */ -#define SC_P_SPI3_CS0 72U /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 \ - */ +#define SC_P_SPI3_CS0 \ + 72U /* ADMA.SPI3.CS0, ADMA.ACM.MCLK_OUT1, ADMA.LCDIF.HSYNC, LSIO.GPIO0.IO16 \ + */ #define SC_P_SPI3_CS1 \ 73U /* ADMA.SPI3.CS1, ADMA.I2C3.SCL, ADMA.LCDIF.RESET, ADMA.SPI2.CS0, ADMA.LCDIF.D16 */ #define SC_P_MCLK_IN1 \ @@ -208,17 +216,21 @@ #define SC_P_UART2_TX 113U /* ADMA.UART2.TX, ADMA.FTM.CH1, ADMA.FLEXCAN1.TX, LSIO.GPIO1.IO23 */ #define SC_P_UART2_RX 114U /* ADMA.UART2.RX, ADMA.FTM.CH0, ADMA.FLEXCAN1.RX, LSIO.GPIO1.IO24 */ #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIOLH 115U /* */ -#define SC_P_MIPI_DSI0_I2C0_SCL 116U /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 \ - */ -#define SC_P_MIPI_DSI0_I2C0_SDA 117U /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 \ - */ +#define SC_P_MIPI_DSI0_I2C0_SCL \ + 116U /* MIPI_DSI0.I2C0.SCL, MIPI_DSI1.GPIO0.IO02, LSIO.GPIO1.IO25 \ + */ +#define SC_P_MIPI_DSI0_I2C0_SDA \ + 117U /* MIPI_DSI0.I2C0.SDA, MIPI_DSI1.GPIO0.IO03, LSIO.GPIO1.IO26 \ + */ #define SC_P_MIPI_DSI0_GPIO0_00 \ 118U /* MIPI_DSI0.GPIO0.IO00, ADMA.I2C1.SCL, MIPI_DSI0.PWM0.OUT, LSIO.GPIO1.IO27 */ #define SC_P_MIPI_DSI0_GPIO0_01 119U /* MIPI_DSI0.GPIO0.IO01, ADMA.I2C1.SDA, LSIO.GPIO1.IO28 */ -#define SC_P_MIPI_DSI1_I2C0_SCL 120U /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 \ - */ -#define SC_P_MIPI_DSI1_I2C0_SDA 121U /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 \ - */ +#define SC_P_MIPI_DSI1_I2C0_SCL \ + 120U /* MIPI_DSI1.I2C0.SCL, MIPI_DSI0.GPIO0.IO02, LSIO.GPIO1.IO29 \ + */ +#define SC_P_MIPI_DSI1_I2C0_SDA \ + 121U /* MIPI_DSI1.I2C0.SDA, MIPI_DSI0.GPIO0.IO03, LSIO.GPIO1.IO30 \ + */ #define SC_P_MIPI_DSI1_GPIO0_00 \ 122U /* MIPI_DSI1.GPIO0.IO00, ADMA.I2C2.SCL, MIPI_DSI1.PWM0.OUT, LSIO.GPIO1.IO31 */ #define SC_P_MIPI_DSI1_GPIO0_01 123U /* MIPI_DSI1.GPIO0.IO01, ADMA.I2C2.SDA, LSIO.GPIO2.IO00 */ @@ -255,21 +267,23 @@ 149U /* CI_PI.RESET, CI_PI.I2C.SDA, ADMA.I2C3.SDA, ADMA.SPI1.CS0, LSIO.GPIO3.IO03 */ #define SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHD 150U /* */ #define SC_P_MIPI_CSI0_MCLK_OUT 151U /* MIPI_CSI0.ACM.MCLK_OUT, LSIO.GPIO3.IO04 */ -#define SC_P_MIPI_CSI0_I2C0_SCL 152U /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 \ - */ -#define SC_P_MIPI_CSI0_I2C0_SDA 153U /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 \ - */ -#define SC_P_MIPI_CSI0_GPIO0_01 154U /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ -#define SC_P_MIPI_CSI0_GPIO0_00 155U /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ -#define SC_P_QSPI0A_DATA0 156U /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ -#define SC_P_QSPI0A_DATA1 157U /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ -#define SC_P_QSPI0A_DATA2 158U /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ -#define SC_P_QSPI0A_DATA3 159U /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ -#define SC_P_QSPI0A_DQS 160U /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ -#define SC_P_QSPI0A_SS0_B 161U /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ -#define SC_P_QSPI0A_SS1_B 162U /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ -#define SC_P_QSPI0A_SCLK 163U /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ -#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164U /* */ +#define SC_P_MIPI_CSI0_I2C0_SCL \ + 152U /* MIPI_CSI0.I2C0.SCL, MIPI_CSI0.GPIO0.IO02, LSIO.GPIO3.IO05 \ + */ +#define SC_P_MIPI_CSI0_I2C0_SDA \ + 153U /* MIPI_CSI0.I2C0.SDA, MIPI_CSI0.GPIO0.IO03, LSIO.GPIO3.IO06 \ + */ +#define SC_P_MIPI_CSI0_GPIO0_01 154U /* MIPI_CSI0.GPIO0.IO01, ADMA.I2C0.SDA, LSIO.GPIO3.IO07 */ +#define SC_P_MIPI_CSI0_GPIO0_00 155U /* MIPI_CSI0.GPIO0.IO00, ADMA.I2C0.SCL, LSIO.GPIO3.IO08 */ +#define SC_P_QSPI0A_DATA0 156U /* LSIO.QSPI0A.DATA0, LSIO.GPIO3.IO09 */ +#define SC_P_QSPI0A_DATA1 157U /* LSIO.QSPI0A.DATA1, LSIO.GPIO3.IO10 */ +#define SC_P_QSPI0A_DATA2 158U /* LSIO.QSPI0A.DATA2, LSIO.GPIO3.IO11 */ +#define SC_P_QSPI0A_DATA3 159U /* LSIO.QSPI0A.DATA3, LSIO.GPIO3.IO12 */ +#define SC_P_QSPI0A_DQS 160U /* LSIO.QSPI0A.DQS, LSIO.GPIO3.IO13 */ +#define SC_P_QSPI0A_SS0_B 161U /* LSIO.QSPI0A.SS0_B, LSIO.GPIO3.IO14 */ +#define SC_P_QSPI0A_SS1_B 162U /* LSIO.QSPI0A.SS1_B, LSIO.GPIO3.IO15 */ +#define SC_P_QSPI0A_SCLK 163U /* LSIO.QSPI0A.SCLK, LSIO.GPIO3.IO16 */ +#define SC_P_COMP_CTL_GPIO_1V8_3V3_QSPI0A 164U /* */ #define SC_P_QSPI0B_SCLK \ 165U /* LSIO.QSPI0B.SCLK, LSIO.QSPI1A.SCLK, LSIO.KPP0.COL0, LSIO.GPIO3.IO17 */ #define SC_P_QSPI0B_DATA0 \ @@ -280,8 +294,9 @@ 168U /* LSIO.QSPI0B.DATA2, LSIO.QSPI1A.DATA2, LSIO.KPP0.COL3, LSIO.GPIO3.IO20 */ #define SC_P_QSPI0B_DATA3 \ 169U /* LSIO.QSPI0B.DATA3, LSIO.QSPI1A.DATA3, LSIO.KPP0.ROW0, LSIO.GPIO3.IO21 */ -#define SC_P_QSPI0B_DQS 170U /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 \ - */ +#define SC_P_QSPI0B_DQS \ + 170U /* LSIO.QSPI0B.DQS, LSIO.QSPI1A.DQS, LSIO.KPP0.ROW1, LSIO.GPIO3.IO22 \ + */ #define SC_P_QSPI0B_SS0_B \ 171U /* LSIO.QSPI0B.SS0_B, LSIO.QSPI1A.SS0_B, LSIO.KPP0.ROW2, LSIO.GPIO3.IO23 */ #define SC_P_QSPI0B_SS1_B \ diff --git a/src/arch/armv7a/include/arch/arch.h b/src/arch/armv7a/include/arch/arch.h index bad3ba24..b2b9598b 100644 --- a/src/arch/armv7a/include/arch/arch.h +++ b/src/arch/armv7a/include/arch/arch.h @@ -447,7 +447,7 @@ /* MAIR macros */ #define MAIR0_ATTR_SET(attr, index) ((attr) << ((index) << U(3))) -#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index)-U(3)) << U(3))) +#define MAIR1_ATTR_SET(attr, index) ((attr) << (((index) - U(3)) << U(3))) /* System register defines The format is: coproc, opt1, CRn, CRm, opt2 */ #define IFSR p15, 0, c5, c0, 1 diff --git a/src/arch/armv8a/include/arch/mmu.h b/src/arch/armv8a/include/arch/mmu.h index 5aa54e8b..e54dd188 100644 --- a/src/arch/armv8a/include/arch/mmu.h +++ b/src/arch/armv8a/include/arch/mmu.h @@ -66,7 +66,7 @@ ((((page_size_shift == 12) & 1) << 1) | ((page_size_shift == 14) & 1) | \ ((page_size_shift == 16) & 1) | (((page_size_shift == 16) & 1) << 1)) -#define MMU_LX_X(page_shift, level) ((4 - (level)) * ((page_shift)-3) + 3) +#define MMU_LX_X(page_shift, level) ((4 - (level)) * ((page_shift) - 3) + 3) #if MMU_USER_SIZE_SHIFT > MMU_LX_X(MMU_USER_PAGE_SIZE_SHIFT, 0) #define MMU_USER_TOP_SHIFT MMU_LX_X(MMU_USER_PAGE_SIZE_SHIFT, 0) diff --git a/src/drivers/fs/lfs.c b/src/drivers/fs/lfs.c index 1ac7d0ee..0f2fdc4a 100644 --- a/src/drivers/fs/lfs.c +++ b/src/drivers/fs/lfs.c @@ -9,8 +9,8 @@ #include #include -#define LFS_BLOCK_NULL ((lfs_block_t)-1) -#define LFS_BLOCK_INLINE ((lfs_block_t)-2) +#define LFS_BLOCK_NULL ((lfs_block_t) - 1) +#define LFS_BLOCK_INLINE ((lfs_block_t) - 2) /// Caching block device operations /// static inline void lfs_cache_drop(lfs_t *lfs, lfs_cache_t *rcache) diff --git a/src/lib/bpak.c b/src/lib/bpak.c index 0dc46fb1..3e6c2bd5 100644 --- a/src/lib/bpak.c +++ b/src/lib/bpak.c @@ -11,7 +11,7 @@ #include /* BPAK_META_ALIGN is a power-of-2 */ -#define BPAK_META_ALIGN_SIZE(_x) (((_x) + ((BPAK_META_ALIGN)-1)) & ~((BPAK_META_ALIGN)-1)) +#define BPAK_META_ALIGN_SIZE(_x) (((_x) + ((BPAK_META_ALIGN) - 1)) & ~((BPAK_META_ALIGN) - 1)) static int bpak_get_meta_int(struct bpak_header *hdr, bpak_id_t id, diff --git a/src/plat/imx6ul/plat.h b/src/plat/imx6ul/plat.h index d26e0a36..9f9f03d9 100644 --- a/src/plat/imx6ul/plat.h +++ b/src/plat/imx6ul/plat.h @@ -10,20 +10,13 @@ #ifndef PLAT_IMX6UL_PLAT_H_ #define PLAT_IMX6UL_PLAT_H_ -#define IMX6UL_FUSE_BANK_WORD(__b, __w, __d) \ - { \ - .bank = __b, .word = __w, .description = __d, .status = FUSE_VALID \ - } +#define IMX6UL_FUSE_BANK_WORD(__b, __w, __d) \ + { .bank = __b, .word = __w, .description = __d, .status = FUSE_VALID } -#define IMX6UL_FUSE_BANK_WORD_VAL(__b, __w, __d, __v) \ - { \ - .bank = __b, .word = __w, .description = __d, .default_value = __v, .status = FUSE_VALID \ - } +#define IMX6UL_FUSE_BANK_WORD_VAL(__b, __w, __d, __v) \ + { .bank = __b, .word = __w, .description = __d, .default_value = __v, .status = FUSE_VALID } -#define IMX6UL_FUSE_END \ - { \ - .status = FUSE_INVALID \ - } +#define IMX6UL_FUSE_END { .status = FUSE_INVALID } #define IMX6UL_PRIV(__p) ((struct imx6ul_private *)__p) diff --git a/src/plat/imx8m/plat.h b/src/plat/imx8m/plat.h index 68252f5f..35158e13 100644 --- a/src/plat/imx8m/plat.h +++ b/src/plat/imx8m/plat.h @@ -10,20 +10,13 @@ #ifndef PLAT_IMX8M_PLAT_H_ #define PLAT_IMX8M_PLAT_H_ -#define IMX8M_FUSE_BANK_WORD(__b, __w, __d) \ - { \ - .bank = __b, .word = __w, .description = __d, .status = FUSE_VALID \ - } +#define IMX8M_FUSE_BANK_WORD(__b, __w, __d) \ + { .bank = __b, .word = __w, .description = __d, .status = FUSE_VALID } -#define IMX8M_FUSE_BANK_WORD_VAL(__b, __w, __d, __v) \ - { \ - .bank = __b, .word = __w, .description = __d, .default_value = __v, .status = FUSE_VALID \ - } +#define IMX8M_FUSE_BANK_WORD_VAL(__b, __w, __d, __v) \ + { .bank = __b, .word = __w, .description = __d, .default_value = __v, .status = FUSE_VALID } -#define IMX8M_FUSE_END \ - { \ - .status = FUSE_INVALID \ - } +#define IMX8M_FUSE_END { .status = FUSE_INVALID } #define IMX8M_PRIV(__p) ((struct imx8m_private *)__p) diff --git a/src/plat/qemu/gcov.c b/src/plat/qemu/gcov.c index 7a667d78..4bd74875 100644 --- a/src/plat/qemu/gcov.c +++ b/src/plat/qemu/gcov.c @@ -274,8 +274,8 @@ void gcov_init(void) { /* Call gcov initalizers */ extern uint32_t __init_array_start, __init_array_end; - void (**pctor)(void) = (void (**)(void)) & __init_array_start; - void (**pctor_last)(void) = (void (**)(void)) & __init_array_end; + void (**pctor)(void) = (void (**)(void))&__init_array_start; + void (**pctor_last)(void) = (void (**)(void))&__init_array_end; for (; pctor < pctor_last; pctor++) { (*pctor)(); diff --git a/tools/punchboot/punchboot/__init__.py b/tools/punchboot/punchboot/__init__.py index 90635674..f704cf42 100644 --- a/tools/punchboot/punchboot/__init__.py +++ b/tools/punchboot/punchboot/__init__.py @@ -48,13 +48,13 @@ ] __all__ = [ - "Session", + "SLC", "Partition", "PartitionFlags", - "SLC", + "Session", "library_version", + "list_usb_devices", "pb_id", "wait_for_device", - "list_usb_devices", ] __all__ += _pb_exceptions diff --git a/tools/punchboot/punchboot/partition.py b/tools/punchboot/punchboot/partition.py index b7bd0ae7..271defdf 100644 --- a/tools/punchboot/punchboot/partition.py +++ b/tools/punchboot/punchboot/partition.py @@ -2,7 +2,7 @@ from __future__ import annotations -import uuid # noqa: TCH003 +import uuid # noqa: TC003 from dataclasses import dataclass from enum import Flag diff --git a/tools/punchboot/punchboot/session.py b/tools/punchboot/punchboot/session.py index 28fbf158..43d768ac 100644 --- a/tools/punchboot/punchboot/session.py +++ b/tools/punchboot/punchboot/session.py @@ -365,8 +365,7 @@ def device_reset(self) -> None: def device_get_punchboot_version(self) -> semver.Version: """Read the punchboot version.""" ver_str: str = self.pb_s.device_get_punchboot_version() - if ver_str.startswith("v"): - ver_str = ver_str[1:] + ver_str = ver_str.removeprefix("v") return semver.Version.parse(ver_str) def device_get_uuid(self) -> uuid.UUID: