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Contains Matlab Script for image pre-processing and Verilog Code for Image denoising using median filtering
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matlab/Image_Pre_Processing.m

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k=rgb2gray(imread('test.png'));
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J = imnoise(k,'salt & pepper',0.2);
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figure,imshow(k)
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figure,imshow(J)
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im=zeros(size(k)+2);
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B=zeros(size(k));
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for x=1:size(k,1)
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for y=1:size(k,2)
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im(x+1,y+1)=J(x,y);
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end
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end
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fid=fopen('image.txt','w')
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for x=1:size(im,1)
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for y=1:size(im,2)
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fprintf(fid,'%s',dec2bin(im(x,y)));
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fprintf(fid,'\n');
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end
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end
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fclose(fid);

src/Compare.v

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module compare(a,b,out1);
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input [7:0]a;
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input [7:0]b;
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output out1;
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reg out1;
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always@(a,b)
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begin
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if(a<b)
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out1=1'b1;
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else
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out1=1'b0;
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end
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endmodule

src/Median_Filtering.v

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module median(s1,s2,s3,s4,s5,s6,s7,s8,s9,med);
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input [7:0]s1,s2,s3,s4,s5,s6,s7,s8,s9;
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output [7:0]med;
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wire [7:0]p1,p2,p3,p4,p5,p6,p7,p8,p9;
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sort9 a1(s1,s2,s3,s4,s5,s6,s7,s8,s9,p1,p2,p3,p4,p5,p6,p7,p8,p9);
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assign med=p5;
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endmodule
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src/Mux.v

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module mux(a,b,s,out1);
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input [7:0]a;
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input [7:0]b;
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input s;
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output [7:0]out1;
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reg [7:0]out1;
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always@(a,b,s)
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begin
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if(s==1'b1)
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out1=a;
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else
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out1=b;
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end
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endmodule

src/Sorter_2.v

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module sorter_2(a,b,min,max);
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input [7:0]a;
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input [7:0]b;
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output [7:0]min;
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output [7:0]max;
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wire cmp;
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compare c1(a,b,cmp);
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mux m1(a,b,cmp,min);
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mux m2(b,a,cmp,max);
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endmodule

src/Sorter_4.v

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module sort4(i1,i2,i3,i4,o1,o2,o3,o4);
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input [7:0]i1,i2,i3,i4;
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output [7:0]o1,o2,o3,o4;
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wire [7:0]m1,m2,m3,m4,w1,w2,w3,w4;
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sorter_2 a41a(i1,i2,m1,w1);
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sorter_2 ar1a(i3,i4,m2,w2);
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sorter_2 a2f1a(m1,m2,o1,w3);
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sorter_2 a3d1a(w1,w2,m4,o4);
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sorter_2 a3d1na(w3,m4,o2,o3);
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endmodule

src/Sorter_9.v

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module sort9(in1,in2,in3,in4,in5,in6,in7,in8,in9,out1,out2,out3,out4,out5,out6,out7,out8,out9);
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input [7:0] in1,in2,in3,in4,in5,in6,in7,in8,in9;
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output [7:0] out1,out2,out3,out4,out5,out6,out7,out8,out9;
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wire [7:0]w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16;
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wire [7:0]m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,m16,l1,l2,l3,l4,l5,l6,l7;
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wire [7:0]in11,in22,in33,in44,in55,in66,in77,in88;
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sort4 j1(in1,in2,in3,in4,in11,in22,in33,in44);
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sort4 hj(in5,in6,in7,in8,in88,in77,in66,in55);
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sorter_2 a1(in11,in55,m1,w1);
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sorter_2 af(in33,in77,m2,w2);
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sorter_2 a2(in22,in66,m3,w3);
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sorter_2 a3(in44,in88,m4,w4);
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///////////////////stage 1 finished//////////////////////
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sorter_2 a4(w1,w2,m5,w5);
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sorter_2 ar(m1,m2,m6,w6);
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sorter_2 a2f(w3,w4,m7,w7);
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sorter_2 a3d(m3,m4,m8,w8);
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///////////////////stage 2///////////////////////
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sorter_2 a41(w5,w7,m9,w9);
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sorter_2 ar1(m5,m7,m10,w10);
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sorter_2 a2f1(w6,w8,m11,w11);
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sorter_2 a3d1(m6,m8,m12,w12);
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sorter_2 a3d12(m12,in9,out1,l1);
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sorter_2 a3d13(l1,w12,out2,l2);
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sorter_2 a3d1d(l2,m11,out3,l3);
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sorter_2 a3d1s(l3,w11,out4,l4);
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sorter_2 a3d1dd(l4,m10,out5,l5);
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sorter_2 a3d1ss(l5,w10,out6,l6);
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sorter_2 a3d1v(l6,m9,out7,l7);
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sorter_2 a3dg1(l7,w9,out8,out9);
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//////////////////stage 3///////////////////
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//assign out1=m12;
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//assign out2=w12;
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//assign out3=m11;
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//assign out4=w11;
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//assign out5=m10;
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//assign out6=w10;
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//assign out7=m9;
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//assign out8=w9;
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endmodule

tb/Testbench.v

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////////////////////////////////testbench below/////////////////////////////////////
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module denois;
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reg unsigned [7:0]img[10000:1];
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wire unsigned [7:0]new;
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integer i,file_id,file_id1,j,k;
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reg clk;
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initial
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begin
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file_id=$fopen("denoised_image.txt");
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file_id1=$fopen("fin.txt");
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$readmemb("img.txt",img);
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end
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initial
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begin
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i=0;
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j=0;
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k=1;
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clk=1'b0;
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end
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always
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begin
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#10;
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clk=~clk;
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end
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always@(posedge(clk))
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begin
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i=i+1;
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j=j+1;
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#10 $fdisplay(file_id,"%d",new);
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end
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always@(i,j)
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begin
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if(j==99) begin
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i=100*k +1;
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j=1;
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k=k+1;
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if(k==99) begin $fclose(file_id);
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#1000000 $fdisplay(file_id1,"%d",1'd0);
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$fclose(file_id1);
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end
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end
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end
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median ma(img[i],img[i+1],img[i+2],img[i+100],img[i+101],img[i+102],img[i+200],img[i+201],img[i+202],new);
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endmodule
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//////////////////////////////////////////////////end///////////////////////////////////////

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