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| 1 | +module sort9(in1,in2,in3,in4,in5,in6,in7,in8,in9,out1,out2,out3,out4,out5,out6,out7,out8,out9); |
| 2 | +input [7:0] in1,in2,in3,in4,in5,in6,in7,in8,in9; |
| 3 | +output [7:0] out1,out2,out3,out4,out5,out6,out7,out8,out9; |
| 4 | +wire [7:0]w1,w2,w3,w4,w5,w6,w7,w8,w9,w10,w11,w12,w13,w14,w15,w16; |
| 5 | +wire [7:0]m1,m2,m3,m4,m5,m6,m7,m8,m9,m10,m11,m12,m13,m14,m15,m16,l1,l2,l3,l4,l5,l6,l7; |
| 6 | +wire [7:0]in11,in22,in33,in44,in55,in66,in77,in88; |
| 7 | + |
| 8 | +sort4 j1(in1,in2,in3,in4,in11,in22,in33,in44); |
| 9 | +sort4 hj(in5,in6,in7,in8,in88,in77,in66,in55); |
| 10 | +sorter_2 a1(in11,in55,m1,w1); |
| 11 | +sorter_2 af(in33,in77,m2,w2); |
| 12 | +sorter_2 a2(in22,in66,m3,w3); |
| 13 | +sorter_2 a3(in44,in88,m4,w4); |
| 14 | +///////////////////stage 1 finished////////////////////// |
| 15 | +sorter_2 a4(w1,w2,m5,w5); |
| 16 | +sorter_2 ar(m1,m2,m6,w6); |
| 17 | +sorter_2 a2f(w3,w4,m7,w7); |
| 18 | +sorter_2 a3d(m3,m4,m8,w8); |
| 19 | +///////////////////stage 2/////////////////////// |
| 20 | +sorter_2 a41(w5,w7,m9,w9); |
| 21 | +sorter_2 ar1(m5,m7,m10,w10); |
| 22 | +sorter_2 a2f1(w6,w8,m11,w11); |
| 23 | +sorter_2 a3d1(m6,m8,m12,w12); |
| 24 | + |
| 25 | +sorter_2 a3d12(m12,in9,out1,l1); |
| 26 | +sorter_2 a3d13(l1,w12,out2,l2); |
| 27 | +sorter_2 a3d1d(l2,m11,out3,l3); |
| 28 | +sorter_2 a3d1s(l3,w11,out4,l4); |
| 29 | +sorter_2 a3d1dd(l4,m10,out5,l5); |
| 30 | +sorter_2 a3d1ss(l5,w10,out6,l6); |
| 31 | +sorter_2 a3d1v(l6,m9,out7,l7); |
| 32 | +sorter_2 a3dg1(l7,w9,out8,out9); |
| 33 | + |
| 34 | + |
| 35 | + |
| 36 | + |
| 37 | + |
| 38 | +//////////////////stage 3/////////////////// |
| 39 | +//assign out1=m12; |
| 40 | +//assign out2=w12; |
| 41 | +//assign out3=m11; |
| 42 | +//assign out4=w11; |
| 43 | +//assign out5=m10; |
| 44 | +//assign out6=w10; |
| 45 | +//assign out7=m9; |
| 46 | +//assign out8=w9; |
| 47 | +endmodule |
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