Skip to content

Commit 4dbd16b

Browse files
mssefatmssefat
authored
[AMDGPU][GlobalISel] Add register bank legalization for buffer_load byte and short (#167798)
This patch adds register bank legalization support for buffer load byte and short operations in the AMDGPU GlobalISel pipeline.
1 parent ff3dcd0 commit 4dbd16b

File tree

6 files changed

+267
-8
lines changed

6 files changed

+267
-8
lines changed

‎llvm/lib/Target/AMDGPU/AMDGPURegBankLegalizeRules.cpp‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -889,6 +889,12 @@ RegBankLegalizeRules::RegBankLegalizeRules(const GCNSubtarget &_ST,
889889
.Div(B128, {{VgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}})
890890
.Uni(B128, {{UniInVgprB128}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}});
891891

892+
addRulesForGOpcs({G_AMDGPU_BUFFER_LOAD_USHORT, G_AMDGPU_BUFFER_LOAD_UBYTE,
893+
G_AMDGPU_BUFFER_LOAD_SSHORT, G_AMDGPU_BUFFER_LOAD_SBYTE},
894+
StandardB)
895+
.Div(B32, {{VgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}})
896+
.Uni(B32, {{UniInVgprB32}, {SgprV4S32_WF, Vgpr32, Vgpr32, Sgpr32_WF}});
897+
892898
addRulesForGOpcs({G_AMDGPU_BUFFER_STORE})
893899
.Any({{S32}, {{}, {Vgpr32, SgprV4S32, Vgpr32, Vgpr32, Sgpr32}}});
894900

‎llvm/test/CodeGen/AMDGPU/GlobalISel/buffer-load-byte-short.ll‎

Lines changed: 253 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,253 @@
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
2+
; RUN: llc -mtriple=amdgcn-amd-amdhsa -global-isel -new-reg-bank-select -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s
3+
4+
define amdgpu_ps void @test_buffer_load_u8_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
5+
; GFX12-LABEL: test_buffer_load_u8_uniform:
6+
; GFX12: ; %bb.0:
7+
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
8+
; GFX12-NEXT: s_mov_b32 s10, s7
9+
; GFX12-NEXT: s_mov_b32 s11, s8
10+
; GFX12-NEXT: buffer_load_u8 v0, v0, s[0:3], s5 offen
11+
; GFX12-NEXT: s_wait_loadcnt 0x0
12+
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
13+
; GFX12-NEXT: s_add_co_i32 s0, s0, s6
14+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
15+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
16+
; GFX12-NEXT: global_store_b32 v1, v0, s[10:11]
17+
; GFX12-NEXT: s_endpgm
18+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
19+
%zext = zext i8 %val to i32
20+
%result = add i32 %zext, %addend
21+
store i32 %result, ptr addrspace(1) %out
22+
ret void
23+
}
24+
25+
define amdgpu_ps void @test_buffer_load_i8_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
26+
; GFX12-LABEL: test_buffer_load_i8_uniform:
27+
; GFX12: ; %bb.0:
28+
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
29+
; GFX12-NEXT: s_mov_b32 s10, s7
30+
; GFX12-NEXT: s_mov_b32 s11, s8
31+
; GFX12-NEXT: buffer_load_i8 v0, v0, s[0:3], s5 offen
32+
; GFX12-NEXT: s_wait_loadcnt 0x0
33+
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
34+
; GFX12-NEXT: s_add_co_i32 s0, s0, s6
35+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
36+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
37+
; GFX12-NEXT: global_store_b32 v1, v0, s[10:11]
38+
; GFX12-NEXT: s_endpgm
39+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
40+
%sext = sext i8 %val to i32
41+
%result = add i32 %sext, %addend
42+
store i32 %result, ptr addrspace(1) %out
43+
ret void
44+
}
45+
46+
define amdgpu_ps void @test_buffer_load_u16_uniform(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
47+
; GFX12-LABEL: test_buffer_load_u16_uniform:
48+
; GFX12: ; %bb.0:
49+
; GFX12-NEXT: buffer_load_u16 v0, off, s[0:3], s4
50+
; GFX12-NEXT: v_mov_b32_e32 v1, 0
51+
; GFX12-NEXT: s_wait_loadcnt 0x0
52+
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
53+
; GFX12-NEXT: s_add_co_i32 s0, s0, s5
54+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
55+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
56+
; GFX12-NEXT: global_store_b32 v1, v0, s[6:7]
57+
; GFX12-NEXT: s_endpgm
58+
%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
59+
%zext = zext i16 %val to i32
60+
%result = add i32 %zext, %addend
61+
store i32 %result, ptr addrspace(1) %out
62+
ret void
63+
}
64+
65+
define amdgpu_ps void @test_buffer_load_i16_uniform(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, i32 inreg %addend, ptr addrspace(1) inreg %out) {
66+
; GFX12-LABEL: test_buffer_load_i16_uniform:
67+
; GFX12: ; %bb.0:
68+
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
69+
; GFX12-NEXT: s_mov_b32 s10, s7
70+
; GFX12-NEXT: s_mov_b32 s11, s8
71+
; GFX12-NEXT: buffer_load_i16 v0, v0, s[0:3], null offen
72+
; GFX12-NEXT: s_wait_loadcnt 0x0
73+
; GFX12-NEXT: v_readfirstlane_b32 s0, v0
74+
; GFX12-NEXT: s_add_co_i32 s0, s0, s6
75+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
76+
; GFX12-NEXT: v_mov_b32_e32 v0, s0
77+
; GFX12-NEXT: global_store_b32 v1, v0, s[10:11]
78+
; GFX12-NEXT: s_endpgm
79+
%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
80+
%sext = sext i16 %val to i32
81+
%result = add i32 %sext, %addend
82+
store i32 %result, ptr addrspace(1) %out
83+
ret void
84+
}
85+
86+
define amdgpu_ps void @test_buffer_load_u8_divergent(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
87+
; GFX12-LABEL: test_buffer_load_u8_divergent:
88+
; GFX12: ; %bb.0:
89+
; GFX12-NEXT: buffer_load_u8 v0, v0, s[0:3], s4 offen
90+
; GFX12-NEXT: v_mov_b32_e32 v1, 0
91+
; GFX12-NEXT: s_mov_b32 s8, s5
92+
; GFX12-NEXT: s_mov_b32 s9, s6
93+
; GFX12-NEXT: s_wait_loadcnt 0x0
94+
; GFX12-NEXT: global_store_b32 v1, v0, s[8:9]
95+
; GFX12-NEXT: s_endpgm
96+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
97+
%zext = zext i8 %val to i32
98+
store i32 %zext, ptr addrspace(1) %out
99+
ret void
100+
}
101+
102+
define amdgpu_ps void @test_buffer_load_i8_divergent(<4 x i32> inreg %rsrc, i32 inreg %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
103+
; GFX12-LABEL: test_buffer_load_i8_divergent:
104+
; GFX12: ; %bb.0:
105+
; GFX12-NEXT: v_dual_mov_b32 v0, s4 :: v_dual_mov_b32 v1, 0
106+
; GFX12-NEXT: buffer_load_i8 v0, v0, s[0:3], s5 offen
107+
; GFX12-NEXT: s_wait_loadcnt 0x0
108+
; GFX12-NEXT: global_store_b32 v1, v0, s[6:7]
109+
; GFX12-NEXT: s_endpgm
110+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
111+
%sext = sext i8 %val to i32
112+
store i32 %sext, ptr addrspace(1) %out
113+
ret void
114+
}
115+
116+
define amdgpu_ps void @test_buffer_load_u16_divergent(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
117+
; GFX12-LABEL: test_buffer_load_u16_divergent:
118+
; GFX12: ; %bb.0:
119+
; GFX12-NEXT: buffer_load_u16 v0, off, s[0:3], s4
120+
; GFX12-NEXT: v_mov_b32_e32 v1, 0
121+
; GFX12-NEXT: s_mov_b32 s8, s5
122+
; GFX12-NEXT: s_mov_b32 s9, s6
123+
; GFX12-NEXT: s_wait_loadcnt 0x0
124+
; GFX12-NEXT: global_store_b32 v1, v0, s[8:9]
125+
; GFX12-NEXT: s_endpgm
126+
%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 0, i32 %soffset, i32 0)
127+
%zext = zext i16 %val to i32
128+
store i32 %zext, ptr addrspace(1) %out
129+
ret void
130+
}
131+
132+
define amdgpu_ps void @test_buffer_load_i16_divergent(<4 x i32> inreg %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
133+
; GFX12-LABEL: test_buffer_load_i16_divergent:
134+
; GFX12: ; %bb.0:
135+
; GFX12-NEXT: buffer_load_i16 v0, v0, s[0:3], null offen
136+
; GFX12-NEXT: v_mov_b32_e32 v1, 0
137+
; GFX12-NEXT: s_mov_b32 s4, s5
138+
; GFX12-NEXT: s_mov_b32 s5, s6
139+
; GFX12-NEXT: s_wait_loadcnt 0x0
140+
; GFX12-NEXT: global_store_b32 v1, v0, s[4:5]
141+
; GFX12-NEXT: s_endpgm
142+
%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 0, i32 0)
143+
%sext = sext i16 %val to i32
144+
store i32 %sext, ptr addrspace(1) %out
145+
ret void
146+
}
147+
148+
define amdgpu_ps void @test_buffer_load_u8_waterfall_rsrc(<4 x i32> %rsrc, i32 %voffset, i32 inreg %soffset, ptr addrspace(1) inreg %out) {
149+
; GFX12-LABEL: test_buffer_load_u8_waterfall_rsrc:
150+
; GFX12: ; %bb.0:
151+
; GFX12-NEXT: s_mov_b32 s8, s1
152+
; GFX12-NEXT: s_mov_b32 s9, s2
153+
; GFX12-NEXT: s_mov_b32 s2, exec_lo
154+
; GFX12-NEXT: .LBB8_1: ; =>This Inner Loop Header: Depth=1
155+
; GFX12-NEXT: v_readfirstlane_b32 s4, v0
156+
; GFX12-NEXT: s_wait_loadcnt 0x0
157+
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
158+
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
159+
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
160+
; GFX12-NEXT: s_wait_alu 0xf1ff
161+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
162+
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
163+
; GFX12-NEXT: v_cmp_eq_u64_e64 s1, s[6:7], v[2:3]
164+
; GFX12-NEXT: s_and_b32 s1, vcc_lo, s1
165+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
166+
; GFX12-NEXT: s_and_saveexec_b32 s1, s1
167+
; GFX12-NEXT: buffer_load_u8 v1, v4, s[4:7], s0 offen
168+
; GFX12-NEXT: ; implicit-def: $vgpr0
169+
; GFX12-NEXT: ; implicit-def: $vgpr4
170+
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
171+
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s1
172+
; GFX12-NEXT: s_cbranch_execnz .LBB8_1
173+
; GFX12-NEXT: ; %bb.2:
174+
; GFX12-NEXT: s_mov_b32 exec_lo, s2
175+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
176+
; GFX12-NEXT: s_wait_loadcnt 0x0
177+
; GFX12-NEXT: global_store_b32 v0, v1, s[8:9]
178+
; GFX12-NEXT: s_endpgm
179+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
180+
%zext = zext i8 %val to i32
181+
store i32 %zext, ptr addrspace(1) %out
182+
ret void
183+
}
184+
185+
define amdgpu_ps void @test_buffer_load_i8_waterfall_soffset(<4 x i32> inreg %rsrc, i32 %voffset, i32 %soffset, ptr addrspace(1) inreg %out) {
186+
; GFX12-LABEL: test_buffer_load_i8_waterfall_soffset:
187+
; GFX12: ; %bb.0:
188+
; GFX12-NEXT: s_mov_b32 s6, exec_lo
189+
; GFX12-NEXT: .LBB9_1: ; =>This Inner Loop Header: Depth=1
190+
; GFX12-NEXT: v_readfirstlane_b32 s8, v1
191+
; GFX12-NEXT: s_mov_b32 s7, exec_lo
192+
; GFX12-NEXT: s_wait_alu 0xf1ff
193+
; GFX12-NEXT: v_cmpx_eq_u32_e64 s8, v1
194+
; GFX12-NEXT: s_wait_loadcnt 0x0
195+
; GFX12-NEXT: buffer_load_i8 v2, v0, s[0:3], s8 offen
196+
; GFX12-NEXT: ; implicit-def: $vgpr1
197+
; GFX12-NEXT: ; implicit-def: $vgpr0
198+
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s7
199+
; GFX12-NEXT: s_cbranch_execnz .LBB9_1
200+
; GFX12-NEXT: ; %bb.2:
201+
; GFX12-NEXT: s_mov_b32 exec_lo, s6
202+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
203+
; GFX12-NEXT: s_wait_loadcnt 0x0
204+
; GFX12-NEXT: global_store_b32 v0, v2, s[4:5]
205+
; GFX12-NEXT: s_endpgm
206+
%val = call i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
207+
%sext = sext i8 %val to i32
208+
store i32 %sext, ptr addrspace(1) %out
209+
ret void
210+
}
211+
212+
define amdgpu_ps void @test_buffer_load_u16_waterfall_both(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, ptr addrspace(1) inreg %out) {
213+
; GFX12-LABEL: test_buffer_load_u16_waterfall_both:
214+
; GFX12: ; %bb.0:
215+
; GFX12-NEXT: s_mov_b32 s8, exec_lo
216+
; GFX12-NEXT: .LBB10_1: ; =>This Inner Loop Header: Depth=1
217+
; GFX12-NEXT: v_readfirstlane_b32 s4, v0
218+
; GFX12-NEXT: s_wait_loadcnt 0x0
219+
; GFX12-NEXT: v_readfirstlane_b32 s5, v1
220+
; GFX12-NEXT: v_readfirstlane_b32 s6, v2
221+
; GFX12-NEXT: v_readfirstlane_b32 s7, v3
222+
; GFX12-NEXT: v_readfirstlane_b32 s9, v5
223+
; GFX12-NEXT: s_wait_alu 0xf1ff
224+
; GFX12-NEXT: v_cmp_eq_u64_e32 vcc_lo, s[4:5], v[0:1]
225+
; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
226+
; GFX12-NEXT: v_cmp_eq_u64_e64 s2, s[6:7], v[2:3]
227+
; GFX12-NEXT: v_cmp_eq_u32_e64 s3, s9, v5
228+
; GFX12-NEXT: s_and_b32 s2, vcc_lo, s2
229+
; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
230+
; GFX12-NEXT: s_and_b32 s2, s2, s3
231+
; GFX12-NEXT: s_and_saveexec_b32 s2, s2
232+
; GFX12-NEXT: buffer_load_u16 v1, v4, s[4:7], s9 offen
233+
; GFX12-NEXT: ; implicit-def: $vgpr0
234+
; GFX12-NEXT: ; implicit-def: $vgpr5
235+
; GFX12-NEXT: ; implicit-def: $vgpr4
236+
; GFX12-NEXT: ; implicit-def: $vgpr2_vgpr3
237+
; GFX12-NEXT: s_xor_b32 exec_lo, exec_lo, s2
238+
; GFX12-NEXT: s_cbranch_execnz .LBB10_1
239+
; GFX12-NEXT: ; %bb.2:
240+
; GFX12-NEXT: s_mov_b32 exec_lo, s8
241+
; GFX12-NEXT: v_mov_b32_e32 v0, 0
242+
; GFX12-NEXT: s_wait_loadcnt 0x0
243+
; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]
244+
; GFX12-NEXT: s_endpgm
245+
%val = call i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32> %rsrc, i32 %voffset, i32 %soffset, i32 0)
246+
%zext = zext i16 %val to i32
247+
store i32 %zext, ptr addrspace(1) %out
248+
ret void
249+
}
250+
251+
declare i8 @llvm.amdgcn.raw.buffer.load.i8(<4 x i32>, i32, i32, i32 immarg) #0
252+
declare i16 @llvm.amdgcn.raw.buffer.load.i16(<4 x i32>, i32, i32, i32 immarg) #0
253+
attributes #0 = { nounwind readonly willreturn }

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.buffer.load.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX8 %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX8 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1200 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefixes=GFX12,GFX1250 %s
55
; FIXME: Test with SI when argument lowering not broken for f16
66

77
; Natural mapping

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.raw.ptr.buffer.load.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
33
; FIXME: Test with SI when argument lowering not broken for f16
44

55
; Natural mapping

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.buffer.load.ll‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
3-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s
4-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX8 %s
3+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1200 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1200 %s
4+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1250 -stop-after=instruction-select -o - %s | FileCheck -check-prefix=GFX1250 %s
55

66
; Natural mapping
77
define amdgpu_ps float @struct_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(<4 x i32> inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

‎llvm/test/CodeGen/AMDGPU/GlobalISel/llvm.amdgcn.struct.ptr.buffer.load.ll‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
2+
; RUN: llc -global-isel -new-reg-bank-select -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -stop-after=instruction-select -o - %s | FileCheck %s
33

44
; Natural mapping
55
define amdgpu_ps float @struct_ptr_buffer_load_f32__sgpr_rsrc__vgpr_vindex__vgpr_voffset__sgpr_soffset(ptr addrspace(8) inreg %rsrc, i32 %vindex, i32 %voffset, i32 inreg %soffset) {

0 commit comments

Comments
 (0)