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[LV] Avoid redundant SCEVChecks on active lane mask
When using an active lane mask, all SCEVChecks except those for stride-versioning are redundant.
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5 files changed

+72
-201
lines changed

5 files changed

+72
-201
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp‎

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1819,7 +1819,8 @@ class GeneratedRTChecks {
18191819
/// there is no vector code generation, the check blocks are removed
18201820
/// completely.
18211821
void create(Loop *L, const LoopAccessInfo &LAI,
1822-
const SCEVPredicate &UnionPred, ElementCount VF, unsigned IC) {
1822+
const SCEVPredicate &UnionPred, ElementCount VF, unsigned IC,
1823+
bool UseActiveLaneMask) {
18231824

18241825
// Hard cutoff to limit compile-time increase in case a very large number of
18251826
// runtime checks needs to be generated.
@@ -1837,7 +1838,8 @@ class GeneratedRTChecks {
18371838
// ensure the blocks are properly added to LoopInfo & DominatorTree. Those
18381839
// may be used by SCEVExpander. The blocks will be un-linked from their
18391840
// predecessors and removed from LI & DT at the end of the function.
1840-
if (!UnionPred.isAlwaysTrue()) {
1841+
if (!UnionPred.isAlwaysTrue() &&
1842+
(!UseActiveLaneMask || !LAI.getSymbolicStrides().empty())) {
18411843
SCEVCheckBlock = SplitBlock(Preheader, Preheader->getTerminator(), DT, LI,
18421844
nullptr, "vector.scevcheck");
18431845

@@ -10094,7 +10096,8 @@ bool LoopVectorizePass::processLoop(Loop *L) {
1009410096
// Optimistically generate runtime checks if they are needed. Drop them if
1009510097
// they turn out to not be profitable.
1009610098
if (VF.Width.isVector() || SelectedIC > 1) {
10097-
Checks.create(L, *LVL.getLAI(), PSE.getPredicate(), VF.Width, SelectedIC);
10099+
Checks.create(L, *LVL.getLAI(), PSE.getPredicate(), VF.Width, SelectedIC,
10100+
useActiveLaneMask(CM.getTailFoldingStyle()));
1009810101

1009910102
// Bail out early if either the SCEV or memory runtime checks are known to
1010010103
// fail. In that case, the vector loop would never execute.

‎llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll‎

Lines changed: 37 additions & 60 deletions
Original file line numberDiff line numberDiff line change
@@ -840,41 +840,17 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
840840
; PRED-SAME: ptr noalias [[SRC_1:%.*]], ptr noalias [[SRC_2:%.*]], ptr noalias [[SRC_3:%.*]], ptr noalias [[SRC_4:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR3:[0-9]+]] {
841841
; PRED-NEXT: [[ENTRY:.*:]]
842842
; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1
843-
; PRED-NEXT: br label %[[VECTOR_SCEVCHECK:.*]]
844-
; PRED: [[VECTOR_SCEVCHECK]]:
845-
; PRED-NEXT: [[MUL:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])
846-
; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i64, i1 } [[MUL]], 0
847-
; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i64, i1 } [[MUL]], 1
848-
; PRED-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[MUL_RESULT]]
849-
; PRED-NEXT: [[TMP3:%.*]] = icmp ult ptr [[TMP2]], [[DST]]
850-
; PRED-NEXT: [[TMP4:%.*]] = or i1 [[TMP3]], [[MUL_OVERFLOW]]
851-
; PRED-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 4
852-
; PRED-NEXT: [[MUL1:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])
853-
; PRED-NEXT: [[MUL_RESULT2:%.*]] = extractvalue { i64, i1 } [[MUL1]], 0
854-
; PRED-NEXT: [[MUL_OVERFLOW3:%.*]] = extractvalue { i64, i1 } [[MUL1]], 1
855-
; PRED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT2]]
856-
; PRED-NEXT: [[TMP7:%.*]] = icmp ult ptr [[TMP6]], [[SCEVGEP]]
857-
; PRED-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW3]]
858-
; PRED-NEXT: [[SCEVGEP4:%.*]] = getelementptr i8, ptr [[DST]], i64 8
859-
; PRED-NEXT: [[MUL5:%.*]] = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 16, i64 [[N]])
860-
; PRED-NEXT: [[MUL_RESULT6:%.*]] = extractvalue { i64, i1 } [[MUL5]], 0
861-
; PRED-NEXT: [[MUL_OVERFLOW7:%.*]] = extractvalue { i64, i1 } [[MUL5]], 1
862-
; PRED-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[SCEVGEP4]], i64 [[MUL_RESULT6]]
863-
; PRED-NEXT: [[TMP11:%.*]] = icmp ult ptr [[TMP10]], [[SCEVGEP4]]
864-
; PRED-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW7]]
865-
; PRED-NEXT: [[TMP13:%.*]] = or i1 [[TMP4]], [[TMP8]]
866-
; PRED-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[TMP12]]
867-
; PRED-NEXT: br i1 [[TMP14]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
843+
; PRED-NEXT: br label %[[VECTOR_PH:.*]]
868844
; PRED: [[VECTOR_PH]]:
869845
; PRED-NEXT: [[TMP15:%.*]] = sub i64 [[TMP0]], 8
870846
; PRED-NEXT: [[TMP16:%.*]] = icmp ugt i64 [[TMP0]], 8
871847
; PRED-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i64 [[TMP15]], i64 0
872848
; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 0, i64 [[TMP0]])
873849
; PRED-NEXT: br label %[[VECTOR_BODY:.*]]
874850
; PRED: [[VECTOR_BODY]]:
875-
; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE27:.*]] ]
876-
; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <8 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[PRED_STORE_CONTINUE27]] ]
877-
; PRED-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE27]] ]
851+
; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[PRED_STORE_CONTINUE20:.*]] ]
852+
; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <8 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], %[[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], %[[PRED_STORE_CONTINUE20]] ]
853+
; PRED-NEXT: [[VEC_IND:%.*]] = phi <8 x i64> [ <i64 0, i64 1, i64 2, i64 3, i64 4, i64 5, i64 6, i64 7>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[PRED_STORE_CONTINUE20]] ]
878854
; PRED-NEXT: [[TMP18:%.*]] = load float, ptr [[SRC_1]], align 4
879855
; PRED-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <8 x float> poison, float [[TMP18]], i64 0
880856
; PRED-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT8]], <8 x float> poison, <8 x i32> zeroinitializer
@@ -909,8 +885,8 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
909885
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE]]
910886
; PRED: [[PRED_STORE_CONTINUE]]:
911887
; PRED-NEXT: [[TMP35:%.*]] = extractelement <8 x i1> [[TMP26]], i32 1
912-
; PRED-NEXT: br i1 [[TMP35]], label %[[PRED_STORE_IF14:.*]], label %[[PRED_STORE_CONTINUE15:.*]]
913-
; PRED: [[PRED_STORE_IF14]]:
888+
; PRED-NEXT: br i1 [[TMP35]], label %[[PRED_STORE_IF7:.*]], label %[[PRED_STORE_CONTINUE8:.*]]
889+
; PRED: [[PRED_STORE_IF7]]:
914890
; PRED-NEXT: [[TMP36:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1
915891
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP36]], align 4
916892
; PRED-NEXT: [[TMP37:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1
@@ -921,11 +897,11 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
921897
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP40]], align 4
922898
; PRED-NEXT: [[TMP41:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 1
923899
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP41]], align 4
924-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE15]]
925-
; PRED: [[PRED_STORE_CONTINUE15]]:
900+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE8]]
901+
; PRED: [[PRED_STORE_CONTINUE8]]:
926902
; PRED-NEXT: [[TMP42:%.*]] = extractelement <8 x i1> [[TMP26]], i32 2
927-
; PRED-NEXT: br i1 [[TMP42]], label %[[PRED_STORE_IF16:.*]], label %[[PRED_STORE_CONTINUE17:.*]]
928-
; PRED: [[PRED_STORE_IF16]]:
903+
; PRED-NEXT: br i1 [[TMP42]], label %[[PRED_STORE_IF9:.*]], label %[[PRED_STORE_CONTINUE10:.*]]
904+
; PRED: [[PRED_STORE_IF9]]:
929905
; PRED-NEXT: [[TMP43:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2
930906
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP43]], align 4
931907
; PRED-NEXT: [[TMP44:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2
@@ -936,11 +912,11 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
936912
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP47]], align 4
937913
; PRED-NEXT: [[TMP48:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 2
938914
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP48]], align 4
939-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE17]]
940-
; PRED: [[PRED_STORE_CONTINUE17]]:
915+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE10]]
916+
; PRED: [[PRED_STORE_CONTINUE10]]:
941917
; PRED-NEXT: [[TMP49:%.*]] = extractelement <8 x i1> [[TMP26]], i32 3
942-
; PRED-NEXT: br i1 [[TMP49]], label %[[PRED_STORE_IF18:.*]], label %[[PRED_STORE_CONTINUE19:.*]]
943-
; PRED: [[PRED_STORE_IF18]]:
918+
; PRED-NEXT: br i1 [[TMP49]], label %[[PRED_STORE_IF11:.*]], label %[[PRED_STORE_CONTINUE12:.*]]
919+
; PRED: [[PRED_STORE_IF11]]:
944920
; PRED-NEXT: [[TMP50:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3
945921
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP50]], align 4
946922
; PRED-NEXT: [[TMP51:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3
@@ -951,11 +927,11 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
951927
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP54]], align 4
952928
; PRED-NEXT: [[TMP55:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 3
953929
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP55]], align 4
954-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE19]]
955-
; PRED: [[PRED_STORE_CONTINUE19]]:
930+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE12]]
931+
; PRED: [[PRED_STORE_CONTINUE12]]:
956932
; PRED-NEXT: [[TMP56:%.*]] = extractelement <8 x i1> [[TMP26]], i32 4
957-
; PRED-NEXT: br i1 [[TMP56]], label %[[PRED_STORE_IF20:.*]], label %[[PRED_STORE_CONTINUE21:.*]]
958-
; PRED: [[PRED_STORE_IF20]]:
933+
; PRED-NEXT: br i1 [[TMP56]], label %[[PRED_STORE_IF13:.*]], label %[[PRED_STORE_CONTINUE14:.*]]
934+
; PRED: [[PRED_STORE_IF13]]:
959935
; PRED-NEXT: [[TMP57:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4
960936
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP57]], align 4
961937
; PRED-NEXT: [[TMP58:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4
@@ -966,11 +942,11 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
966942
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP61]], align 4
967943
; PRED-NEXT: [[TMP62:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 4
968944
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP62]], align 4
969-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE21]]
970-
; PRED: [[PRED_STORE_CONTINUE21]]:
945+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE14]]
946+
; PRED: [[PRED_STORE_CONTINUE14]]:
971947
; PRED-NEXT: [[TMP63:%.*]] = extractelement <8 x i1> [[TMP26]], i32 5
972-
; PRED-NEXT: br i1 [[TMP63]], label %[[PRED_STORE_IF22:.*]], label %[[PRED_STORE_CONTINUE23:.*]]
973-
; PRED: [[PRED_STORE_IF22]]:
948+
; PRED-NEXT: br i1 [[TMP63]], label %[[PRED_STORE_IF15:.*]], label %[[PRED_STORE_CONTINUE16:.*]]
949+
; PRED: [[PRED_STORE_IF15]]:
974950
; PRED-NEXT: [[TMP64:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5
975951
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP64]], align 4
976952
; PRED-NEXT: [[TMP65:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5
@@ -981,11 +957,11 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
981957
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP68]], align 4
982958
; PRED-NEXT: [[TMP69:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 5
983959
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP69]], align 4
984-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE23]]
985-
; PRED: [[PRED_STORE_CONTINUE23]]:
960+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE16]]
961+
; PRED: [[PRED_STORE_CONTINUE16]]:
986962
; PRED-NEXT: [[TMP70:%.*]] = extractelement <8 x i1> [[TMP26]], i32 6
987-
; PRED-NEXT: br i1 [[TMP70]], label %[[PRED_STORE_IF24:.*]], label %[[PRED_STORE_CONTINUE25:.*]]
988-
; PRED: [[PRED_STORE_IF24]]:
963+
; PRED-NEXT: br i1 [[TMP70]], label %[[PRED_STORE_IF17:.*]], label %[[PRED_STORE_CONTINUE18:.*]]
964+
; PRED: [[PRED_STORE_IF17]]:
989965
; PRED-NEXT: [[TMP71:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6
990966
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP71]], align 4
991967
; PRED-NEXT: [[TMP72:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6
@@ -996,11 +972,11 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
996972
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP75]], align 4
997973
; PRED-NEXT: [[TMP76:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 6
998974
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP76]], align 4
999-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE25]]
1000-
; PRED: [[PRED_STORE_CONTINUE25]]:
975+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE18]]
976+
; PRED: [[PRED_STORE_CONTINUE18]]:
1001977
; PRED-NEXT: [[TMP77:%.*]] = extractelement <8 x i1> [[TMP26]], i32 7
1002-
; PRED-NEXT: br i1 [[TMP77]], label %[[PRED_STORE_IF26:.*]], label %[[PRED_STORE_CONTINUE27]]
1003-
; PRED: [[PRED_STORE_IF26]]:
978+
; PRED-NEXT: br i1 [[TMP77]], label %[[PRED_STORE_IF19:.*]], label %[[PRED_STORE_CONTINUE20]]
979+
; PRED: [[PRED_STORE_IF19]]:
1004980
; PRED-NEXT: [[TMP78:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 7
1005981
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP78]], align 4
1006982
; PRED-NEXT: [[TMP79:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 7
@@ -1011,17 +987,18 @@ define void @test_conditional_interleave_group (ptr noalias %src.1, ptr noalias
1011987
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP82]], align 4
1012988
; PRED-NEXT: [[TMP83:%.*]] = extractelement <8 x ptr> [[TMP27]], i32 7
1013989
; PRED-NEXT: store float 0.000000e+00, ptr [[TMP83]], align 4
1014-
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE27]]
1015-
; PRED: [[PRED_STORE_CONTINUE27]]:
990+
; PRED-NEXT: br label %[[PRED_STORE_CONTINUE20]]
991+
; PRED: [[PRED_STORE_CONTINUE20]]:
1016992
; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 8
1017993
; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <8 x i1> @llvm.get.active.lane.mask.v8i1.i64(i64 [[INDEX]], i64 [[TMP17]])
1018994
; PRED-NEXT: [[TMP84:%.*]] = extractelement <8 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0
1019995
; PRED-NEXT: [[TMP85:%.*]] = xor i1 [[TMP84]], true
1020996
; PRED-NEXT: [[VEC_IND_NEXT]] = add <8 x i64> [[VEC_IND]], splat (i64 8)
1021997
; PRED-NEXT: br i1 [[TMP85]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
1022998
; PRED: [[MIDDLE_BLOCK]]:
1023-
; PRED-NEXT: br [[EXIT:label %.*]]
1024-
; PRED: [[SCALAR_PH]]:
999+
; PRED-NEXT: br label %[[EXIT:.*]]
1000+
; PRED: [[EXIT]]:
1001+
; PRED-NEXT: ret void
10251002
;
10261003
entry:
10271004
br label %loop.header
@@ -1124,7 +1101,7 @@ define void @redundant_branch_and_tail_folding(ptr %dst, i1 %c) {
11241101
; PRED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
11251102
; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4)
11261103
; PRED-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], 24
1127-
; PRED-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
1104+
; PRED-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
11281105
; PRED: [[MIDDLE_BLOCK]]:
11291106
; PRED-NEXT: br label %[[EXIT:.*]]
11301107
; PRED: [[EXIT]]:
@@ -1313,7 +1290,7 @@ define void @pred_udiv_select_cost(ptr %A, ptr %B, ptr %C, i64 %n, i8 %y) #1 {
13131290
; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX]], i64 [[TMP11]])
13141291
; PRED-NEXT: [[TMP28:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0
13151292
; PRED-NEXT: [[TMP29:%.*]] = xor i1 [[TMP28]], true
1316-
; PRED-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
1293+
; PRED-NEXT: br i1 [[TMP29]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
13171294
; PRED: [[MIDDLE_BLOCK]]:
13181295
; PRED-NEXT: br [[EXIT:label %.*]]
13191296
; PRED: [[SCALAR_PH]]:

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