Addressed the reviews related to dewscription & documentation of the new operand.

Author: vg0204

llvm/docs/MIRLangRef.rst

@@ -807,23 +807,23 @@ For an int eq predicate ``ICMP_EQ``, the syntax is:
 
    %2:gpr(s32) = G_ICMP intpred(eq), %0, %1
 
-Lanemask Operands
+LaneMask Operands
 ^^^^^^^^^^^^^^^^^^
 
-A Lanemask operand is a 64-bit unsigned value that can store lane information 
-for a register operand in the instruction. It can be used as many times as needed
-in an instruction, with one or more register operands associated with it. While 
-the active bits represent the live subregister (in virtual registers) or regUnits
-(in physical registers), the remaining bits can represent the UNDEF part of it. 
+A LaneMask operand contains a LaneBitmask struct representing the covering of a
+register with sub-registers. [That's what it says in LaneBitmask.h!] Instructions
+typically associate a LaneMask operand with one or more Register operands, and
+use it to represent sub-register granularity information like liveness for those 
+associated Register operands.
 
 
-For example, the COPY_LANEMASK instruction uses this operand to copy only active 
+For example, the COPY_LANEMASK instruction uses this operand to copy only active
 lanes (of the source register) in the mask. The syntax for it would look like:
 
 .. code-block:: text
 
    $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(0x00000000000000C0)
-   
+
 .. TODO: Describe the parsers default behaviour when optional YAML attributes
    are missing.
 .. TODO: Describe the syntax for virtual register YAML definitions.

llvm/include/llvm/CodeGen/MachineInstr.h

@@ -1432,7 +1432,7 @@ class MachineInstr
     return getOpcode() == TargetOpcode::COPY;
   }
 
-  bool isCopyLanemask() const {
+  bool isCopyLaneMask() const {
     return getOpcode() == TargetOpcode::COPY_LANEMASK;
   }
 

llvm/include/llvm/Support/TargetOpcodes.def

@@ -114,8 +114,9 @@ HANDLE_TARGET_OPCODE(REG_SEQUENCE)
 /// used to copy between subregisters of virtual registers.
 HANDLE_TARGET_OPCODE(COPY)
 
-/// COPY_LANEMASK - Target-independent register copy for active mask in 
-/// register as represented by the lanemask. This instruction does not 
+/// COPY_LANEMASK - Target-independent partial register copy. The laneMask
+/// operand indicates which parts of the source register are copied to the
+/// destination. Other parts of the destination are undefined. It does not
 /// support copy between subregisters of virtual registers.
 HANDLE_TARGET_OPCODE(COPY_LANEMASK)
 

llvm/lib/CodeGen/MIRParser/MIParser.cpp

@@ -2881,22 +2881,22 @@ bool MIParser::parseLaneMaskOperand(MachineOperand &Dest) {
 
   lex();
   if (expectAndConsume(MIToken::lparen))
-    return error("lanemask should begin with '('.");
+    return true;
 
   LaneBitmask LaneMask = LaneBitmask::getAll();
   // Parse lanemask.
   if (Token.isNot(MIToken::IntegerLiteral) && Token.isNot(MIToken::HexLiteral))
-    return error("expected a valid lane mask value.");
+    return error("expected a valid lane mask value");
   static_assert(sizeof(LaneBitmask::Type) == sizeof(uint64_t),
                 "Use correct get-function for lane mask.");
   LaneBitmask::Type V;
   if (getUint64(V))
-    return error("invalid lanemask value");
+    return true;
   LaneMask = LaneBitmask(V);
   lex();
 
   if (expectAndConsume(MIToken::rparen))
-    return error("lanemask should be terminated by ')'.");
+    return true;
 
   Dest = MachineOperand::CreateLaneMask(LaneMask);
   return false;

llvm/lib/CodeGen/MachineVerifier.cpp

@@ -2434,7 +2434,7 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     const MachineOperand &LaneMaskOp = MI->getOperand(2);
     const Register SrcReg = SrcOp.getReg();
     const LaneBitmask LaneMask = LaneMaskOp.getLaneMask();
-    LaneBitmask SrcMaxLanemask = LaneBitmask::getAll();
+    LaneBitmask SrcMaxLaneMask = LaneBitmask::getAll();
 
     if (DstOp.getSubReg())
       report("COPY_LANEMASK must not use a subregister index", &DstOp, 0);
@@ -2448,15 +2448,22 @@ void MachineVerifier::visitMachineInstrBefore(const MachineInstr *MI) {
     if (SrcReg.isPhysical()) {
       const TargetRegisterClass *SrcRC = TRI->getMinimalPhysRegClass(SrcReg);
       if (SrcRC)
-        SrcMaxLanemask = SrcRC->getLaneMask();
+        SrcMaxLaneMask = SrcRC->getLaneMask();
     } else {
-      SrcMaxLanemask = MRI->getMaxLaneMaskForVReg(SrcReg);
+      SrcMaxLaneMask = MRI->getMaxLaneMaskForVReg(SrcReg);
     }
 
-    // If LaneMask is equal to OR greater than the SrcMaxLanemask, it
-    // impliess COPY_LANEMASK is trying to copy all lanes.
-    if (SrcMaxLanemask <= LaneMask)
-      report("COPY_LANEMASK cannot read all lanes", MI);
+    // COPY_LANEMASK should be used only for partial copy. For full
+    // copy, one should strictly use the COPY instruction.
+    if (SrcMaxLaneMask == LaneMask)
+      report("COPY_LANEMASK cannot be used to do full copy", MI);
+
+    // If LaneMask is equal to OR greater than the SrcMaxLaneMask, it
+    // implies COPY_LANEMASK is attempting to read from the lanes that
+    // don't exists in the source register.
+    if (SrcMaxLaneMask < LaneMask)
+      report("COPY_LANEMASK attempts to read from the lanes that "
+             "don't exist in the source register", MI);
 
     break;
   }

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-0.mir

@@ -7,7 +7,7 @@ body:             |
   bb.0:
     liveins: $vgpr0
 
-    ; CHECK: [[@LINE+1]]:47: lanemask should be terminated by ')'. 
+    ; CHECK: [[@LINE+1]]:47: expected ')'
     $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(16
     S_ENDPGM 0
 ...

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-1.mir

@@ -7,7 +7,7 @@ body:             |
   bb.0:
     liveins: $vgpr0
 
-    ; CHECK: [[@LINE+1]]:45: lanemask should begin with '('. 
+    ; CHECK: [[@LINE+1]]:45: expected '('
     $vgpr1 = COPY_LANEMASK $vgpr0, lanemask 14)
     S_ENDPGM 0
 ...

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-2.mir

@@ -7,7 +7,7 @@ body:             |
   bb.0:
     liveins: $vgpr0
 
-    ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value. 
+    ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value
     $vgpr1 = COPY_LANEMASK $vgpr0, lanemask(undef)
     S_ENDPGM 0
 ...

llvm/test/CodeGen/MIR/AMDGPU/parse-lanemask-operand-invalid-3.mir

@@ -7,7 +7,7 @@ body:             |
   bb.0:
     liveins: $vgpr0
 
-    ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value. 
+    ; CHECK: [[@LINE+1]]:45: expected a valid lane mask value
     $vgpr1 = COPY_LANEMASK $vgpr0, lanemask()
     S_ENDPGM 0
 ...

llvm/test/CodeGen/RISCV/GlobalISel/legalizer-info-validation.mir

@@ -77,7 +77,7 @@
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 #
 # DEBUG-NEXT: G_ABDU (opcode 67): 1 type index, 0 imm indices
-# DEBUG-NEXT: .. opcode 67 is aliased to 66 
+# DEBUG-NEXT: .. opcode 67 is aliased to 66
 # DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 #