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Add select non-boolean vector condition tests (#484)
This PR is the first part of the fix for [#164018](llvm/llvm-project#164018). Adds non-boolean vector condition tests to the `select` tests.
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-88
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5 files changed

+253
-88
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‎test/Feature/HLSLLib/select.32.test‎

Lines changed: 85 additions & 33 deletions
Original file line numberDiff line numberDiff line change
@@ -6,24 +6,28 @@
66
// - Vector condition, scalar true value, vector false value
77
// - Vector condition, vector true value, scalar false value
88
// - Vector condition, scalar true/false values
9+
// - Non-boolean vector condition, vector true/false values
910
// For each vector condition scenario, there are tests for vec4, vec3, and vec2.
1011
// For the scalar condition scenario, there are four tests. One uses the buffers
1112
// for inputs and the other three use constants.
1213

1314
StructuredBuffer<bool> Cond : register(t0);
14-
StructuredBuffer<float4> TrueVal0 : register(t1);
15-
StructuredBuffer<float4> FalseVal0 : register(t2);
16-
StructuredBuffer<int4> TrueVal1 : register(t3);
17-
StructuredBuffer<int4> FalseVal1 : register(t4);
18-
StructuredBuffer<uint4> TrueVal2 : register(t5);
19-
StructuredBuffer<uint4> FalseVal2 : register(t6);
20-
StructuredBuffer<bool> TrueVal3 : register(t7);
21-
StructuredBuffer<bool> FalseVal3 : register(t8);
15+
StructuredBuffer<float4> FloatCond : register(t1);
16+
StructuredBuffer<float4> TrueVal0 : register(t2);
17+
StructuredBuffer<float4> FalseVal0 : register(t3);
18+
StructuredBuffer<int4> IntCond : register(t4);
19+
StructuredBuffer<int4> TrueVal1 : register(t5);
20+
StructuredBuffer<int4> FalseVal1 : register(t6);
21+
StructuredBuffer<uint4> UIntCond : register(t7);
22+
StructuredBuffer<uint4> TrueVal2 : register(t8);
23+
StructuredBuffer<uint4> FalseVal2 : register(t9);
24+
StructuredBuffer<bool> TrueVal3 : register(t10);
25+
StructuredBuffer<bool> FalseVal3 : register(t11);
2226

23-
RWStructuredBuffer<float4> Out0 : register(u9);
24-
RWStructuredBuffer<int4> Out1 : register(u10);
25-
RWStructuredBuffer<uint4> Out2 : register(u11);
26-
RWStructuredBuffer<bool4> Out3 : register(u12);
27+
RWStructuredBuffer<float4> Out0 : register(u12);
28+
RWStructuredBuffer<int4> Out1 : register(u13);
29+
RWStructuredBuffer<uint4> Out2 : register(u14);
30+
RWStructuredBuffer<bool4> Out3 : register(u15);
2731

2832

2933
[numthreads(1,1,1)]
@@ -47,6 +51,9 @@ void main() {
4751
// vec2
4852
Out0[8] = float4(select(Cond2, TrueVal0[2].xy, FalseVal0[2].xy), select(Cond3, TrueVal0[2].z, FalseVal0[2].zw));
4953
Out0[9] = float4(select(Cond2, TrueVal0[2].xy, FalseVal0[2].x), select(Cond3, TrueVal0[2].z, FalseVal0[2].z));
54+
// non-bool vector condition
55+
Out0[10] = select(FloatCond[0], TrueVal0[0], FalseVal0[0]);
56+
Out0[11] = select(FloatCond[0] == FloatCond[1], TrueVal0[0], FalseVal0[0]);
5057

5158
// int
5259
// vec4
@@ -62,6 +69,9 @@ void main() {
6269
// vec2
6370
Out1[8] = int4(select(Cond2, TrueVal1[2].xy, FalseVal1[2].xy), select(Cond3, TrueVal1[2].z, FalseVal1[2].zw));
6471
Out1[9] = int4(select(Cond2, TrueVal1[2].xy, FalseVal1[2].x), select(Cond3, TrueVal1[2].z, FalseVal1[2].z));
72+
// non-bool vector condition
73+
Out1[10] = select(IntCond[0], TrueVal1[0], FalseVal1[0]);
74+
Out1[11] = select(IntCond[0] == IntCond[1], TrueVal1[0], FalseVal1[0]);
6575

6676
// uint
6777
// vec4
@@ -77,6 +87,9 @@ void main() {
7787
// vec2
7888
Out2[8] = uint4(select(Cond2, TrueVal2[2].xy, FalseVal2[2].xy), select(Cond3, TrueVal2[2].z, FalseVal2[2].zw));
7989
Out2[9] = uint4(select(Cond2, TrueVal2[2].xy, FalseVal2[2].x), select(Cond3, TrueVal2[2].z, FalseVal2[2].z));
90+
// non-bool vector condition
91+
Out2[10] = select(UIntCond[0], TrueVal2[0], FalseVal2[0]);
92+
Out2[11] = select(UIntCond[0] == UIntCond[1], TrueVal2[0], FalseVal2[0]);
8093

8194
// bool
8295
// vec4
@@ -109,6 +122,10 @@ Buffers:
109122
Format: Bool
110123
Stride: 4
111124
Data: [ 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 1 ]
125+
- Name: FloatCond
126+
Format: Float32
127+
Stride: 16
128+
Data: [ 10, 0, 20, 0, 1, -10, 20, 0 ]
112129
- Name: TrueVal0
113130
Format: Float32
114131
Stride: 16
@@ -117,6 +134,10 @@ Buffers:
117134
Format: Float32
118135
Stride: 16
119136
Data: [ -1, -2, -3, -4, 7.7, 8.8, -9.9, 0.01, 100, 200, -15, 25 ]
137+
- Name: IntCond
138+
Format: Int32
139+
Stride: 16
140+
Data: [ 10, 0, 20, 0, 1, -10, 20, 0 ]
120141
- Name: TrueVal1
121142
Format: Int32
122143
Stride: 16
@@ -125,6 +146,10 @@ Buffers:
125146
Format: Int32
126147
Stride: 16
127148
Data: [ -1, -2, -3, -4, 7, 8, -9, 1, 100, 200, -15, 25 ]
149+
- Name: UIntCond
150+
Format: UInt32
151+
Stride: 16
152+
Data: [ 10, 0, 20, 0, 1, 10, 20, 0 ]
128153
- Name: TrueVal2
129154
Format: UInt32
130155
Stride: 16
@@ -144,38 +169,41 @@ Buffers:
144169
- Name: Out0
145170
Format: Float32
146171
Stride: 16
147-
FillSize: 160
172+
FillSize: 192
148173
- Name: ExpectedOut0
149174
Format: Float32
150175
Stride: 16
151176
Data: [
152177
1, -2, 3, -4, 1, -2, 1, -4, 1, -1, 3, -1, 1, -1, 1, -1,
153178
4.4, -5.5, -9.9, 0.01, 4.4, 4.4, -9.9, 1, 4.4, -5.5, 7.7, -2, 4.4, 4.4, 7.7, 3,
154-
-10, 200, -15, 15, -10, 100, -15, 15
179+
-10, 200, -15, 15, -10, 100, -15, 15,
180+
1, -2, 3, -4, -1, -2, 3, 4
155181
]
156182
- Name: Out1
157183
Format: Int32
158184
Stride: 16
159-
FillSize: 160
185+
FillSize: 192
160186
- Name: ExpectedOut1
161187
Format: Int32
162188
Stride: 16
163189
Data: [
164190
1, -2, 3, -4, 1, -2, 1, -4, 1, -1, 3, -1, 1, -1, 1, -1,
165191
4, -5, -9, 1, 4, 4, -9, 1, 4, -5, 7, -2, 4, 4, 7, 3,
166-
-10, 200, -15, 15, -10, 100, -15, 15
192+
-10, 200, -15, 15, -10, 100, -15, 15,
193+
1, -2, 3, -4, -1, -2, 3, 4
167194
]
168195
- Name: Out2
169196
Format: UInt32
170197
Stride: 16
171-
FillSize: 160
198+
FillSize: 192
172199
- Name: ExpectedOut2
173200
Format: UInt32
174201
Stride: 16
175202
Data: [
176203
1, 20, 3, 40, 1, 20, 1, 40, 1, 10, 3, 10, 1, 10, 1, 10,
177204
4, 5, 9, 1, 4, 4, 9, 1, 4, 5, 7, 20, 4, 4, 7, 3,
178-
10, 200, 150, 15, 10, 100, 150, 15
205+
10, 200, 150, 15, 10, 100, 150, 15,
206+
1, 20, 3, 40, 10, 20, 3, 4
179207
]
180208
- Name: Out3
181209
Format: Bool
@@ -215,92 +243,116 @@ DescriptorSets:
215243
Space: 0
216244
VulkanBinding:
217245
Binding: 0
218-
- Name: TrueVal0
246+
- Name: FloatCond
219247
Kind: StructuredBuffer
220248
DirectXBinding:
221249
Register: 1
222250
Space: 0
223251
VulkanBinding:
224252
Binding: 1
225-
- Name: FalseVal0
253+
- Name: TrueVal0
226254
Kind: StructuredBuffer
227255
DirectXBinding:
228256
Register: 2
229257
Space: 0
230258
VulkanBinding:
231259
Binding: 2
232-
- Name: TrueVal1
260+
- Name: FalseVal0
233261
Kind: StructuredBuffer
234262
DirectXBinding:
235263
Register: 3
236264
Space: 0
237265
VulkanBinding:
238266
Binding: 3
239-
- Name: FalseVal1
267+
- Name: IntCond
240268
Kind: StructuredBuffer
241269
DirectXBinding:
242270
Register: 4
243271
Space: 0
244272
VulkanBinding:
245273
Binding: 4
246-
- Name: TrueVal2
274+
- Name: TrueVal1
247275
Kind: StructuredBuffer
248276
DirectXBinding:
249277
Register: 5
250278
Space: 0
251279
VulkanBinding:
252280
Binding: 5
253-
- Name: FalseVal2
281+
- Name: FalseVal1
254282
Kind: StructuredBuffer
255283
DirectXBinding:
256284
Register: 6
257285
Space: 0
258286
VulkanBinding:
259287
Binding: 6
260-
- Name: TrueVal3
288+
- Name: UIntCond
261289
Kind: StructuredBuffer
262290
DirectXBinding:
263291
Register: 7
264292
Space: 0
265293
VulkanBinding:
266294
Binding: 7
267-
- Name: FalseVal3
295+
- Name: TrueVal2
268296
Kind: StructuredBuffer
269297
DirectXBinding:
270298
Register: 8
271299
Space: 0
272300
VulkanBinding:
273301
Binding: 8
274-
- Name: Out0
275-
Kind: RWStructuredBuffer
302+
- Name: FalseVal2
303+
Kind: StructuredBuffer
276304
DirectXBinding:
277305
Register: 9
278306
Space: 0
279307
VulkanBinding:
280308
Binding: 9
281-
- Name: Out1
282-
Kind: RWStructuredBuffer
309+
- Name: TrueVal3
310+
Kind: StructuredBuffer
283311
DirectXBinding:
284312
Register: 10
285313
Space: 0
286314
VulkanBinding:
287315
Binding: 10
288-
- Name: Out2
289-
Kind: RWStructuredBuffer
316+
- Name: FalseVal3
317+
Kind: StructuredBuffer
290318
DirectXBinding:
291319
Register: 11
292320
Space: 0
293321
VulkanBinding:
294322
Binding: 11
295-
- Name: Out3
323+
- Name: Out0
296324
Kind: RWStructuredBuffer
297325
DirectXBinding:
298326
Register: 12
299327
Space: 0
300328
VulkanBinding:
301329
Binding: 12
330+
- Name: Out1
331+
Kind: RWStructuredBuffer
332+
DirectXBinding:
333+
Register: 13
334+
Space: 0
335+
VulkanBinding:
336+
Binding: 13
337+
- Name: Out2
338+
Kind: RWStructuredBuffer
339+
DirectXBinding:
340+
Register: 14
341+
Space: 0
342+
VulkanBinding:
343+
Binding: 14
344+
- Name: Out3
345+
Kind: RWStructuredBuffer
346+
DirectXBinding:
347+
Register: 15
348+
Space: 0
349+
VulkanBinding:
350+
Binding: 15
302351
#--- end
303352

353+
# Bug https://github.com/llvm/llvm-project/issues/164018
354+
# XFAIL: Clang
355+
304356
# RUN: split-file %s %t
305357
# RUN: %dxc_target -HV 202x -T cs_6_5 -Fo %t.o %t/source.hlsl
306358
# RUN: %offloader %t/pipeline.yaml %t.o

‎test/Feature/HLSLLib/select.fp16.test‎

Lines changed: 31 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -6,15 +6,17 @@
66
// - Vector condition, scalar true value, vector false value
77
// - Vector condition, vector true value, scalar false value
88
// - Vector condition, scalar true/false values
9+
// - Non-boolean vector condition, vector true/false values
910
// For each vector condition scenario, there are tests for vec4, vec3, and vec2.
1011
// For the scalar condition scenario, there are four tests. One uses the buffers
1112
// for inputs and the other three use constants.
1213

1314
StructuredBuffer<bool> Cond : register(t0);
14-
StructuredBuffer<half4> TrueVal : register(t1);
15-
StructuredBuffer<half4> FalseVal : register(t2);
15+
StructuredBuffer<half4> HalfCond : register(t1);
16+
StructuredBuffer<half4> TrueVal : register(t2);
17+
StructuredBuffer<half4> FalseVal : register(t3);
1618

17-
RWStructuredBuffer<half4> Out : register(u3);
19+
RWStructuredBuffer<half4> Out : register(u4);
1820

1921

2022
[numthreads(1,1,1)]
@@ -37,6 +39,9 @@ void main() {
3739
// vec2
3840
Out[8] = half4(select(Cond2, TrueVal[2].xy, FalseVal[2].xy), select(Cond3, TrueVal[2].z, FalseVal[2].zw));
3941
Out[9] = half4(select(Cond2, TrueVal[2].xy, FalseVal[2].x), select(Cond3, TrueVal[2].z, FalseVal[2].z));
42+
// non-bool vector condition
43+
Out[10] = select(HalfCond[0], TrueVal[0], FalseVal[0]);
44+
Out[11] = select(HalfCond[0] == HalfCond[1], TrueVal[0], FalseVal[0]);
4045
}
4146
//--- pipeline.yaml
4247

@@ -50,6 +55,11 @@ Buffers:
5055
Format: Bool
5156
Stride: 4
5257
Data: [ 1, 0, 1, 0, 1, 1, 0, 0, 1, 0, 0, 1 ]
58+
- Name: HalfCond
59+
Format: Float16
60+
Stride: 8
61+
Data: [ 0x4900, 0x0000, 0x4d00, 0x0000, 0x3c00, 0xc900, 0x4d00, 0x0000 ]
62+
# 10, 0, 20, 0, 1, -10, 20, 0
5363
- Name: TrueVal
5464
Format: Float16
5565
Stride: 8
@@ -63,18 +73,20 @@ Buffers:
6373
- Name: Out
6474
Format: Float16
6575
Stride: 8
66-
FillSize: 80
76+
FillSize: 96
6777
- Name: ExpectedOut
6878
Format: Float16
6979
Stride: 8
7080
Data: [
7181
0x3c00, 0xc000, 0x4200, 0xc400, 0x3c00, 0xc000, 0x3c00, 0xc400, 0x3c00, 0xbc00, 0x4200, 0xbc00, 0x3c00, 0xbc00, 0x3c00, 0xbc00,
7282
0x4466, 0xc580, 0xc8f3, 0x211f, 0x4466, 0x4466, 0xc8f3, 0x3c00, 0x4466, 0xc580, 0x47b3, 0xc000, 0x4466, 0x4466, 0x47b3, 0x4200,
73-
0xc900, 0x5a40, 0xcb80, 0x4b80, 0xc900, 0x5640, 0xcb80, 0x4b80
83+
0xc900, 0x5a40, 0xcb80, 0x4b80, 0xc900, 0x5640, 0xcb80, 0x4b80,
84+
0x3c00, 0xc000, 0x4200, 0xc400, 0xbc00, 0xc000, 0x4200, 0x4400
7485
]
7586
# 1, -2, 3, -4, 1, -2, 1, -4, 1, -1, 3, -1, 1, -1, 1, -1,
7687
# 4.4, -5.5, -9.9, 0.01, 4.4, 4.4, -9.9, 1, 4.4, -5.5, 7.7, -2, 4.4, 4.4, 7.7, 3,
7788
# -10, 200, -15, 15, -10, 100, -15, 15
89+
# 1, -2, 3, -4, -1, -2, 3, 4
7890
Results:
7991
- Result: Test0
8092
Rule: BufferExact
@@ -89,29 +101,39 @@ DescriptorSets:
89101
Space: 0
90102
VulkanBinding:
91103
Binding: 0
92-
- Name: TrueVal
104+
- Name: HalfCond
93105
Kind: StructuredBuffer
94106
DirectXBinding:
95107
Register: 1
96108
Space: 0
97109
VulkanBinding:
98110
Binding: 1
99-
- Name: FalseVal
111+
- Name: TrueVal
100112
Kind: StructuredBuffer
101113
DirectXBinding:
102114
Register: 2
103115
Space: 0
104116
VulkanBinding:
105117
Binding: 2
106-
- Name: Out
107-
Kind: RWStructuredBuffer
118+
- Name: FalseVal
119+
Kind: StructuredBuffer
108120
DirectXBinding:
109121
Register: 3
110122
Space: 0
111123
VulkanBinding:
112124
Binding: 3
125+
- Name: Out
126+
Kind: RWStructuredBuffer
127+
DirectXBinding:
128+
Register: 4
129+
Space: 0
130+
VulkanBinding:
131+
Binding: 4
113132
#--- end
114133

134+
# Bug https://github.com/llvm/llvm-project/issues/164018
135+
# XFAIL: Clang
136+
115137
# REQUIRES: Half
116138
# RUN: split-file %s %t
117139
# RUN: %dxc_target -enable-16bit-types -HV 202x -T cs_6_5 -Fo %t.o %t/source.hlsl

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