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Aug 26, 2025
Merged

Add any tests #368

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9721697
add any tests
kmpeng Aug 20, 2025
550928f
add newlines
kmpeng Aug 21, 2025
5a31818
xfail intel bug and link issue
kmpeng Aug 21, 2025
ad18b83
fix xfails
kmpeng Aug 21, 2025
4624f9f
split xfail lines
kmpeng Aug 22, 2025
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142 changes: 142 additions & 0 deletions test/Feature/HLSLLib/any.32.test
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#--- source.hlsl
StructuredBuffer<float4> In0 : register(t0);
StructuredBuffer<int4> In1 : register(t1);
StructuredBuffer<uint4> In2 : register(t2);

RWStructuredBuffer<bool> Out0 : register(u3);
RWStructuredBuffer<bool> Out1 : register(u4);
RWStructuredBuffer<bool> Out2 : register(u5);


[numthreads(1,1,1)]
void main() {
// float
Out0[0] = any(In0[0]);
Out0[1] = any(In0[1].xyz);
Out0[2] = any(In0[1].w);
Out0[3] = any(In0[2].xy);
Out0[4] = any(In0[2].zw);
Out0[5] = any(float4(0, 0, 0, 4.5));

// int
Out1[0] = any(In1[0]);
Out1[1] = any(In1[1].xyz);
Out1[2] = any(In1[1].w);
Out1[3] = any(In1[2].xy);
Out1[4] = any(In1[2].zw);
Out1[5] = any(int4(0, 0, 0, 4));

// uint
Out2[0] = any(In2[0]);
Out2[1] = any(In2[1].xyz);
Out2[2] = any(In2[1].w);
Out2[3] = any(In2[2].xy);
Out2[4] = any(In2[2].zw);
Out2[5] = any(uint4(0, 0, 0, 4));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In0
Format: Float32
Stride: 16
Data: [ 0, 0, 0, 4.5, 0, 0, 0, -5.5, 0, 1.0, -0.01, 0.01]
- Name: In1
Format: Int32
Stride: 16
Data: [ 0, 0, 0, 4, 0, 0, 0, -5, 0, 2, -1, 1 ]
- Name: In2
Format: UInt32
Stride: 16
Data: [ 0, 0, 0, 4, 0, 0, 0, 5, 0, 2, 100, 1 ]
- Name: Out0
Format: Bool
Stride: 4
ZeroInitSize: 24
- Name: ExpectedOut0
Format: Bool
Stride: 4
Data: [ 1, 0, 1, 1, 1, 1 ]
- Name: Out1
Format: Bool
Stride: 4
ZeroInitSize: 24
- Name: ExpectedOut1
Format: Bool
Stride: 4
Data: [ 1, 0, 1, 1, 1, 1 ]
- Name: Out2
Format: Bool
Stride: 4
ZeroInitSize: 24
- Name: ExpectedOut2
Format: Bool
Stride: 4
Data: [ 1, 0, 1, 1, 1, 1 ]
Results:
- Result: Test0
Rule: BufferExact
Actual: Out0
Expected: ExpectedOut0
- Result: Test1
Rule: BufferExact
Actual: Out1
Expected: ExpectedOut1
- Result: Test2
Rule: BufferExact
Actual: Out2
Expected: ExpectedOut2
DescriptorSets:
- Resources:
- Name: In0
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: In1
Kind: StructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
- Name: In2
Kind: StructuredBuffer
DirectXBinding:
Register: 2
Space: 0
VulkanBinding:
Binding: 2
- Name: Out0
Kind: RWStructuredBuffer
DirectXBinding:
Register: 3
Space: 0
VulkanBinding:
Binding: 3
- Name: Out1
Kind: RWStructuredBuffer
DirectXBinding:
Register: 4
Space: 0
VulkanBinding:
Binding: 4
- Name: Out2
Kind: RWStructuredBuffer
DirectXBinding:
Register: 5
Space: 0
VulkanBinding:
Binding: 5
#--- end

# RUN: split-file %s %t
# RUN: %dxc_target -HV 202x -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
64 changes: 64 additions & 0 deletions test/Feature/HLSLLib/any.bool.test
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#--- source.hlsl
StructuredBuffer<bool4> In : register(t0);

RWStructuredBuffer<bool> Out : register(u1);


[numthreads(1,1,1)]
void main() {
Out[0] = any(In[0]);
Out[1] = any(In[1].xyz);
Out[2] = any(In[1].w);
Out[3] = any(In[2].xy);
Out[4] = any(In[2].zw);
Out[5] = any(bool4(0, 0, 0, 1));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In
Format: Bool
Stride: 16
Data: [ 0, 0, 0, 1, 0, 0, 0, 1, 0, 1, 1, 1 ]
- Name: Out
Format: Bool
Stride: 4
ZeroInitSize: 24
- Name: ExpectedOut
Format: Bool
Stride: 4
Data: [ 1, 0, 1, 1, 1, 1 ]
Results:
- Result: Test0
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: In
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# Bug https://github.com/llvm/llvm-project/issues/140824
# XFAIL: Clang

# RUN: split-file %s %t
# RUN: %dxc_target -HV 202x -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
63 changes: 63 additions & 0 deletions test/Feature/HLSLLib/any.fp16.test
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#--- source.hlsl
StructuredBuffer<half4> In : register(t0);

RWStructuredBuffer<bool> Out : register(u1);


[numthreads(1,1,1)]
void main() {
Out[0] = any(In[0]);
Out[1] = any(In[1].xyz);
Out[2] = any(In[1].w);
Out[3] = any(In[2].xy);
Out[4] = any(In[2].zw);
Out[5] = any(half4(0, 0, 0, 4.5));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In
Format: Float16
Stride: 8
Data: [ 0x0000, 0x0000, 0x0000, 0x4480, 0x0000, 0x0000, 0x0000, 0xc580, 0x0000, 0x3c00, 0xa11f, 0x211f ]
# 0, 0, 0, 4.5, 0, 0, 0, -5.5, 0, 1.0, -0.01, 0.01
- Name: Out
Format: Bool
Stride: 4
ZeroInitSize: 24
- Name: ExpectedOut
Format: Bool
Stride: 4
Data: [ 1, 0, 1, 1, 1, 1 ]
Results:
- Result: Test0
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: In
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# REQUIRES: Half
# RUN: split-file %s %t
# RUN: %dxc_target -enable-16bit-types -HV 202x -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
65 changes: 65 additions & 0 deletions test/Feature/HLSLLib/any.fp64.test
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#--- source.hlsl
StructuredBuffer<double4> In : register(t0);

RWStructuredBuffer<bool> Out : register(u1);


[numthreads(1,1,1)]
void main() {
Out[0] = any(In[0]);
Out[1] = any(In[1].xyz);
Out[2] = any(In[1].w);
Out[3] = any(In[2].xy);
Out[4] = any(In[2].zw);
Out[5] = any(double4(0, 0, 0, 4.5));
}
//--- pipeline.yaml

---
Shaders:
- Stage: Compute
Entry: main
DispatchSize: [1, 1, 1]
Buffers:
- Name: In
Format: Float64
Stride: 32
Data: [ 0, 0, 0, 4.5, 0, 0, 0, -5.5, 0, 1.0, -0.01, 0.01 ]
- Name: Out
Format: Bool
Stride: 4
ZeroInitSize: 24
- Name: ExpectedOut
Format: Bool
Stride: 4
Data: [ 1, 0, 1, 1, 1, 1 ]
Results:
- Result: Test0
Rule: BufferExact
Actual: Out
Expected: ExpectedOut
DescriptorSets:
- Resources:
- Name: In
Kind: StructuredBuffer
DirectXBinding:
Register: 0
Space: 0
VulkanBinding:
Binding: 0
- Name: Out
Kind: RWStructuredBuffer
DirectXBinding:
Register: 1
Space: 0
VulkanBinding:
Binding: 1
#--- end

# Bug https://github.com/llvm/offload-test-suite/issues/370
# XFAIL: DXC && DirectX-Intel

# REQUIRES: Double
# RUN: split-file %s %t
# RUN: %dxc_target -HV 202x -T cs_6_5 -Fo %t.o %t/source.hlsl
# RUN: %offloader %t/pipeline.yaml %t.o
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