diff --git a/DSA-drawings.odg b/DSA-drawings.odg
index 4ef6d22..48e1c27 100644
Binary files a/DSA-drawings.odg and b/DSA-drawings.odg differ
diff --git a/cross-chip.svg b/cross-chip.svg
new file mode 100644
index 0000000..aa2d644
--- /dev/null
+++ b/cross-chip.svg
@@ -0,0 +1,1150 @@
+
+
\ No newline at end of file
diff --git a/dsa-netdev-2.1.lyx b/dsa-netdev-2.1.lyx
index d2063cf..6b99338 100644
--- a/dsa-netdev-2.1.lyx
+++ b/dsa-netdev-2.1.lyx
@@ -11,6 +11,13 @@
\setbeamercovered{transparent}
% or whatever (possibly just delete it)
+
+\AtBeginSection[]
+{
+ \begin{frame}
+ \tableofcontents[currentsection]
+ \end{frame}
+}
\end_preamble
\use_default_options false
\maintain_unincluded_children false
@@ -286,7 +293,7 @@ DSA in one Slide
\begin_layout Frame
\begin_inset Graphics
filename DSA-basic.svg
- scale 35
+ scale 28
\end_inset
@@ -324,7 +331,7 @@ The D in DSA
\begin_layout Frame
\begin_inset Graphics
filename DSA-D-in-DSA.svg
- scale 35
+ scale 29
\end_inset
@@ -344,7 +351,7 @@ Users of DSA
status open
\begin_layout Plain Layout
-WiFi Access Point, Set Top Boxes
+Wi-Fi Access Point, Set-top Boxes
\end_layout
\end_inset
@@ -405,7 +412,7 @@ Industrial Switches/Routers, mostly Transport Industry
\align center
\begin_inset Graphics
filename transport-devices.jpg
- scale 20
+ scale 18
\end_inset
@@ -480,7 +487,7 @@ Added to the kernel in 2008
\begin_inset Graphics
filename dsa-activity.svg
lyxscale 10
- scale 50
+ scale 56
\end_inset
@@ -525,7 +532,7 @@ First commit, support for some Marvell SOHO switches
\end_layout
\begin_layout Itemize
-Broadcom SF2, EEPROM, Temperature sensor, EEE, WoL, better libphy integration,
+Broadcom SF2, EEPROM, Temperature sensor, EEE, WoL, better PHYLIB integration,
88E6352
\end_layout
@@ -750,19 +757,34 @@ RX: master interface netif_receive_skb() -> tag parser, slave interface
selection -> netif_receive_skb
\end_layout
+\end_deeper
\begin_layout Standard
-\begin_inset Graphics
- filename wireshark.png
- lyxscale 50
- scale 20
+\begin_inset Separator plain
+\end_inset
+
+
+\end_layout
+
+\begin_layout Frame
+\begin_inset Argument 4
+status open
+
+\begin_layout Plain Layout
+The Data Plane
+\end_layout
\end_inset
\end_layout
-\end_deeper
\begin_layout Frame
+\begin_inset Graphics
+ filename wireshark.png
+ scale 25
+
+\end_inset
+
\end_layout
@@ -789,7 +811,7 @@ Ethernet frame processing
\begin_layout Frame
\begin_inset Graphics
filename DSA-frame-processing.svg
- scale 35
+ scale 28
\end_inset
@@ -819,7 +841,7 @@ Network stack flow
\begin_layout Frame
\begin_inset Graphics
filename dsa_explained.svg
- scale 35
+ scale 27
\end_inset
@@ -936,6 +958,145 @@ Well defined device (Device Tree) and driver model (dsa_switch_ops)
Implements switchdev_ops for supported offloads: bridge, VLAN, FDB, MDB
\end_layout
+\end_deeper
+\begin_layout Subsection
+The D in DSA
+\end_layout
+
+\begin_layout Frame
+\begin_inset Argument 4
+status open
+
+\begin_layout Plain Layout
+Cross-chip configuration
+\end_layout
+
+\end_inset
+
+
+\end_layout
+
+\begin_layout Frame
+\begin_inset Graphics
+ filename cross-chip.svg
+ scale 35
+
+\end_inset
+
+
+\end_layout
+
+\begin_layout Standard
+\begin_inset Separator plain
+\end_inset
+
+
+\end_layout
+
+\begin_layout Frame
+\begin_inset Argument 4
+status open
+
+\begin_layout Plain Layout
+Cross-chip configuration
+\end_layout
+
+\end_inset
+
+
+\end_layout
+
+\begin_deeper
+\begin_layout Standard
+Current behavior:
+\end_layout
+
+\begin_layout Itemize
+Interconnected switch chips create a switch fabric
+\end_layout
+
+\begin_layout Itemize
+DSA drivers manage single chip (struct dsa_switch)
+\end_layout
+
+\begin_layout Itemize
+DSA links configured to pass frames to any port
+\end_layout
+
+\begin_layout Standard
+Problem?
+\end_layout
+
+\begin_layout Itemize
+br0 bridging? Switches can potentially leak cross-chip frames!
+\end_layout
+
+\begin_layout Itemize
+br0 VLAN 42? Switch 1 won't pass traffic!
+\end_layout
+
+\end_deeper
+\begin_layout Standard
+\begin_inset Separator plain
+\end_inset
+
+
+\end_layout
+
+\begin_layout Frame
+\begin_inset Argument 4
+status open
+
+\begin_layout Plain Layout
+Cross-chip configuration
+\end_layout
+
+\end_inset
+
+
+\end_layout
+
+\begin_deeper
+\begin_layout Standard
+Solutions?
+\end_layout
+
+\begin_layout Itemize
+Cross-chip bridging (DONE):
+\end_layout
+
+\begin_deeper
+\begin_layout Itemize
+DSA core notifies drivers about fabric bridge events (crosschip_bridge_{join,lea
+ve} ops)
+\end_layout
+
+\begin_layout Itemize
+mv88e6xxx configure
+\begin_inset Flex Emphasize
+status open
+
+\begin_layout Plain Layout
+Cross-chip Port Based VLAN Table
+\end_layout
+
+\end_inset
+
+ (PVT, Marvell specific)
+\end_layout
+
+\end_deeper
+\begin_layout Itemize
+Cross-chip VLAN (WIP):
+\end_layout
+
+\begin_deeper
+\begin_layout Itemize
+DSA core notifies drivers about switchdev port objects (VLAN, FDB, MDB)
+ so that drivers allow traffic to pass
+\end_layout
+
+\end_deeper
\end_deeper
\begin_layout Section
The Future
@@ -960,7 +1121,7 @@ Multiple CPU ports
\end_layout
\begin_layout Itemize
-Often seen in WiFi devices to double SoC <–> Switch Bandwidth
+Often seen in Wi-Fi devices to double SoC <-> Switch Bandwidth
\end_layout
\begin_layout Itemize