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UPSTREAM: media: i2c: imx214: Make use of CCS PLL calculator
Calculate PLL parameters based on clock frequency and link frequency. Acked-by: Ricardo Ribalda <ribalda@chromium.org> Signed-off-by: André Apitzsch <git@apitzsch.eu>
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+175
-39
lines changed

2 files changed

+175
-39
lines changed

drivers/media/i2c/Kconfig

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -141,6 +141,7 @@ config VIDEO_IMX214
141141
depends on GPIOLIB
142142
select REGMAP_I2C
143143
select V4L2_CCI_I2C
144+
select VIDEO_CCS_PLL
144145
help
145146
This is a Video4Linux2 sensor driver for the Sony
146147
IMX214 camera.

drivers/media/i2c/imx214.c

Lines changed: 174 additions & 39 deletions
Original file line numberDiff line numberDiff line change
@@ -20,6 +20,8 @@
2020
#include <media/v4l2-fwnode.h>
2121
#include <media/v4l2-subdev.h>
2222

23+
#include "ccs-pll.h"
24+
2325
/* Chip ID */
2426
#define IMX214_REG_CHIP_ID CCI_REG16(0x0016)
2527
#define IMX214_CHIP_ID 0x0214
@@ -34,7 +36,6 @@
3436
#define IMX214_DEFAULT_LINK_FREQ 600000000
3537
/* Keep wrong link frequency for backward compatibility */
3638
#define IMX214_DEFAULT_LINK_FREQ_LEGACY 480000000
37-
#define IMX214_DEFAULT_PIXEL_RATE ((IMX214_DEFAULT_LINK_FREQ * 8LL) / 10)
3839
#define IMX214_FPS 30
3940

4041
/* V-TIMING internal */
@@ -84,6 +85,7 @@
8485
#define IMX214_CSI_DATA_FORMAT_RAW10 0x0A0A
8586
#define IMX214_CSI_DATA_FORMAT_COMP6 0x0A06
8687
#define IMX214_CSI_DATA_FORMAT_COMP8 0x0A08
88+
#define IMX214_BITS_PER_PIXEL_MASK 0xFF
8789

8890
#define IMX214_REG_CSI_LANE_MODE CCI_REG8(0x0114)
8991
#define IMX214_CSI_2_LANE_MODE 1
@@ -249,6 +251,10 @@ struct imx214 {
249251
struct clk *xclk;
250252
struct regmap *regmap;
251253

254+
struct ccs_pll pll;
255+
256+
struct v4l2_fwnode_endpoint bus_cfg;
257+
252258
struct v4l2_subdev sd;
253259
struct media_pad pad;
254260

@@ -758,16 +764,22 @@ static int imx214_configure_pll(struct imx214 *imx214)
758764
{
759765
int ret = 0;
760766

761-
cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV, 5, &ret);
762-
cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV, 2, &ret);
763-
cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV, 3, &ret);
764-
cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY, 150, &ret);
765-
cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV, 10, &ret);
766-
cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV, 1, &ret);
767+
cci_write(imx214->regmap, IMX214_REG_VTPXCK_DIV,
768+
imx214->pll.vt_bk.pix_clk_div, &ret);
769+
cci_write(imx214->regmap, IMX214_REG_VTSYCK_DIV,
770+
imx214->pll.vt_bk.sys_clk_div, &ret);
771+
cci_write(imx214->regmap, IMX214_REG_PREPLLCK_VT_DIV,
772+
imx214->pll.vt_fr.pre_pll_clk_div, &ret);
773+
cci_write(imx214->regmap, IMX214_REG_PLL_VT_MPY,
774+
imx214->pll.vt_fr.pll_multiplier, &ret);
775+
cci_write(imx214->regmap, IMX214_REG_OPPXCK_DIV,
776+
imx214->pll.op_bk.pix_clk_div, &ret);
777+
cci_write(imx214->regmap, IMX214_REG_OPSYCK_DIV,
778+
imx214->pll.op_bk.sys_clk_div, &ret);
767779
cci_write(imx214->regmap, IMX214_REG_PLL_MULT_DRIV,
768780
IMX214_PLL_SINGLE, &ret);
769781
cci_write(imx214->regmap, IMX214_REG_EXCK_FREQ,
770-
IMX214_EXCK_FREQ(IMX214_DEFAULT_CLK_FREQ / 1000000), &ret);
782+
IMX214_EXCK_FREQ(imx214->pll.ext_clk_freq_hz / 1000000), &ret);
771783

772784
return ret;
773785
}
@@ -872,9 +884,6 @@ static const struct v4l2_ctrl_ops imx214_ctrl_ops = {
872884

873885
static int imx214_ctrls_init(struct imx214 *imx214)
874886
{
875-
static const s64 link_freq[] = {
876-
IMX214_DEFAULT_LINK_FREQ
877-
};
878887
static const struct v4l2_area unit_size = {
879888
.width = 1120,
880889
.height = 1120,
@@ -895,15 +904,14 @@ static int imx214_ctrls_init(struct imx214 *imx214)
895904
if (ret)
896905
return ret;
897906

898-
imx214->pixel_rate = v4l2_ctrl_new_std(ctrl_hdlr, NULL,
899-
V4L2_CID_PIXEL_RATE, 0,
900-
IMX214_DEFAULT_PIXEL_RATE, 1,
901-
IMX214_DEFAULT_PIXEL_RATE);
907+
imx214->pixel_rate =
908+
v4l2_ctrl_new_std(ctrl_hdlr, NULL, V4L2_CID_PIXEL_RATE, 1,
909+
INT_MAX, 1, 1);
902910

903911
imx214->link_freq = v4l2_ctrl_new_int_menu(ctrl_hdlr, NULL,
904912
V4L2_CID_LINK_FREQ,
905-
ARRAY_SIZE(link_freq) - 1,
906-
0, link_freq);
913+
imx214->bus_cfg.nr_of_link_frequencies - 1,
914+
0, imx214->bus_cfg.link_frequencies);
907915
if (imx214->link_freq)
908916
imx214->link_freq->flags |= V4L2_CTRL_FLAG_READ_ONLY;
909917

@@ -1006,6 +1014,7 @@ static int imx214_start_streaming(struct imx214 *imx214)
10061014
const struct v4l2_mbus_framefmt *fmt;
10071015
struct v4l2_subdev_state *state;
10081016
const struct imx214_mode *mode;
1017+
int bit_rate_mbps;
10091018
int ret;
10101019

10111020
ret = cci_multi_reg_write(imx214->regmap, mode_table_common,
@@ -1021,8 +1030,10 @@ static int imx214_start_streaming(struct imx214 *imx214)
10211030
return ret;
10221031
}
10231032

1033+
bit_rate_mbps = (imx214->pll.pixel_rate_csi / 1000000)
1034+
* imx214->pll.bits_per_pixel;
10241035
ret = cci_write(imx214->regmap, IMX214_REG_REQ_LINK_BIT_RATE,
1025-
IMX214_LINK_BIT_RATE_MBPS(4800), NULL);
1036+
IMX214_LINK_BIT_RATE_MBPS(bit_rate_mbps), NULL);
10261037
if (ret) {
10271038
dev_err(imx214->dev, "failed to configure link bit rate\n");
10281039
return ret;
@@ -1105,6 +1116,109 @@ static int imx214_s_stream(struct v4l2_subdev *subdev, int enable)
11051116
return ret;
11061117
}
11071118

1119+
static int imx214_pll_calculate(struct imx214 *imx214, struct ccs_pll *pll,
1120+
unsigned int link_freq)
1121+
{
1122+
struct ccs_pll_limits limits = {
1123+
.min_ext_clk_freq_hz = 6000000,
1124+
.max_ext_clk_freq_hz = 27000000,
1125+
1126+
.vt_fr = {
1127+
.min_pre_pll_clk_div = 1,
1128+
.max_pre_pll_clk_div = 15,
1129+
/* Value is educated guess as we don't have a spec */
1130+
.min_pll_ip_clk_freq_hz = 6000000,
1131+
/* Value is educated guess as we don't have a spec */
1132+
.max_pll_ip_clk_freq_hz = 12000000,
1133+
.min_pll_multiplier = 12,
1134+
.max_pll_multiplier = 1200,
1135+
.min_pll_op_clk_freq_hz = 338000000,
1136+
.max_pll_op_clk_freq_hz = 1200000000,
1137+
},
1138+
.vt_bk = {
1139+
.min_sys_clk_div = 2,
1140+
.max_sys_clk_div = 4,
1141+
.min_pix_clk_div = 5,
1142+
.max_pix_clk_div = 10,
1143+
.min_pix_clk_freq_hz = 30000000,
1144+
.max_pix_clk_freq_hz = 120000000,
1145+
},
1146+
.op_bk = {
1147+
.min_sys_clk_div = 1,
1148+
.max_sys_clk_div = 2,
1149+
.min_pix_clk_div = 6,
1150+
.max_pix_clk_div = 10,
1151+
.min_pix_clk_freq_hz = 30000000,
1152+
.max_pix_clk_freq_hz = 120000000,
1153+
},
1154+
1155+
.min_line_length_pck_bin = IMX214_PPL_DEFAULT,
1156+
.min_line_length_pck = IMX214_PPL_DEFAULT,
1157+
};
1158+
unsigned int num_lanes = imx214->bus_cfg.bus.mipi_csi2.num_data_lanes;
1159+
1160+
/*
1161+
* There are no documented constraints on the sys clock frequency, for
1162+
* either branch. Recover them based on the PLL output clock frequency
1163+
* and sys_clk_div limits on one hand, and the pix clock frequency and
1164+
* the pix_clk_div limits on the other hand.
1165+
*/
1166+
limits.vt_bk.min_sys_clk_freq_hz =
1167+
max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.vt_bk.max_sys_clk_div,
1168+
limits.vt_bk.min_pix_clk_freq_hz * limits.vt_bk.min_pix_clk_div);
1169+
limits.vt_bk.max_sys_clk_freq_hz =
1170+
min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.vt_bk.min_sys_clk_div,
1171+
limits.vt_bk.max_pix_clk_freq_hz * limits.vt_bk.max_pix_clk_div);
1172+
1173+
limits.op_bk.min_sys_clk_freq_hz =
1174+
max(limits.vt_fr.min_pll_op_clk_freq_hz / limits.op_bk.max_sys_clk_div,
1175+
limits.op_bk.min_pix_clk_freq_hz * limits.op_bk.min_pix_clk_div);
1176+
limits.op_bk.max_sys_clk_freq_hz =
1177+
min(limits.vt_fr.max_pll_op_clk_freq_hz / limits.op_bk.min_sys_clk_div,
1178+
limits.op_bk.max_pix_clk_freq_hz * limits.op_bk.max_pix_clk_div);
1179+
1180+
memset(pll, 0, sizeof(*pll));
1181+
1182+
pll->bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
1183+
pll->op_lanes = num_lanes;
1184+
pll->vt_lanes = num_lanes;
1185+
pll->csi2.lanes = num_lanes;
1186+
1187+
pll->binning_horizontal = 1;
1188+
pll->binning_vertical = 1;
1189+
pll->scale_m = 1;
1190+
pll->scale_n = 1;
1191+
pll->bits_per_pixel =
1192+
IMX214_CSI_DATA_FORMAT_RAW10 & IMX214_BITS_PER_PIXEL_MASK;
1193+
pll->flags = CCS_PLL_FLAG_LANE_SPEED_MODEL;
1194+
pll->link_freq = link_freq;
1195+
pll->ext_clk_freq_hz = clk_get_rate(imx214->xclk);
1196+
1197+
return ccs_pll_calculate(imx214->dev, &limits, pll);
1198+
}
1199+
1200+
static int imx214_pll_update(struct imx214 *imx214)
1201+
{
1202+
u64 link_freq;
1203+
int ret;
1204+
1205+
link_freq = imx214->bus_cfg.link_frequencies[imx214->link_freq->val];
1206+
ret = imx214_pll_calculate(imx214, &imx214->pll, link_freq);
1207+
if (ret) {
1208+
dev_err(imx214->dev, "PLL calculations failed: %d\n", ret);
1209+
return ret;
1210+
}
1211+
1212+
ret = v4l2_ctrl_s_ctrl_int64(imx214->pixel_rate,
1213+
imx214->pll.pixel_rate_pixel_array);
1214+
if (ret) {
1215+
dev_err(imx214->dev, "failed to set pixel rate\n");
1216+
return ret;
1217+
}
1218+
1219+
return 0;
1220+
}
1221+
11081222
static int imx214_get_frame_interval(struct v4l2_subdev *subdev,
11091223
struct v4l2_subdev_state *sd_state,
11101224
struct v4l2_subdev_frame_interval *fival)
@@ -1211,55 +1325,63 @@ static int imx214_identify_module(struct imx214 *imx214)
12111325
return 0;
12121326
}
12131327

1214-
static int imx214_parse_fwnode(struct device *dev)
1328+
static int imx214_parse_fwnode(struct device *dev, struct imx214 *imx214)
12151329
{
1330+
struct v4l2_fwnode_endpoint *bus_cfg = &imx214->bus_cfg;
12161331
struct fwnode_handle *endpoint;
1217-
struct v4l2_fwnode_endpoint bus_cfg = {
1218-
.bus_type = V4L2_MBUS_CSI2_DPHY,
1219-
};
12201332
unsigned int i;
12211333
int ret;
12221334

12231335
endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(dev), NULL);
12241336
if (!endpoint)
12251337
return dev_err_probe(dev, -EINVAL, "endpoint node not found\n");
12261338

1227-
ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, &bus_cfg);
1339+
bus_cfg->bus_type = V4L2_MBUS_CSI2_DPHY;
1340+
ret = v4l2_fwnode_endpoint_alloc_parse(endpoint, bus_cfg);
1341+
fwnode_handle_put(endpoint);
12281342
if (ret) {
12291343
dev_err_probe(dev, ret, "parsing endpoint node failed\n");
1230-
goto done;
1344+
goto error;
12311345
}
12321346

12331347
/* Check the number of MIPI CSI2 data lanes */
1234-
if (bus_cfg.bus.mipi_csi2.num_data_lanes != 4) {
1348+
if (bus_cfg->bus.mipi_csi2.num_data_lanes != 4) {
12351349
ret = dev_err_probe(dev, -EINVAL,
12361350
"only 4 data lanes are currently supported\n");
1237-
goto done;
1351+
goto error;
12381352
}
12391353

1240-
if (bus_cfg.nr_of_link_frequencies != 1)
1354+
if (bus_cfg->nr_of_link_frequencies != 1)
12411355
dev_warn(dev, "Only one link-frequency supported, please review your DT. Continuing anyway\n");
12421356

1243-
for (i = 0; i < bus_cfg.nr_of_link_frequencies; i++) {
1244-
if (bus_cfg.link_frequencies[i] == IMX214_DEFAULT_LINK_FREQ)
1357+
for (i = 0; i < bus_cfg->nr_of_link_frequencies; i++) {
1358+
u64 freq = bus_cfg->link_frequencies[i];
1359+
struct ccs_pll pll;
1360+
1361+
if (!imx214_pll_calculate(imx214, &pll, freq))
12451362
break;
1246-
if (bus_cfg.link_frequencies[i] ==
1247-
IMX214_DEFAULT_LINK_FREQ_LEGACY) {
1363+
if (freq == IMX214_DEFAULT_LINK_FREQ_LEGACY) {
12481364
dev_warn(dev,
12491365
"link-frequencies %d not supported, please review your DT. Continuing anyway\n",
12501366
IMX214_DEFAULT_LINK_FREQ);
1367+
freq = IMX214_DEFAULT_LINK_FREQ;
1368+
if (imx214_pll_calculate(imx214, &pll, freq))
1369+
continue;
1370+
bus_cfg->link_frequencies[i] = freq;
12511371
break;
12521372
}
12531373
}
12541374

1255-
if (i == bus_cfg.nr_of_link_frequencies)
1375+
if (i == bus_cfg->nr_of_link_frequencies)
12561376
ret = dev_err_probe(dev, -EINVAL,
1257-
"link-frequencies %d not supported, please review your DT\n",
1258-
IMX214_DEFAULT_LINK_FREQ);
1377+
"link-frequencies %lld not supported, please review your DT\n",
1378+
bus_cfg->nr_of_link_frequencies ?
1379+
bus_cfg->link_frequencies[0] : 0);
12591380

1260-
done:
1261-
v4l2_fwnode_endpoint_free(&bus_cfg);
1262-
fwnode_handle_put(endpoint);
1381+
return 0;
1382+
1383+
error:
1384+
v4l2_fwnode_endpoint_free(&imx214->bus_cfg);
12631385
return ret;
12641386
}
12651387

@@ -1299,7 +1421,7 @@ static int imx214_probe(struct i2c_client *client)
12991421
return dev_err_probe(dev, PTR_ERR(imx214->regmap),
13001422
"failed to initialize CCI\n");
13011423

1302-
ret = imx214_parse_fwnode(dev);
1424+
ret = imx214_parse_fwnode(dev, imx214);
13031425
if (ret)
13041426
return ret;
13051427

@@ -1310,7 +1432,9 @@ static int imx214_probe(struct i2c_client *client)
13101432
* Enable power initially, to avoid warnings
13111433
* from clk_disable on power_off
13121434
*/
1313-
imx214_power_on(imx214->dev);
1435+
ret = imx214_power_on(imx214->dev);
1436+
if (ret < 0)
1437+
goto error_fwnode;
13141438

13151439
ret = imx214_identify_module(imx214);
13161440
if (ret)
@@ -1341,6 +1465,12 @@ static int imx214_probe(struct i2c_client *client)
13411465
pm_runtime_set_active(imx214->dev);
13421466
pm_runtime_enable(imx214->dev);
13431467

1468+
ret = imx214_pll_update(imx214);
1469+
if (ret < 0) {
1470+
dev_err_probe(dev, ret, "failed to update PLL\n");
1471+
goto error_subdev_cleanup;
1472+
}
1473+
13441474
ret = v4l2_async_register_subdev_sensor(&imx214->sd);
13451475
if (ret < 0) {
13461476
dev_err_probe(dev, ret,
@@ -1366,6 +1496,9 @@ static int imx214_probe(struct i2c_client *client)
13661496
error_power_off:
13671497
imx214_power_off(imx214->dev);
13681498

1499+
error_fwnode:
1500+
v4l2_fwnode_endpoint_free(&imx214->bus_cfg);
1501+
13691502
return ret;
13701503
}
13711504

@@ -1378,6 +1511,8 @@ static void imx214_remove(struct i2c_client *client)
13781511
v4l2_subdev_cleanup(sd);
13791512
media_entity_cleanup(&imx214->sd.entity);
13801513
v4l2_ctrl_handler_free(&imx214->ctrls);
1514+
v4l2_fwnode_endpoint_free(&imx214->bus_cfg);
1515+
13811516
pm_runtime_disable(&client->dev);
13821517
if (!pm_runtime_status_suspended(&client->dev)) {
13831518
imx214_power_off(imx214->dev);

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