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Why are there multiple tech LEFs
- prtech/techLEF/N551P6M.lef
- prtech/techLEF/N551P6M_ieda.lef
and multiple std cell LEFs, eg
- IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/lef/ics55_LLSC_H7CR.lef
- IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/lef/ics55_LLSC_H7CR_ant.lef
- IP/STD_cell/ics55_LLSC_H7C_V1p10C100/ics55_LLSC_H7CR/lef/ics55_LLSC_H7CR_ieda.lef
There is no GDS for any of the cells nor any RAMs. Are those planned?
Is there any recommended PDN structure or well tap rules?
Blebowski and Andrea-Spitale
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