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Merge pull request #136 from os-fpga/pass_sim_1.6.0
Pulling SIMs release 1.6.0 into main.
2 parents eaa0ee8 + 0cc5f1e commit a6a73f9

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19 files changed

+395
-137
lines changed

19 files changed

+395
-137
lines changed

‎sim_models/verilog/BOOT_CLOCK.v‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -12,11 +12,13 @@ module BOOT_CLOCK #(
1212
) (
1313
output reg O = 1'b0 // Clock output
1414
);
15-
localparam HALF_PERIOD = PERIOD/2.0;
15+
16+
localparam HALF_PERIOD = PERIOD/2.0;
1617

1718

1819
always
1920
#HALF_PERIOD O <= ~O;
21+
2022
initial begin
2123

2224
if ((PERIOD < 16.0) || (PERIOD > 30.0)) begin

‎sim_models/verilog/CARRY.v‎

Lines changed: 15 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -15,20 +15,28 @@ module CARRY (
1515
output COUT // Carry out
1616
);
1717

18-
assign {COUT, O} = {P ? CIN : G, P ^ CIN};
18+
assign {COUT, O} = {P ? CIN : G, P ^ CIN};
19+
20+
`ifndef SYNTHESIS
21+
`ifdef TIMED_SIM
22+
23+
specparam T1 = 0.3;
24+
specparam T2 = 0.4;
1925

20-
`ifndef SYNTHESIS
21-
specify
2226

27+
specify
28+
2329
if (P == 1'b1)
24-
(CIN => COUT) = (0, 0);
30+
(CIN => COUT) = (T1, T2);
2531
if (P == 1'b0)
26-
(G => COUT) = (0, 0);
32+
(G => COUT) = (T1, T2);
2733

28-
( P, CIN *> O ) = (0, 0);
34+
( P, CIN *> O ) = (T1, T2);
2935

3036
endspecify
31-
`endif // `ifndef SYNTHESIS
3237

38+
`endif // `ifdef TIMED_SIM
39+
`endif // `ifndef SYNTHESIS
40+
3341
endmodule
3442
`endcelldefine

‎sim_models/verilog/DFFNRE.v‎

Lines changed: 58 additions & 54 deletions
Original file line numberDiff line numberDiff line change
@@ -16,66 +16,70 @@ module DFFNRE (
1616
output reg Q = 1'b0 // Data Output
1717
);
1818

19-
always @(negedge C, negedge R)
20-
if (!R)
21-
Q <= 1'b0;
22-
else if (E)
23-
Q <= D;
19+
always @(negedge C, negedge R)
20+
if (!R)
21+
Q <= 1'b0;
22+
else if (E)
23+
Q <= D;
2424

25-
`ifndef SYNTHESIS
26-
wire C_D_SDFCHK;
27-
wire C_nD_SDFCHK;
28-
wire nC_D_SDFCHK;
29-
wire nC_nD_SDFCHK;
30-
wire R_D_SDFCHK;
31-
wire R_nD_SDFCHK;
32-
wire R_SDFCHK;
33-
wire D_SDFCHK;
25+
wire C_D_SDFCHK;
26+
wire C_nD_SDFCHK;
27+
wire nC_D_SDFCHK;
28+
wire nC_nD_SDFCHK;
29+
wire R_D_SDFCHK;
30+
wire R_nD_SDFCHK;
31+
wire R_SDFCHK;
32+
wire D_SDFCHK;
3433

35-
assign C_D_SDFCHK = C & D;
36-
assign C_nD_SDFCHK = C & !D;
37-
assign nC_D_SDFCHK = !C & D;
38-
assign nC_nD_SDFCHK = !C & !D;
39-
assign R_D_SDFCHK = R & D;
40-
assign R_nD_SDFCHK = R & !D;
41-
assign R_SDFCHK = R;
42-
assign D_SDFCHK = D;
34+
assign C_D_SDFCHK = C & D;
35+
assign C_nD_SDFCHK = C & !D;
36+
assign nC_D_SDFCHK = !C & D;
37+
assign nC_nD_SDFCHK = !C & !D;
38+
assign R_D_SDFCHK = R & D;
39+
assign R_nD_SDFCHK = R & !D;
40+
assign R_SDFCHK = R;
41+
assign D_SDFCHK = D;
4342

43+
`ifndef SYNTHESIS
44+
`ifdef TIMED_SIM
45+
specparam T1 = 0.3;
46+
specparam T2 = 0.4;
4447

45-
specify
46-
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
47-
(negedge R => (Q+:1'b0)) = (0, 0);
48-
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
49-
(negedge R => (Q+:1'b0)) = (0, 0);
50-
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
51-
(negedge R => (Q+:1'b0)) = (0, 0);
52-
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
53-
(negedge R => (Q+:1'b0)) = (0, 0);
54-
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
55-
(negedge R => (Q+:1'b0)) = (0, 0);
56-
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
57-
(negedge R => (Q+:1'b0)) = (0, 0);
58-
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
59-
(negedge R => (Q+:1'b0)) = (0, 0);
60-
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
61-
(negedge R => (Q+:1'b0)) = (0, 0);
62-
(negedge C => (Q+:D)) = (0, 0);
48+
specify
49+
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
50+
(negedge R => (Q+:1'b0)) = (T1, 0);
51+
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
52+
(negedge R => (Q+:1'b0)) = (T1, T2);
53+
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
54+
(negedge R => (Q+:1'b0)) = (T1, T2);
55+
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
56+
(negedge R => (Q+:1'b0)) = (T1, T2);
57+
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
58+
(negedge R => (Q+:1'b0)) = (T1, T2);
59+
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
60+
(negedge R => (Q+:1'b0)) = (T1, T2);
61+
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
62+
(negedge R => (Q+:1'b0)) = (T1, T2);
63+
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
64+
(negedge R => (Q+:1'b0)) = (T1, T2);
65+
(negedge C => (Q+:D)) = (T1, T2);
6366

64-
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
65-
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
66-
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
67-
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
68-
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
69-
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
70-
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
71-
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
67+
$width (negedge R &&& C_D_SDFCHK, T1, T2, notifier);
68+
$width (negedge R &&& C_nD_SDFCHK, T1, T2, notifier);
69+
$width (negedge R &&& nC_D_SDFCHK, T1, T2, notifier);
70+
$width (negedge R &&& nC_nD_SDFCHK, T1, T2, notifier);
71+
$width (posedge C &&& R_D_SDFCHK, T1, T2, notifier);
72+
$width (negedge C &&& R_D_SDFCHK, T1, T2, notifier);
73+
$width (posedge C &&& R_nD_SDFCHK, T1, T2, notifier);
74+
$width (negedge C &&& R_nD_SDFCHK, T1, T2, notifier);
7275

73-
$setuphold (negedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
74-
$setuphold (negedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
75-
$recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier);
76-
$hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier);
77-
endspecify
78-
`endif // `ifndef SYNTHESIS
76+
$setuphold (negedge C &&& R_SDFCHK, posedge D , T1, T2, notifier);
77+
$setuphold (negedge C &&& R_SDFCHK, negedge D , T1, T2, notifier);
78+
$recovery (posedge R &&& D_SDFCHK, negedge C &&& D_SDFCHK, 0, notifier);
79+
$hold (negedge C &&& D_SDFCHK, posedge R , 0, notifier);
80+
endspecify
7981

82+
`endif // `ifdef TIMED_SIM
83+
`endif // `ifndef SYNTHESIS
8084
endmodule
8185
`endcelldefine

‎sim_models/verilog/DFFRE.v‎

Lines changed: 66 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -16,67 +16,77 @@ module DFFRE (
1616
output reg Q = 1'b0 // Data Output
1717
);
1818

19-
always @(posedge C, negedge R)
20-
if (!R)
21-
Q <= 1'b0;
22-
else if (E)
23-
Q <= D;
2419

25-
`ifndef SYNTHESIS
26-
wire C_D_SDFCHK;
27-
wire C_nD_SDFCHK;
28-
wire nC_D_SDFCHK;
29-
wire nC_nD_SDFCHK;
30-
wire R_D_SDFCHK;
31-
wire R_nD_SDFCHK;
32-
wire R_SDFCHK;
33-
wire D_SDFCHK;
20+
always @(posedge C, negedge R)
21+
if (!R)
22+
Q <= 1'b0;
23+
else if (E)
24+
Q <= D;
3425

35-
assign C_D_SDFCHK = C & D;
36-
assign C_nD_SDFCHK = C & !D;
37-
assign nC_D_SDFCHK = !C & D;
38-
assign nC_nD_SDFCHK = !C & !D;
39-
assign R_D_SDFCHK = R & D;
40-
assign R_nD_SDFCHK = R & !D;
41-
assign R_SDFCHK = R;
42-
assign D_SDFCHK = D;
4326

27+
wire C_D_SDFCHK;
28+
wire C_nD_SDFCHK;
29+
wire nC_D_SDFCHK;
30+
wire nC_nD_SDFCHK;
31+
wire R_D_SDFCHK;
32+
wire R_nD_SDFCHK;
33+
wire R_SDFCHK;
34+
wire D_SDFCHK;
4435

45-
specify
46-
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
47-
(negedge R => (Q+:1'b0)) = (0, 0);
48-
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
49-
(negedge R => (Q+:1'b0)) = (0, 0);
50-
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
51-
(negedge R => (Q+:1'b0)) = (0, 0);
52-
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
53-
(negedge R => (Q+:1'b0)) = (0, 0);
54-
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
55-
(negedge R => (Q+:1'b0)) = (0, 0);
56-
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
57-
(negedge R => (Q+:1'b0)) = (0, 0);
58-
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
59-
(negedge R => (Q+:1'b0)) = (0, 0);
60-
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
61-
(negedge R => (Q+:1'b0)) = (0, 0);
62-
(posedge C => (Q+:D)) = (0, 0);
36+
assign C_D_SDFCHK = C & D;
37+
assign C_nD_SDFCHK = C & !D;
38+
assign nC_D_SDFCHK = !C & D;
39+
assign nC_nD_SDFCHK = !C & !D;
40+
assign R_D_SDFCHK = R & D;
41+
assign R_nD_SDFCHK = R & !D;
42+
assign R_SDFCHK = R;
43+
assign D_SDFCHK = D;
44+
45+
46+
47+
`ifndef SYNTHESIS
48+
`ifdef TIMED_SIM
49+
specparam T1 = 0.3;
50+
specparam T2 = 0.4;
51+
52+
specify
53+
if (C == 1'b0 && D == 1'b1 && E == 1'b0)
54+
(negedge R => (Q+:1'b0)) = (T1, T2);
55+
if (C == 1'b0 && D == 1'b0 && E == 1'b0)
56+
(negedge R => (Q+:1'b0)) = (T1, T2);
57+
if (C == 1'b1 && D == 1'b1 && E == 1'b0)
58+
(negedge R => (Q+:1'b0)) = (T1, T2);
59+
if (C == 1'b1 && D == 1'b0 && E == 1'b0)
60+
(negedge R => (Q+:1'b0)) = (T1, T2);
61+
if (C == 1'b0 && D == 1'b1 && E == 1'b1)
62+
(negedge R => (Q+:1'b0)) = (T1, T2);
63+
if (C == 1'b0 && D == 1'b0 && E == 1'b1)
64+
(negedge R => (Q+:1'b0)) = (T1, T2);
65+
if (C == 1'b1 && D == 1'b1 && E == 1'b1)
66+
(negedge R => (Q+:1'b0)) = (T1, T2);
67+
if (C == 1'b1 && D == 1'b0 && E == 1'b1)
68+
(negedge R => (Q+:1'b0)) = (T1, T2);
69+
(posedge C => (Q+:D)) = (T1, T2);
70+
71+
$width (negedge R &&& C_D_SDFCHK, T1, T2, notifier);
72+
$width (negedge R &&& C_nD_SDFCHK, T1, T2, notifier);
73+
$width (negedge R &&& nC_D_SDFCHK, T1, T2, notifier);
74+
$width (negedge R &&& nC_nD_SDFCHK, T1, T2, notifier);
75+
$width (posedge C &&& R_D_SDFCHK, T1, T2, notifier);
76+
$width (negedge C &&& R_D_SDFCHK, T1, T2, notifier);
77+
$width (posedge C &&& R_nD_SDFCHK, T1, T2, notifier);
78+
$width (negedge C &&& R_nD_SDFCHK, T1, T2, notifier);
79+
80+
$setuphold (posedge C &&& R_SDFCHK, posedge D , T1, T2, notifier);
81+
$setuphold (posedge C &&& R_SDFCHK, negedge D , T1, T2, notifier);
82+
$recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier);
83+
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
84+
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
85+
endspecify
86+
87+
`endif // `ifdef TIMED_SIM
88+
`endif // `ifndef SYNTHESIS
6389

64-
$width (negedge R &&& C_D_SDFCHK, 0, 0, notifier);
65-
$width (negedge R &&& C_nD_SDFCHK, 0, 0, notifier);
66-
$width (negedge R &&& nC_D_SDFCHK, 0, 0, notifier);
67-
$width (negedge R &&& nC_nD_SDFCHK, 0, 0, notifier);
68-
$width (posedge C &&& R_D_SDFCHK, 0, 0, notifier);
69-
$width (negedge C &&& R_D_SDFCHK, 0, 0, notifier);
70-
$width (posedge C &&& R_nD_SDFCHK, 0, 0, notifier);
71-
$width (negedge C &&& R_nD_SDFCHK, 0, 0, notifier);
7290

73-
$setuphold (posedge C &&& R_SDFCHK, posedge D , 0, 0, notifier);
74-
$setuphold (posedge C &&& R_SDFCHK, negedge D , 0, 0, notifier);
75-
$recovery (posedge R &&& D_SDFCHK, posedge C &&& D_SDFCHK, 0, notifier);
76-
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
77-
$hold (posedge C &&& D_SDFCHK, posedge R , 0, notifier);
78-
endspecify
79-
`endif // `ifndef SYNTHESIS
80-
8191
endmodule
8292
`endcelldefine

‎sim_models/verilog/DLY_VALUE_MUX.v‎

Lines changed: 51 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,5 +59,56 @@ begin
5959
endcase
6060
end
6161

62+
63+
64+
65+
`ifndef SYNTHESIS
66+
`ifdef TIMED_SIM
67+
specparam T1 = 0.4;
68+
69+
specify
70+
if (DLY_ADDR == 5'd0)
71+
(DLY_TAP0_VAL => DLY_TAP_VALUE) = T1;
72+
if (DLY_ADDR == 5'd1)
73+
(DLY_TAP1_VAL => DLY_TAP_VALUE) = T1;
74+
if (DLY_ADDR == 5'd2)
75+
(DLY_TAP2_VAL => DLY_TAP_VALUE) = T1;
76+
if (DLY_ADDR == 5'd3)
77+
(DLY_TAP3_VAL => DLY_TAP_VALUE) = T1;
78+
if (DLY_ADDR == 5'd4)
79+
(DLY_TAP4_VAL => DLY_TAP_VALUE) = T1;
80+
if (DLY_ADDR == 5'd5)
81+
(DLY_TAP5_VAL => DLY_TAP_VALUE) = T1;
82+
if (DLY_ADDR == 5'd6)
83+
(DLY_TAP6_VAL => DLY_TAP_VALUE) = T1;
84+
if (DLY_ADDR == 5'd7)
85+
(DLY_TAP7_VAL => DLY_TAP_VALUE) = T1;
86+
if (DLY_ADDR == 5'd8)
87+
(DLY_TAP8_VAL => DLY_TAP_VALUE) = T1;
88+
if (DLY_ADDR == 5'd9)
89+
(DLY_TAP9_VAL => DLY_TAP_VALUE) = T1;
90+
if (DLY_ADDR == 5'd10)
91+
(DLY_TAP10_VAL => DLY_TAP_VALUE) = T1;
92+
if (DLY_ADDR == 5'd12)
93+
(DLY_TAP12_VAL => DLY_TAP_VALUE) = T1;
94+
if (DLY_ADDR == 5'd13)
95+
(DLY_TAP13_VAL => DLY_TAP_VALUE) = T1;
96+
if (DLY_ADDR == 5'd14)
97+
(DLY_TAP14_VAL => DLY_TAP_VALUE) = T1;
98+
if (DLY_ADDR == 5'd15)
99+
(DLY_TAP15_VAL => DLY_TAP_VALUE) = T1;
100+
if (DLY_ADDR == 5'd16)
101+
(DLY_TAP16_VAL => DLY_TAP_VALUE) = T1;
102+
if (DLY_ADDR == 5'd17)
103+
(DLY_TAP17_VAL => DLY_TAP_VALUE) = T1;
104+
if (DLY_ADDR == 5'd18)
105+
(DLY_TAP18_VAL => DLY_TAP_VALUE) = T1;
106+
if (DLY_ADDR == 5'd19)
107+
(DLY_TAP19_VAL => DLY_TAP_VALUE) = T1;
108+
endspecify
109+
110+
`endif // `ifdef TIMED_SIM
111+
`endif // `ifndef SYNTHESIS
112+
62113
endmodule
63114
`endcelldefine

‎sim_models/verilog/I_BUF.v‎

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -25,13 +25,18 @@ module I_BUF #(
2525

2626
assign O = EN ? I : 1'b0;
2727

28-
`ifndef SYNTHESIS
29-
specify
30-
if (EN == 1'b1)
31-
(I => O) = (0, 0);
32-
endspecify
28+
`ifndef SYNTHESIS
29+
`ifdef TIMED_SIM
30+
specify
31+
specparam T1 = 0.5;
32+
33+
if (EN == 1'b1)
34+
(I => O) = (T1);
35+
endspecify
36+
`endif // `ifdef TIMED_SIM
3337
`endif // `ifndef SYNTHESIS
3438

39+
3540
initial begin
3641
case(WEAK_KEEPER)
3742
"NONE" ,

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