From be0b58a0e094f007cd42b1513db48cde17b3ba8f Mon Sep 17 00:00:00 2001
From: Lenny Truong <lenny@stanford.edu>
Date: Wed, 12 May 2021 14:09:30 -0700
Subject: [PATCH 1/2] init test

---
 tests/test_verilog/foo.py                   | 24 +++++++++++++++++++++
 tests/test_verilog/test_get_inst_verilog.py | 21 ++++++++++++++++++
 2 files changed, 45 insertions(+)
 create mode 100644 tests/test_verilog/foo.py
 create mode 100644 tests/test_verilog/test_get_inst_verilog.py

diff --git a/tests/test_verilog/foo.py b/tests/test_verilog/foo.py
new file mode 100644
index 000000000..c5de9f05d
--- /dev/null
+++ b/tests/test_verilog/foo.py
@@ -0,0 +1,24 @@
+import magma as m
+
+
+class T(m.Product):
+    x = m.Bit
+    y = m.Bits[2]
+
+
+class Baz(m.Circuit):
+    io = m.IO(I=m.In(T), O=m.Out(T))
+    io.O @= io.I
+
+
+class Bar(m.Circuit):
+    io = m.IO(I=m.In(T), O=m.Out(T))
+    io.O @= Baz()(io.I)
+
+
+class Foo(m.Circuit):
+    io = m.IO(I=m.In(T), O=m.Out(T))
+    io.O @= Bar()(io.I)
+
+
+m.compile("build/Foo", Foo)
diff --git a/tests/test_verilog/test_get_inst_verilog.py b/tests/test_verilog/test_get_inst_verilog.py
new file mode 100644
index 000000000..c0f423290
--- /dev/null
+++ b/tests/test_verilog/test_get_inst_verilog.py
@@ -0,0 +1,21 @@
+import os
+import magma as m
+
+
+class T(m.Product):
+    x = m.Bit
+    y = m.Bits[2]
+
+
+def test_get_inst_verilog():
+    dirname = os.path.abspath(os.path.dirname(__file__))
+    os.system(f"cd {dirname} && python foo.py")
+    # TODO: Need API to load with a symbol table
+    # Also, would be nice to derive a wrapper (e.g. reconstruct the tuples)
+    Foo = m.define_from_verilog_file(f"{dirname}/build/Foo.v")[0]
+
+    class Main(m.Circuit):
+        io = m.IO(I=m.In(T), O=m.Out(T))
+        io.O @= T(*Foo()(io.I.x, io.I.y))
+
+    m.compile("build/Main", Main)

From 029d45a27ae2d48ec3afa1f45d3422c9f294971a Mon Sep 17 00:00:00 2001
From: Lenny Truong <lenny@stanford.edu>
Date: Wed, 12 May 2021 14:16:02 -0700
Subject: [PATCH 2/2] Add notes

---
 tests/test_verilog/foo.py                   |  4 ++--
 tests/test_verilog/test_get_inst_verilog.py | 13 ++++++++++++-
 2 files changed, 14 insertions(+), 3 deletions(-)

diff --git a/tests/test_verilog/foo.py b/tests/test_verilog/foo.py
index c5de9f05d..0b984b8a3 100644
--- a/tests/test_verilog/foo.py
+++ b/tests/test_verilog/foo.py
@@ -13,12 +13,12 @@ class Baz(m.Circuit):
 
 class Bar(m.Circuit):
     io = m.IO(I=m.In(T), O=m.Out(T))
-    io.O @= Baz()(io.I)
+    io.O @= Baz(name="baz")(io.I)
 
 
 class Foo(m.Circuit):
     io = m.IO(I=m.In(T), O=m.Out(T))
-    io.O @= Bar()(io.I)
+    io.O @= Bar(name="bar")(io.I)
 
 
 m.compile("build/Foo", Foo)
diff --git a/tests/test_verilog/test_get_inst_verilog.py b/tests/test_verilog/test_get_inst_verilog.py
index c0f423290..1ffaa75fb 100644
--- a/tests/test_verilog/test_get_inst_verilog.py
+++ b/tests/test_verilog/test_get_inst_verilog.py
@@ -16,6 +16,17 @@ def test_get_inst_verilog():
 
     class Main(m.Circuit):
         io = m.IO(I=m.In(T), O=m.Out(T))
-        io.O @= T(*Foo()(io.I.x, io.I.y))
+        foo = Foo()
+        # TODO: If we can reconstruct the original tuple for foo, we can just
+        # pass the packed tuple rather than x, y individually
+        io.O @= T(*foo(io.I.x, io.I.y))
+        # TODO: Need API to refer to instance nested inside a verilog imported
+        # module (resolved using the symbol table)
+        # Proposed API is to pass a name for instances, hierarchical reference
+        # using a variable number of string arguments
+        # Then the instance reference provides attributes for magma's standard
+        # type syntax (e.g. dot notation tuples, subscript for arrays)
+        ref = foo.get_instance("bar", "baz").O.x[1]
+        m.inline_verilog('assert ({A} == 1) else $error("ERROR");', A=ref)
 
     m.compile("build/Main", Main)