Feature consideration? #263
Description
After exploring and playing with pymtl3, I can feel how this can speed up hardware development. I have some suggestions for features that might enhance the experience of using pymtl3.
Better slicing
Allow the Bits slice to work like Python slicing. For example allow, a[start:] or a[:end] for accessing a[start:nBits] or a[0:end].
Singed bit
Allow Bits to be signed or provide a $signed like Verilog does. This is just something nice to have out of the box instead of me needing to write it when simulating and testing with negative values.
Making more function and class static
For example, things like b1 or b32 are statically available, which allows for static analysis from IDE and hinting. Things added in simulation pass like sim_tick, letting those also be statically available. Just seeing what function is available by the IDE static analysis saves a lot of time in finding relevant information. Another benefit is you can document each of the individual functions within the code, and the IDE will display them, which results in less documentation needing to be maintained. A good example is Networkx. They have the best open-source documentation I have ever seen.
Introducing match
Starting from Python3.10, the match statement is available, and it would be nice if we could use them for constructing hardware similar to how Verilog have a case statement.
Variable naming control
Some constant variables will be named __const__something or __tmpvar__something. It would be nice if passes were available for renaming them.
Loop unrolling
Including passes that unroll for loop statements. This might defeat the purpose of generating readable Verilog. Sometimes, reading the statement as it is rolled is more difficult, but easier to construct with a loop.
Once again, thanks for the great work.