Expose MSI-X configuration

Author: devsnek

src/device/blk.rs

@@ -378,6 +378,16 @@ impl<H: Hal, T: Transport> VirtIOBlk<H, T> {
     pub fn virt_queue_size(&self) -> u16 {
         QUEUE_SIZE
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
 }
 
 impl<H: Hal, T: Transport> Drop for VirtIOBlk<H, T> {

src/device/console.rs

@@ -246,6 +246,16 @@ impl<H: Hal, T: Transport> VirtIOConsole<H, T> {
             Err(Error::Unsupported)
         }
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
 }
 
 impl<H: Hal, T: Transport> Write for VirtIOConsole<H, T> {

src/device/gpu.rs

@@ -181,6 +181,16 @@ impl<H: Hal, T: Transport> VirtIOGpu<H, T> {
         Ok(())
     }
 
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
+
     /// Send a request to the device and block for a response.
     fn request<Req: IntoBytes + Immutable, Rsp: FromBytes>(&mut self, req: Req) -> Result<Rsp> {
         req.write_to_prefix(&mut self.queue_buf_send).unwrap();

src/device/input.rs

@@ -196,6 +196,16 @@ impl<H: Hal, T: Transport> VirtIOInput<H, T> {
             Err(Error::IoError)
         }
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
 }
 
 // SAFETY: The config space can be accessed from any thread.

src/device/net/dev.rs

@@ -122,4 +122,14 @@ impl<H: Hal, T: Transport, const QUEUE_SIZE: usize> VirtIONet<H, T, QUEUE_SIZE>
     pub fn send(&mut self, tx_buf: TxBuffer) -> Result {
         self.inner.send(tx_buf.packet())
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        self.inner.transport()
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        self.inner.transport_mut()
+    }
 }

src/device/net/dev_raw.rs

@@ -266,6 +266,16 @@ impl<H: Hal, T: Transport, const QUEUE_SIZE: usize> VirtIONetRaw<H, T, QUEUE_SIZ
         // SAFETY: This `rx_buf` is the same one passed to `receive_begin`.
         unsafe { self.receive_complete(token, rx_buf) }
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
 }
 
 impl<H: Hal, T: Transport, const QUEUE_SIZE: usize> Drop for VirtIONetRaw<H, T, QUEUE_SIZE> {

src/device/rng.rs

@@ -49,6 +49,16 @@ impl<H: Hal, T: Transport> VirtIORng<H, T> {
     pub fn ack_interrupt(&mut self) -> bool {
         self.transport.ack_interrupt()
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
 }
 
 impl<H: Hal, T: Transport> Drop for VirtIORng<H, T> {

src/device/socket/vsock.rs

@@ -424,6 +424,16 @@ impl<H: Hal, T: Transport, const RX_BUFFER_SIZE: usize> VirtIOSocket<H, T, RX_BU
         Ok(())
     }
 
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
+
     fn send_packet_to_tx_queue(&mut self, header: &VirtioVsockHdr, buffer: &[u8]) -> Result {
         let _len = if buffer.is_empty() {
             self.tx

src/device/sound.rs

@@ -726,6 +726,16 @@ impl<H: Hal, T: Transport> VirtIOSound<H, T> {
             }
         })
     }
+
+    /// Get the underlying transport.
+    pub fn transport(&self) -> &T {
+        &self.transport
+    }
+
+    /// Get the underlying transport.
+    pub fn transport_mut(&mut self) -> &mut T {
+        &mut self.transport
+    }
 }
 
 /// The status of the PCM stream.

src/transport/pci.rs

@@ -366,6 +366,30 @@ impl Transport for PciTransport {
     }
 }
 
+impl PciTransport {
+    /// Get the MSI-X vector for config.
+    pub fn get_config_msix_vector(&self) -> u16 {
+        field_shared!(self.common_cfg, config_msix_vector).read()
+    }
+
+    /// Set the MSI-X vector for config.
+    pub fn set_config_msix_vector(&mut self, vector: u16) {
+        field!(self.common_cfg, config_msix_vector).write(vector);
+    }
+
+    /// Get the MSI-X vector for a queue.
+    pub fn get_queue_msix_vector(&mut self, queue: u16) -> u16 {
+        field!(self.common_cfg, queue_select).write(queue);
+        field_shared!(self.common_cfg, queue_msix_vector).read()
+    }
+
+    /// Set the MSI-X vector for a queue.
+    pub fn set_queue_msix_vector(&mut self, queue: u16, vector: u16) {
+        field!(self.common_cfg, queue_select).write(queue);
+        field!(self.common_cfg, queue_msix_vector).write(vector);
+    }
+}
+
 // SAFETY: MMIO can be done from any thread or CPU core.
 unsafe impl Send for PciTransport {}
 
@@ -388,7 +412,7 @@ pub(crate) struct CommonCfg {
     pub device_feature: ReadPure<u32>,
     pub driver_feature_select: ReadPureWrite<u32>,
     pub driver_feature: ReadPureWrite<u32>,
-    pub msix_config: ReadPureWrite<u16>,
+    pub config_msix_vector: ReadPureWrite<u16>,
     pub num_queues: ReadPure<u16>,
     pub device_status: ReadPureWrite<u8>,
     pub config_generation: ReadPure<u8>,