@@ -453,6 +453,10 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
453453 } else {
454454 reg_t ad = PTE_A | ((type == STORE) * PTE_D);
455455
456+ int napot_bits = ((pte & PTE_N) ? (ctz (ppn) + 1 ) : 0 );
457+ if (((pte & PTE_N) && (ppn == 0 || i != 0 )) || (napot_bits != 0 && napot_bits != 4 ))
458+ break ;
459+
456460 if ((pte & ad) != ad) {
457461 if (hade) {
458462 // set accessed and possibly dirty bits
@@ -466,10 +470,6 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty
466470 reg_t vpn = gpa >> PGSHIFT;
467471 reg_t page_mask = (reg_t (1 ) << PGSHIFT) - 1 ;
468472
469- int napot_bits = ((pte & PTE_N) ? (ctz (ppn) + 1 ) : 0 );
470- if (((pte & PTE_N) && (ppn == 0 || i != 0 )) || (napot_bits != 0 && napot_bits != 4 ))
471- break ;
472-
473473 reg_t page_base = ((ppn & ~((reg_t (1 ) << napot_bits) - 1 ))
474474 | (vpn & ((reg_t (1 ) << napot_bits) - 1 ))
475475 | (vpn & ((reg_t (1 ) << ptshift) - 1 ))) << PGSHIFT;
@@ -571,6 +571,10 @@ reg_t mmu_t::walk(mem_access_info_t access_info)
571571 } else {
572572 reg_t ad = PTE_A | ((type == STORE) * PTE_D);
573573
574+ int napot_bits = ((pte & PTE_N) ? (ctz (ppn) + 1 ) : 0 );
575+ if (((pte & PTE_N) && (ppn == 0 || i != 0 )) || (napot_bits != 0 && napot_bits != 4 ))
576+ break ;
577+
574578 if ((pte & ad) != ad) {
575579 if (hade) {
576580 // Check for write permission to the first-stage PT in second-stage
@@ -587,10 +591,6 @@ reg_t mmu_t::walk(mem_access_info_t access_info)
587591 // for superpage or Svnapot NAPOT mappings, make a fake leaf PTE for the TLB's benefit.
588592 reg_t vpn = addr >> PGSHIFT;
589593
590- int napot_bits = ((pte & PTE_N) ? (ctz (ppn) + 1 ) : 0 );
591- if (((pte & PTE_N) && (ppn == 0 || i != 0 )) || (napot_bits != 0 && napot_bits != 4 ))
592- break ;
593-
594594 reg_t page_base = ((ppn & ~((reg_t (1 ) << napot_bits) - 1 ))
595595 | (vpn & ((reg_t (1 ) << napot_bits) - 1 ))
596596 | (vpn & ((reg_t (1 ) << ptshift) - 1 ))) << PGSHIFT;
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