feat: add SystemVerilog backend generator

Implements a new backend generator for SystemVerilog output, matching
the exact format used by riscv-opcodes/inst.sverilog. This provides
direct compatibility with hardware designs using the riscv-opcodes
SystemVerilog package format.

Features:
- Generates SystemVerilog package with instruction and CSR definitions
- Outputs 32-bit instruction patterns with proper bit encoding
- Handles compressed (16-bit) instructions correctly
- Supports all standard RISC-V extensions
- Integrated with the ./do build system as gen:sverilog task

The generator produces output identical to riscv-opcodes format:
- Instructions as 'localparam [31:0] NAME = 32'bpattern'
- CSRs as 'localparam logic [11:0] CSR_NAME = 12'haddr'
- Proper alignment and formatting for readability

Tested against riscv-opcodes/inst.sverilog to ensure format compatibility.

Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>

Author: AFOliveira

backends/generators/sverilog/sverilog_generator.py

@@ -0,0 +1,179 @@
+#!/usr/bin/env python3
+
+import argparse
+import os
+import sys
+import logging
+from pathlib import Path
+
+# Add parent directory to path for imports
+sys.path.insert(0, os.path.dirname(os.path.dirname(os.path.abspath(__file__))))
+
+from generator import load_instructions, load_csrs
+
+
+def format_instruction_name(name):
+    """Format instruction name for SystemVerilog (uppercase with underscores)."""
+    # Handle compressed instructions
+    if name.startswith("c."):
+        name = "C_" + name[2:]
+    # Replace dots with underscores and convert to uppercase
+    return name.replace(".", "_").upper()
+
+
+def format_csr_name(name):
+    """Format CSR name for SystemVerilog (uppercase with underscores)."""
+    return "CSR_" + name.replace(".", "_").upper()
+
+
+def match_to_sverilog_bits(match_str, is_compressed=False):
+    """Convert a match string to SystemVerilog bit pattern."""
+    if not match_str:
+        return "32'b" + "?" * 32
+    
+    # For compressed instructions (16-bit), we need to handle them differently
+    # The riscv-opcodes format puts the 16-bit pattern in the lower 16 bits
+    # with the upper 16 bits as wildcards
+    if is_compressed or len(match_str) == 16:
+        # Pad with wildcards on the left for 16-bit instructions
+        match_str = "?" * 16 + match_str
+    elif len(match_str) < 32:
+        # For other cases, pad on the right
+        match_str = match_str + "-" * (32 - len(match_str))
+    
+    # Convert to SystemVerilog format (0, 1, or ?)
+    result = []
+    for bit in match_str:
+        if bit == "0":
+            result.append("0")
+        elif bit == "1":
+            result.append("1")
+        else:  # '-' or any other character
+            result.append("?")
+    
+    return "32'b" + "".join(result)
+
+
+def generate_sverilog(instructions, csrs, output_file):
+    """Generate SystemVerilog package file."""
+    with open(output_file, "w") as f:
+        # Write header
+        f.write("\n/* Automatically generated by parse_opcodes */\n")
+        f.write("package riscv_instr;\n")
+        
+        # Find the maximum name length for alignment
+        max_instr_len = max((len(format_instruction_name(name)) for name in instructions.keys()), default=0)
+        max_csr_len = max((len(format_csr_name(csrs[addr])) for addr in csrs.keys()), default=0)
+        max_len = max(max_instr_len, max_csr_len)
+        
+        # Write instruction parameters
+        for name in sorted(instructions.keys()):
+            encoding = instructions[name]
+            sv_name = format_instruction_name(name)
+            # Pad the name for alignment
+            padded_name = sv_name.ljust(max_len)
+            
+            # Get the match pattern
+            if isinstance(encoding, dict) and "match" in encoding:
+                match = encoding["match"]
+            else:
+                # If no match field, use all wildcards
+                match = "-" * 32
+            
+            # Check if this is a compressed instruction
+            is_compressed = name.startswith("c.")
+            sv_bits = match_to_sverilog_bits(match, is_compressed)
+            f.write(f"  localparam [31:0] {padded_name} = {sv_bits};\n")
+        
+        # Write CSR parameters
+        # CSRs are returned as {address: name} by load_csrs
+        for addr in sorted(csrs.keys()):
+            csr_name = csrs[addr]
+            sv_name = format_csr_name(csr_name)
+            # Pad the name for alignment
+            padded_name = sv_name.ljust(max_len)
+            
+            # Format CSR address as 12-bit hex
+            f.write(f"  localparam logic [11:0] {padded_name} = 12'h{addr:03x};\n")
+        
+        # Write footer
+        f.write("\nendpackage\n")
+
+
+def parse_args():
+    parser = argparse.ArgumentParser(
+        description="Generate SystemVerilog package from RISC-V instruction definitions"
+    )
+    parser.add_argument(
+        "--inst-dir",
+        default="../../../gen/resolved_spec/_/inst/",
+        help="Directory containing instruction YAML files",
+    )
+    parser.add_argument(
+        "--csr-dir",
+        default="../../../gen/resolved_spec/_/csr/",
+        help="Directory containing CSR YAML files",
+    )
+    parser.add_argument(
+        "--output", 
+        default="inst.sverilog", 
+        help="Output SystemVerilog file name"
+    )
+    parser.add_argument(
+        "--extensions",
+        default="A,D,F,I,M,Q,Zba,Zbb,Zbs,S,System,V,Zicsr,Smpmp,Sm,H,U,Zicntr,Zihpm,Smhpm",
+        help="Comma-separated list of enabled extensions. Default includes standard extensions.",
+    )
+    parser.add_argument(
+        "--arch",
+        default="RV64",
+        choices=["RV32", "RV64", "BOTH"],
+        help="Target architecture (RV32, RV64, or BOTH). Default is RV64.",
+    )
+    parser.add_argument(
+        "--verbose", "-v", action="store_true", help="Enable verbose logging"
+    )
+    parser.add_argument(
+        "--include-all",
+        action="store_true",
+        help="Include all instructions and CSRs regardless of extensions",
+    )
+    return parser.parse_args()
+
+
+def main():
+    args = parse_args()
+
+    # Set up logging
+    log_level = logging.DEBUG if args.verbose else logging.INFO
+    logging.basicConfig(level=log_level, format="%(levelname)s:: %(message)s")
+
+    # Parse extensions
+    if args.include_all:
+        enabled_extensions = []
+        logging.info("Including all instructions and CSRs (ignoring extension filter)")
+    else:
+        enabled_extensions = [ext.strip() for ext in args.extensions.split(",")]
+        logging.info(f"Enabled extensions: {', '.join(enabled_extensions)}")
+
+    logging.info(f"Target architecture: {args.arch}")
+
+    # Load instructions
+    instructions = load_instructions(
+        args.inst_dir, enabled_extensions, args.include_all, args.arch
+    )
+    logging.info(f"Loaded {len(instructions)} instructions")
+
+    # Load CSRs
+    csrs = load_csrs(args.csr_dir, enabled_extensions, args.include_all, args.arch)
+    logging.info(f"Loaded {len(csrs)} CSRs")
+
+    # Generate the SystemVerilog file
+    generate_sverilog(instructions, csrs, args.output)
+    logging.info(
+        f"Generated {args.output} with {len(instructions)} instructions and {len(csrs)} CSRs"
+    )
+
+
+if __name__ == "__main__":
+    main()

backends/generators/tasks.rake

@@ -6,6 +6,7 @@ require 'tempfile'
 
 directory "#{$root}/gen/go"
 directory "#{$root}/gen/c_header"
+directory "#{$root}/gen/sverilog"
 
 namespace :gen do
   desc <<~DESC
@@ -87,4 +88,28 @@ namespace :gen do
       resolved_codes_file.unlink
     end
   end
+
+  desc <<~DESC
+    Generate SystemVerilog package from RISC-V instruction and CSR definitions
+
+    Options:
+     * CONFIG - Configuration name (defaults to "_")
+     * OUTPUT_DIR - Output directory for generated SystemVerilog code (defaults to "#{$root}/gen/sverilog")
+  DESC
+  task sverilog: "#{$root}/gen/sverilog" do
+    config_name = ENV["CONFIG"] || "_"
+    output_dir = ENV["OUTPUT_DIR"] || "#{$root}/gen/sverilog/"
+
+    # Ensure the output directory exists
+    FileUtils.mkdir_p output_dir
+
+    # Get the arch paths based on the config
+    resolver = Udb::Resolver.new
+    cfg_arch = resolver.cfg_arch_for(config_name)
+    inst_dir = cfg_arch.path / "inst"
+    csr_dir = cfg_arch.path / "csr"
+
+    # Run the SystemVerilog generator script using the same Python environment
+    sh "#{$root}/.home/.venv/bin/python3 #{$root}/backends/generators/sverilog/sverilog_generator.py --inst-dir=#{inst_dir} --csr-dir=#{csr_dir} --output=#{output_dir}inst.sverilog"
+  end
 end