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fixed indentations and minor issues
1 parent bf9ad02 commit d5de362

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3 files changed

+180
-210
lines changed

3 files changed

+180
-210
lines changed

spec/std/isa/csr/scountinhibit.layout

Lines changed: 17 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,7 @@ long_name: Supervisor Counter-Inhibit Register
1010
address: 0x120
1111
writable: true
1212
priv_mode: S
13-
length: SXLEN
13+
length: 32
1414
description: |
1515
For counters delegated to S-mode, the associated `mcountinhibit` bits can be accessed
1616
via `scountinhibit`. For counters not delegated to S-mode, the associated bits in
@@ -32,16 +32,15 @@ fields:
3232
sw_write(csr_value): |
3333
if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b0) {
3434
if (mode() == PrivilegeMode::M) {
35-
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
35+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
3636
}
3737
} else if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b1) {
3838
if ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) {
39-
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
39+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
4040
}
41-
} else {
42-
CSR[mcountinhibit].CY = csr_value.CY;
43-
return csr_value.CY;
4441
}
42+
CSR[mcountinhibit].CY = csr_value.CY;
43+
return csr_value.CY;
4544
IR:
4645
location: 2
4746
description: |
@@ -54,16 +53,15 @@ fields:
5453
sw_write(csr_value): |
5554
if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b0) {
5655
if (mode() == PrivilegeMode::M) {
57-
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
56+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
5857
}
5958
} else if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b1) {
6059
if ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) {
61-
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
60+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
6261
}
63-
} else {
64-
CSR[mcountinhibit].IR = csr_value.IR;
65-
return csr_value.IR;
6662
}
63+
CSR[mcountinhibit].IR = csr_value.IR;
64+
return csr_value.IR;
6765
<%- (3..31).each do |hpm_num| -%>
6866
HPM<%= hpm_num %>:
6967
location: <%= hpm_num %>
@@ -93,25 +91,25 @@ fields:
9391
sw_write(csr_value): |
9492
if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b0) {
9593
if (mode() == PrivilegeMode::M) {
96-
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
94+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
9795
}
9896
} else if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b1) {
9997
if ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) {
100-
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
98+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
10199
}
102-
} else {
103-
CSR[mcountinhibit].HPM<%= hpm_num %> = csr_value.HPM<%= hpm_num %>;
104-
return csr_value.HPM<%= hpm_num %>;
105100
}
101+
CSR[mcountinhibit].HPM<%= hpm_num %> = csr_value.HPM<%= hpm_num %>;
102+
return csr_value.HPM<%= hpm_num %>;
106103
<%- end -%>
107104

108105
sw_read(): |
109106
if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b0) {
110107
if (mode() == PrivilegeMode::M) {
111-
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
108+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
112109
}
113110
} else if (implemented_csr?(CsrName::menvcfg) && CSR[menvcfg].CDE == 1'b1) {
114111
if ((mode() == PrivilegeMode::VS) || (mode() == PrivilegeMode::VU)) {
115-
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
112+
raise(ExceptionCode::VirtualInstruction, mode(), $encoding);
116113
}
117-
} return ($bits(CSR[mcountinhibit]) & ($bits(CSR[scounteren]) & ~32'd2)) ;
114+
}
115+
return ($bits(CSR[mcountinhibit]) & ($bits(CSR[scounteren]) & ~32'd2)) ;

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