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- Due by April 24, 2026
- Due by March 27, 2026
- Due by February 27, 2026
- Due by January 30, 2026
- Due by November 28, 2025
- Overdue by 2 day(s)•Due by October 31, 2025•0/1 issues closed
- Prove that UDB -> riscv-opcodes format -> output is identical to riscv-opcodes output - Implement UDB -> output, prove it is identical - Deprecate riscv-opcodes - Migration documentation
No due date- Name - Synopsis - Extensions (with “option” type) - Instructions added - CSRs added - Versions - Ratification date
Overdue by 1 month(s)•Due by October 1, 2025- Name - Synopsis - Instructions added - CSRs added - Versions - Ratification date
Overdue by 1 month(s)•Due by October 1, 2025Add data that depends on IDL and/or Sail: - Field list - Reset value - Write behavior - Type (RO/RW/…) - Read behavior
No due dateList of every CSR, with the following information: - Name/mnemonic - Long name (“Signed Multiply”) - (Virtual/Indirect) Address - Synopsis - Field list - Location - Defining extension(s)
Overdue by 1 month(s)•Due by October 1, 2025•9/18 issues closedAdd the following data to the instruction appendix: - Assembly format - Encoding (w/ names for opcodes) - Decode variable metadata - Instruction format (I/R/…) - Pseudo instructions
Overdue by 1 month(s)•Due by October 1, 2025Phase 1 shall include: - Integration of riscv-isa-manual repo into UDB - Generated ISA Manual PDF with complete instruction appendix - Generated ISA Manual HTML using Antora with complete instruction appendix In the appendix, we will include, for each instruction: - Mnemonic / name - Long name (e.g, "Signed Multiply") - Synopsis - Encoding, without opcode field names - Decode variables (name and position, no 'type') - Defining extension(s) - Defining profile(s)
Overdue by 5 month(s)•Due by May 12, 2025•3/5 issues closed