From 4674bdf57c89a973a898bf6a391bc6734cde1e3e Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Thu, 27 Mar 2025 08:43:04 -0700 Subject: [PATCH 1/8] Add Smctr/Ssctr YAML and properly attribute SCTRCLR to them --- arch/ext/Smctr.yaml | 51 +++++++++++++++++++++++++++++++++ arch/ext/Ssctr.yaml | 13 +++++++++ arch/inst/Smdbltrp/sctrclr.yaml | 3 +- 3 files changed, 66 insertions(+), 1 deletion(-) create mode 100644 arch/ext/Smctr.yaml create mode 100644 arch/ext/Ssctr.yaml diff --git a/arch/ext/Smctr.yaml b/arch/ext/Smctr.yaml new file mode 100644 index 0000000000..e0aa14cd96 --- /dev/null +++ b/arch/ext/Smctr.yaml @@ -0,0 +1,51 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smctr +long_name: Control Transfer Records +description: | + A method for recording control flow transfer history is valuable not only for performance + profiling but also for debugging. + Control flow transfers refer to jump instructions (including function calls and returns), taken + branch instructions, traps, and trap returns. + Profiling tools, such as Linux perf, collect control transfer history when sampling software + execution, thereby enabling tools, like AutoFDO, to identify hot paths for optimization. + + Control flow trace capabilities offer very deep transfer history, but the volume of data produced + can result in significant performance overheads due to memory bandwidth consumption, buffer + management, and decoder overhead. + The Control Transfer Records (CTR) extension provides a method to record a limited history in + register-accessible internal chip storage, with the intent of dramatically reducing the + performance overhead and complexity of collecting transfer history. + + CTR defines a circular (FIFO) buffer. Each buffer entry holds a record for a single recorded + control flow transfer. + The number of records that can be held in the buffer depends upon both the implementation (the + maximum supported depth) and the CTR configuration (the software selected depth). + + Only qualified transfers are recorded. + Qualified transfers are those that meet the filtering criteria, which include the privilege mode + and the transfer type. + + Recorded transfers are inserted at the write pointer, which is then incremented, while older + recorded transfers may be overwritten once the buffer is full. + Or the user can enable RAS (Return Address Stack) emulation mode, where only function calls are + recorded, and function returns pop the last call record. + The source PC, target PC, and some optional metadata (transfer type, elapsed cycles) are stored + for each recorded transfer. + + The CTR buffer is accessible through an indirect CSR interface, such that software can specify + which logical entry in the buffer it wishes to read or write. + Logical entry 0 always corresponds to the youngest recorded transfer, followed by entry 1 as the + next youngest, and so on. +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: 2024-11 + implies: + - if: S + then: + name: Ssctr + version: "1.0.0" diff --git a/arch/ext/Ssctr.yaml b/arch/ext/Ssctr.yaml new file mode 100644 index 0000000000..0f02bc6b38 --- /dev/null +++ b/arch/ext/Ssctr.yaml @@ -0,0 +1,13 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Ssctr +long_name: Control Transfer Records +description: | + The supervisor view of `Smctr`. +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: 2024-11 diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index b8f99a943f..bdfaa5e02e 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -6,7 +6,8 @@ name: sctrclr long_name: No synopsis available. description: | No description available. -definedBy: Smdbltrp +definedBy: + anyOf: [Smctr, Ssctr] assembly: sctrclr encoding: match: "00010000010000000000000001110011" From dfe449469a7ccff1aec842c918777f59990f77ca Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Thu, 27 Mar 2025 10:59:40 -0700 Subject: [PATCH 2/8] Make Smctr/Ssctr require S and Smcsrind/Sscsrind --- arch/ext/Smctr.yaml | 12 ++++++++---- arch/ext/Ssctr.yaml | 6 ++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/arch/ext/Smctr.yaml b/arch/ext/Smctr.yaml index e0aa14cd96..370c1e278d 100644 --- a/arch/ext/Smctr.yaml +++ b/arch/ext/Smctr.yaml @@ -45,7 +45,11 @@ versions: state: ratified ratification_date: 2024-11 implies: - - if: S - then: - name: Ssctr - version: "1.0.0" + name: Ssctr + version: "1.0.0" + requires: + allOf: + - name: S + version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified + - name: Smcsrind + version: ~> 1.0 diff --git a/arch/ext/Ssctr.yaml b/arch/ext/Ssctr.yaml index 0f02bc6b38..f2719b62fc 100644 --- a/arch/ext/Ssctr.yaml +++ b/arch/ext/Ssctr.yaml @@ -11,3 +11,9 @@ versions: - version: "1.0.0" state: ratified ratification_date: 2024-11 + requires: + allOf: + - name: S + version: ~> 1.13 # The latest ratified version of S when Sscntr was ratified + - name: Sscsrind + version: ~> 1.0 From 8c95734985f524f84d144c567e7218d4b07ce7bd Mon Sep 17 00:00:00 2001 From: Derek Hower Date: Thu, 3 Apr 2025 05:39:32 -0700 Subject: [PATCH 3/8] data(inst): add long_name and description for sctclr Co-authored-by: David Brash --- arch/inst/Smdbltrp/sctrclr.yaml | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index bdfaa5e02e..e8472bd141 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -3,9 +3,27 @@ $schema: inst_schema.json# kind: instruction name: sctrclr -long_name: No synopsis available. +long_name: Supervisor Control Transfer Record (CTR) clear description: | - No description available. + When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: + + * Zeroes all CTR Entry Registers, for all DEPTH values + * Reset to Zero the optional CTR cycle counter where implemented + ** `ctrdata.CC` and `ctrdata.CC` bit fields. + + Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next + qualified control transfer, will return the value 0. + Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. + + SCTRCLR execution causes an `IllegalInstruction` exception if: + + * `Smctr` is not implemented + * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 + * The instruction is executed in U-mode + + SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: + * The instruction is executed in VS-mode and `hstateen0.CTR`=0 + * The instruction is executed in VU-mode definedBy: anyOf: [Smctr, Ssctr] assembly: sctrclr From c133198ed2718fdfb2a3cdf0d1358688d05203cf Mon Sep 17 00:00:00 2001 From: Derek Hower <134728312+dhower-qc@users.noreply.github.com> Date: Thu, 17 Apr 2025 14:13:01 -0400 Subject: [PATCH 4/8] refactor(data): convert SCTRCLR description to array form Signed-off-by: Derek Hower <134728312+dhower-qc@users.noreply.github.com> --- arch/inst/Smdbltrp/sctrclr.yaml | 49 +++++++++++++++++++++------------ 1 file changed, 31 insertions(+), 18 deletions(-) diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index e8472bd141..44eac28d6d 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -4,26 +4,39 @@ $schema: inst_schema.json# kind: instruction name: sctrclr long_name: Supervisor Control Transfer Record (CTR) clear -description: | - When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: +description: + - id: inst-sctrclr-operation + normative: false + text: | + When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: - * Zeroes all CTR Entry Registers, for all DEPTH values - * Reset to Zero the optional CTR cycle counter where implemented - ** `ctrdata.CC` and `ctrdata.CC` bit fields. + * Zeroes all CTR Entry Registers, for all DEPTH values + * Reset to Zero the optional CTR cycle counter where implemented + ** `ctrdata.CC` and `ctrdata.CC` bit fields. + - id: inst-sctrclr-csr-effect + normative: true + text: | + Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next + qualified control transfer, will return the value 0. + - id: inst-sctrclr-after + normative: true + text: | + Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. + - id: inst-sctrclr-illegal + normative: false + text: | + SCTRCLR execution causes an `IllegalInstruction` exception if: - Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next - qualified control transfer, will return the value 0. - Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. - - SCTRCLR execution causes an `IllegalInstruction` exception if: - - * `Smctr` is not implemented - * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 - * The instruction is executed in U-mode - - SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: - * The instruction is executed in VS-mode and `hstateen0.CTR`=0 - * The instruction is executed in VU-mode + * `Smctr` is not implemented + * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 + * The instruction is executed in U-mode + - id: inst-sctrclr-virtual + normative: false + text: | + SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: + + * The instruction is executed in VS-mode and `hstateen0.CTR`=0 + * The instruction is executed in VU-mode definedBy: anyOf: [Smctr, Ssctr] assembly: sctrclr From 74e623710f670553669e86c7733164bc7cf7ebd3 Mon Sep 17 00:00:00 2001 From: Derek Hower <134728312+dhower-qc@users.noreply.github.com> Date: Tue, 29 Apr 2025 15:01:46 -0400 Subject: [PATCH 5/8] Update sctrclr.yaml Signed-off-by: Derek Hower <134728312+dhower-qc@users.noreply.github.com> --- arch/inst/Smdbltrp/sctrclr.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index 44eac28d6d..b29f067e41 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -12,7 +12,7 @@ description: * Zeroes all CTR Entry Registers, for all DEPTH values * Reset to Zero the optional CTR cycle counter where implemented - ** `ctrdata.CC` and `ctrdata.CC` bit fields. + ** `ctrdata.CC` and `ctrdata.CCV` bit fields. - id: inst-sctrclr-csr-effect normative: true text: | From f5fad4221a85f6d6bcfa9448508c7b2c941b68f5 Mon Sep 17 00:00:00 2001 From: zain2050 Date: Fri, 3 Oct 2025 12:49:56 +0000 Subject: [PATCH 6/8] fix(idl): add config params to Smctr --- arch/ext/Smctr.yaml | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/ext/Smctr.yaml b/arch/ext/Smctr.yaml index 370c1e278d..d10b543a8f 100644 --- a/arch/ext/Smctr.yaml +++ b/arch/ext/Smctr.yaml @@ -39,6 +39,25 @@ description: | which logical entry in the buffer it wishes to read or write. Logical entry 0 always corresponds to the youngest recorded transfer, followed by entry 1 as the next youngest, and so on. +params: + CTR_CYCLE_COUNTER: + description: | + The elapsed cycle counter includes a count of CPU cycles elapsed since the prior CTR record. + It is represented by the CC field, which has a 12-bit mantissa component + (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE). + It increments at the same rate as the mcycle counter. + The CtrCycleCounter is reset on writes to xctrctl , and on execution of SCTRCLR, to ensure that any + accumulated cycle counts do not persist across a context switch. + schema: + type: integer + CCV: + description: | + The CC value is valid only when the Cycle Count Valid (CCV) bit is set. The next record will + have CCV=0 after a write to xctrctl , or execution of SCTRCLR, since CtrCycleCounter is reset. CCV + should additionally be cleared after any other implementation-specific scenarios where active cycles + might not be counted in CtrCycleCounter. + schema: + type: boolean type: privileged versions: - version: "1.0.0" From dcc0552b7f6ad7810230c0a20370831bbf9121eb Mon Sep 17 00:00:00 2001 From: zain2050 Date: Fri, 3 Oct 2025 13:09:09 +0000 Subject: [PATCH 7/8] fix(idl): add IDL for Sctrclr --- arch/inst/Smdbltrp/sctrclr.yaml | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index b29f067e41..e796658e93 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -4,7 +4,7 @@ $schema: inst_schema.json# kind: instruction name: sctrclr long_name: Supervisor Control Transfer Record (CTR) clear -description: +description: | - id: inst-sctrclr-operation normative: false text: | @@ -34,7 +34,7 @@ description: normative: false text: | SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: - + * The instruction is executed in VS-mode and `hstateen0.CTR`=0 * The instruction is executed in VU-mode definedBy: @@ -50,3 +50,31 @@ access: vu: always data_independent_timing: false operation(): | + if (implemented?(ExtensionName::Smstateen)) { + if (CSR[mstateen0].CTR == 1'b0) { + if (mode() != PrivilegeMode::M) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + } + else if (implemented?(ExtensionName::H)) { + if (CSR[hstateen0].CTR == 1'b0 && mode() == PrivilegeMode::VS) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + } + } + if (mode() == PrivilegeMode::U) { + raise (ExceptionCode::IllegalInstruction, mode(), $encoding); + } + else if (implemented?(ExtensionName::H) && mode() == PrivilegeMode::VU) { + raise (ExceptionCode::VirtualInstruction, mode(), $encoding); + } + else { + for (U32 i = 0; i < (16 << CSR[sctrdepth].DEPTH); i++) { + CSR[siselect] = (0x200 + i); + CSR[sireg1] = 0; + CSR[sireg2] = 0; + CSR[sireg3] = 0; + } + CTRCycleCounter = 16'b0; + CycleCountValid = 1'b0; + } From 23e433dacbf05c05e90d56c444d6d3f44fcbd78c Mon Sep 17 00:00:00 2001 From: zain2050 Date: Sat, 4 Oct 2025 16:28:49 +0000 Subject: [PATCH 8/8] fix: modified params --- arch/ext/Smctr.yaml | 22 +++++++------- arch/inst/Smdbltrp/sctrclr.yaml | 51 +++++++++++++-------------------- 2 files changed, 31 insertions(+), 42 deletions(-) diff --git a/arch/ext/Smctr.yaml b/arch/ext/Smctr.yaml index d10b543a8f..26be154fa2 100644 --- a/arch/ext/Smctr.yaml +++ b/arch/ext/Smctr.yaml @@ -42,20 +42,20 @@ description: | params: CTR_CYCLE_COUNTER: description: | - The elapsed cycle counter includes a count of CPU cycles elapsed since the prior CTR record. - It is represented by the CC field, which has a 12-bit mantissa component - (Cycle Count Mantissa, or CCM) and a 4-bit exponent component (Cycle Count Exponent, or CCE). - It increments at the same rate as the mcycle counter. - The CtrCycleCounter is reset on writes to xctrctl , and on execution of SCTRCLR, to ensure that any - accumulated cycle counts do not persist across a context switch. + An internal counter used to count CPU cycles while CTR is active, where active implies that the + current privilege mode is enabled for recording and CTR is not frozen. This counter is only for + implementations that support cycle counting. It increments at the same rate as the mcycle counter. + This counter is used to populate the CC field of ctrdata when a qualified control transfer occurs. + It resets on writes to xctrctl and on execution of SCTRCLR. schema: type: integer - CCV: + CCV_HW: description: | - The CC value is valid only when the Cycle Count Valid (CCV) bit is set. The next record will - have CCV=0 after a write to xctrctl , or execution of SCTRCLR, since CtrCycleCounter is reset. CCV - should additionally be cleared after any other implementation-specific scenarios where active cycles - might not be counted in CtrCycleCounter. + An internal hardware flag, which is stored in ctrdata.CCV of the next record in case of a qualified + control transfer. + It is cleared out after a write to xctrctl or execution of SCTRCLR, since CTR_CYCLE_COUNTER is reset. + This flag should additionally be cleared after any other implementation-specific scenarios where + active cycles might not be counted in CTR_CYCLE_COUNTER. schema: type: boolean type: privileged diff --git a/arch/inst/Smdbltrp/sctrclr.yaml b/arch/inst/Smdbltrp/sctrclr.yaml index e796658e93..89020ea476 100644 --- a/arch/inst/Smdbltrp/sctrclr.yaml +++ b/arch/inst/Smdbltrp/sctrclr.yaml @@ -5,38 +5,27 @@ kind: instruction name: sctrclr long_name: Supervisor Control Transfer Record (CTR) clear description: | - - id: inst-sctrclr-operation - normative: false - text: | - When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: + When `mstateen0.CTR`=1, the SCTRCLR instruction performs the following operations: - * Zeroes all CTR Entry Registers, for all DEPTH values - * Reset to Zero the optional CTR cycle counter where implemented - ** `ctrdata.CC` and `ctrdata.CCV` bit fields. - - id: inst-sctrclr-csr-effect - normative: true - text: | - Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next - qualified control transfer, will return the value 0. - - id: inst-sctrclr-after - normative: true - text: | - Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. - - id: inst-sctrclr-illegal - normative: false - text: | - SCTRCLR execution causes an `IllegalInstruction` exception if: + * Zeroes all CTR Entry Registers, for all DEPTH values + * Reset to Zero the optional CTR cycle counter where implemented + ** `ctrdata.CC` and `ctrdata.CCV` bit fields. - * `Smctr` is not implemented - * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 - * The instruction is executed in U-mode - - id: inst-sctrclr-virtual - normative: false - text: | - SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: + Any read of `ctrsource`, `ctrtarget`, or `ctrdata` that follows SCTRCLR, such that it precedes the next + qualified control transfer, will return the value 0. - * The instruction is executed in VS-mode and `hstateen0.CTR`=0 - * The instruction is executed in VU-mode + Further, the first recorded transfer following SCTRCLR will have `ctrdata.CCV`=0. + + SCTRCLR execution causes an `IllegalInstruction` exception if: + + * `Smctr` is not implemented + * The instruction is executed in S/VS/VU-mode and `Ssctr` is not implemented, or `mstateen0.CTR`=0 + * The instruction is executed in U-mode + + SCTRCLR execution causes a `VirtualInstruciton` exception if `mstateen0.CTR`=1 and: + + * The instruction is executed in VS-mode and `hstateen0.CTR`=0 + * The instruction is executed in VU-mode definedBy: anyOf: [Smctr, Ssctr] assembly: sctrclr @@ -75,6 +64,6 @@ operation(): | CSR[sireg2] = 0; CSR[sireg3] = 0; } - CTRCycleCounter = 16'b0; - CycleCountValid = 1'b0; + CTR_CYCLE_COUNTER = 16'b0; + CCV_HW = 1'b0; }