From 8985ce180126919297cca34dfd31e0c3be33d2a9 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Fri, 17 Oct 2025 21:40:47 -0700 Subject: [PATCH 1/3] fix(data): use hints for Zicbop instructions - Replace `pseudoinstructions` inline in `ori.yaml` with hint references - Fix IDL implementation for prefetch instructions to use the offset+reg value --- .../all_instructions.golden.adoc | 122 +++++++++++++++++- spec/std/isa/inst/I/ori.yaml | 28 +--- spec/std/isa/inst/Zicbop/prefetch.i.yaml | 32 +++++ spec/std/isa/inst/Zicbop/prefetch.r.yaml | 32 +++++ spec/std/isa/inst/Zicbop/prefetch.w.yaml | 32 +++++ 5 files changed, 221 insertions(+), 25 deletions(-) create mode 100644 spec/std/isa/inst/Zicbop/prefetch.i.yaml create mode 100644 spec/std/isa/inst/Zicbop/prefetch.r.yaml create mode 100644 spec/std/isa/inst/Zicbop/prefetch.w.yaml diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc index 46a78c77d1..dfb86f7250 100644 --- a/backends/instructions_appendix/all_instructions.golden.adoc +++ b/backends/instructions_appendix/all_instructions.golden.adoc @@ -1,6 +1,6 @@ = Instruction Appendix :doctype: book -:wavedrom: /workspace/riscv-unified-db/node_modules/.bin/wavedrom-cli +:wavedrom: /workspaces/riscv-unified-db/node_modules/.bin/wavedrom-cli // Now the document header is complete and the wavedrom attribute is active. @@ -16539,6 +16539,126 @@ Included in:: |=== +[#udb:doc:inst:prefetch_i] +== prefetch.i + +Synopsis:: +Cache block prefetch for instruction fetch + +Assembly:: +prefetch.i imm(xs1) + +Encoding:: +[wavedrom, ,svg,subs='attributes',width="100%"] +.... +{"reg":[{"bits":15,"name": 0x6013,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": 0x0,"type":2},{"bits":7,"name": "imm","type":4}]} +.... + +Description:: +A prefetch.i instruction indicates to hardware that the cache block whose +effective address is the sum of the base address specified in rs1 and the +sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, +is likely to be accessed by an instruction fetch in the near future. + + +Decode Variables:: +[width="100%", cols="1,2", options="header"] +|=== +|Variable Name |Location +|imm |$encoding[31:25] +|xs1 |$encoding[19:15] +|=== + +Included in:: +[options="autowrap,autowidth"] +|=== +| Extension | Version + +| *Zicbop* | ~> 1.0.0 + +|=== + + +[#udb:doc:inst:prefetch_r] +== prefetch.r + +Synopsis:: +Cache block prefetch for data read + +Assembly:: +prefetch.r imm(xs1) + +Encoding:: +[wavedrom, ,svg,subs='attributes',width="100%"] +.... +{"reg":[{"bits":15,"name": 0x6013,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": 0x1,"type":2},{"bits":7,"name": "imm","type":4}]} +.... + +Description:: +A prefetch.r instruction indicates to hardware that the cache block whose +effective address is the sum of the base address specified in rs1 and the +sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, +is likely to be accessed by a data read (i.e. load) in the near future. + + +Decode Variables:: +[width="100%", cols="1,2", options="header"] +|=== +|Variable Name |Location +|imm |$encoding[31:25] +|xs1 |$encoding[19:15] +|=== + +Included in:: +[options="autowrap,autowidth"] +|=== +| Extension | Version + +| *Zicbop* | ~> 1.0.0 + +|=== + + +[#udb:doc:inst:prefetch_w] +== prefetch.w + +Synopsis:: +Cache block prefetch for data write + +Assembly:: +prefetch.w imm(xs1) + +Encoding:: +[wavedrom, ,svg,subs='attributes',width="100%"] +.... +{"reg":[{"bits":15,"name": 0x6013,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": 0x3,"type":2},{"bits":7,"name": "imm","type":4}]} +.... + +Description:: +A prefetch.w instruction indicates to hardware that the cache block whose +effective address is the sum of the base address specified in rs1 and the +sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, +is likely to be accessed by a data write (i.e. store) in the near future. + + +Decode Variables:: +[width="100%", cols="1,2", options="header"] +|=== +|Variable Name |Location +|imm |$encoding[31:25] +|xs1 |$encoding[19:15] +|=== + +Included in:: +[options="autowrap,autowidth"] +|=== +| Extension | Version + +| *Zicbop* | ~> 1.0.0 + +|=== + + [#udb:doc:inst:rem] == rem diff --git a/spec/std/isa/inst/I/ori.yaml b/spec/std/isa/inst/I/ori.yaml index 46ff34e8b3..85fb173f36 100644 --- a/spec/std/isa/inst/I/ori.yaml +++ b/spec/std/isa/inst/I/ori.yaml @@ -25,32 +25,12 @@ access: vs: always vu: always data_independent_timing: true +hints: + - { $ref: inst/Zicbop/prefetch.r.yaml# } + - { $ref: inst/Zicbop/prefetch.w.yaml# } + - { $ref: inst/Zicbop/prefetch.i.yaml# } operation(): | - if (implemented?(ExtensionName::Zicbop)) { - if (xd == 0) { - if (imm[4:0] == 0) { - # prefetch.i instruction - Bits<12> offset = {imm[11:5], xd}; - prefetch_instruction(offset); - } else if (imm[4:0] == 1) { - # prefetch.r instruction - Bits<12> offset = {imm[11:5], xd}; - prefetch_read(offset); - } else if (imm[4:0] == 3) { - # prefetch.r instruction - Bits<12> offset = {imm[11:5], xd}; - prefetch_write(offset); - } - } - } X[xd] = X[xs1] | $signed(imm); -pseudoinstructions: - - when: (xd == 0) && (imm[4:0] == 0) - to: prefetch.i offset - - when: (xd == 0) && (imm[4:0] == 1) - to: prefetch.r offset - - when: (xd == 0) && (imm[4:0] == 3) - to: prefetch.w offset # SPDX-SnippetBegin # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model diff --git a/spec/std/isa/inst/Zicbop/prefetch.i.yaml b/spec/std/isa/inst/Zicbop/prefetch.i.yaml new file mode 100644 index 0000000000..8abecddf4c --- /dev/null +++ b/spec/std/isa/inst/Zicbop/prefetch.i.yaml @@ -0,0 +1,32 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: prefetch.i +long_name: Cache block prefetch for instruction fetch +description: | + A prefetch.i instruction indicates to hardware that the cache block whose + effective address is the sum of the base address specified in rs1 and the + sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, + is likely to be accessed by an instruction fetch in the near future. +definedBy: Zicbop +assembly: imm(xs1) +encoding: + match: -------00000-----110000000010011 + variables: + - name: imm + location: 31-25 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg address = X[xs1] + $signed(imm << 5); + prefetch_instruction(address); diff --git a/spec/std/isa/inst/Zicbop/prefetch.r.yaml b/spec/std/isa/inst/Zicbop/prefetch.r.yaml new file mode 100644 index 0000000000..80b28e6946 --- /dev/null +++ b/spec/std/isa/inst/Zicbop/prefetch.r.yaml @@ -0,0 +1,32 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: prefetch.r +long_name: Cache block prefetch for data read +description: | + A prefetch.r instruction indicates to hardware that the cache block whose + effective address is the sum of the base address specified in rs1 and the + sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, + is likely to be accessed by a data read (i.e. load) in the near future. +definedBy: Zicbop +assembly: imm(xs1) +encoding: + match: -------00001-----110000000010011 + variables: + - name: imm + location: 31-25 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg address = X[xs1] + $signed(imm << 5); + prefetch_read(address); diff --git a/spec/std/isa/inst/Zicbop/prefetch.w.yaml b/spec/std/isa/inst/Zicbop/prefetch.w.yaml new file mode 100644 index 0000000000..44cdaa6937 --- /dev/null +++ b/spec/std/isa/inst/Zicbop/prefetch.w.yaml @@ -0,0 +1,32 @@ +# Copyright (c) Jordan Carlin +# SPDX-License-Identifier: BSD-3-Clause-Clear + +# yaml-language-server: $schema=../../../../schemas/inst_schema.json + +$schema: inst_schema.json# +kind: instruction +name: prefetch.w +long_name: Cache block prefetch for data write +description: | + A prefetch.w instruction indicates to hardware that the cache block whose + effective address is the sum of the base address specified in rs1 and the + sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, + is likely to be accessed by a data write (i.e. store) in the near future. +definedBy: Zicbop +assembly: imm(xs1) +encoding: + match: -------00011-----110000000010011 + variables: + - name: imm + location: 31-25 + - name: xs1 + location: 19-15 +access: + s: always + u: always + vs: always + vu: always +data_independent_timing: false +operation(): | + XReg address = X[xs1] + $signed(imm << 5); + prefetch_write(address); From 67a9ad8dcb89fa38bdb1c4e989e46d1325cc47de Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 27 Oct 2025 11:05:30 -0700 Subject: [PATCH 2/3] use xs1 instead of rs1 in description --- spec/std/isa/inst/Zicbop/prefetch.i.yaml | 2 +- spec/std/isa/inst/Zicbop/prefetch.r.yaml | 2 +- spec/std/isa/inst/Zicbop/prefetch.w.yaml | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/spec/std/isa/inst/Zicbop/prefetch.i.yaml b/spec/std/isa/inst/Zicbop/prefetch.i.yaml index 8abecddf4c..9bdec44468 100644 --- a/spec/std/isa/inst/Zicbop/prefetch.i.yaml +++ b/spec/std/isa/inst/Zicbop/prefetch.i.yaml @@ -9,7 +9,7 @@ name: prefetch.i long_name: Cache block prefetch for instruction fetch description: | A prefetch.i instruction indicates to hardware that the cache block whose - effective address is the sum of the base address specified in rs1 and the + effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by an instruction fetch in the near future. definedBy: Zicbop diff --git a/spec/std/isa/inst/Zicbop/prefetch.r.yaml b/spec/std/isa/inst/Zicbop/prefetch.r.yaml index 80b28e6946..450f69885e 100644 --- a/spec/std/isa/inst/Zicbop/prefetch.r.yaml +++ b/spec/std/isa/inst/Zicbop/prefetch.r.yaml @@ -9,7 +9,7 @@ name: prefetch.r long_name: Cache block prefetch for data read description: | A prefetch.r instruction indicates to hardware that the cache block whose - effective address is the sum of the base address specified in rs1 and the + effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data read (i.e. load) in the near future. definedBy: Zicbop diff --git a/spec/std/isa/inst/Zicbop/prefetch.w.yaml b/spec/std/isa/inst/Zicbop/prefetch.w.yaml index 44cdaa6937..7205ef0a63 100644 --- a/spec/std/isa/inst/Zicbop/prefetch.w.yaml +++ b/spec/std/isa/inst/Zicbop/prefetch.w.yaml @@ -9,7 +9,7 @@ name: prefetch.w long_name: Cache block prefetch for data write description: | A prefetch.w instruction indicates to hardware that the cache block whose - effective address is the sum of the base address specified in rs1 and the + effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data write (i.e. store) in the near future. definedBy: Zicbop From 4b18ad1d3fed841dea45725e741b280808153f12 Mon Sep 17 00:00:00 2001 From: Jordan Carlin Date: Mon, 27 Oct 2025 11:21:51 -0700 Subject: [PATCH 3/3] Update golden instruction appendix --- backends/instructions_appendix/all_instructions.golden.adoc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc index dfb86f7250..d2678908b2 100644 --- a/backends/instructions_appendix/all_instructions.golden.adoc +++ b/backends/instructions_appendix/all_instructions.golden.adoc @@ -16556,7 +16556,7 @@ Encoding:: Description:: A prefetch.i instruction indicates to hardware that the cache block whose -effective address is the sum of the base address specified in rs1 and the +effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by an instruction fetch in the near future. @@ -16596,7 +16596,7 @@ Encoding:: Description:: A prefetch.r instruction indicates to hardware that the cache block whose -effective address is the sum of the base address specified in rs1 and the +effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data read (i.e. load) in the near future. @@ -16636,7 +16636,7 @@ Encoding:: Description:: A prefetch.w instruction indicates to hardware that the cache block whose -effective address is the sum of the base address specified in rs1 and the +effective address is the sum of the base address specified in xs1 and the sign-extended offset encoded in imm[11:0], where imm[4:0] equals 0b00000, is likely to be accessed by a data write (i.e. store) in the near future.