Add Smaia/Ssaia (Advanced Interrupt Architecture) support

.github/actions/singularity-setup/action.yml

@@ -19,10 +19,25 @@ runs:
             .home/.gems
             node_modules
           key: ${{ hashFiles('Gemfile.lock') }}-${{ hashFiles('package-lock.json') }}
+          fail-on-cache-miss: false
       - if: ${{ steps.cache-sif.outputs.cache-hit != 'true' }}
         name: Build container
         run: ./bin/build_container
         shell: bash
+      - name: Set up Ruby
+        uses: ruby/setup-ruby@v1
+        with:
+          ruby-version: '3.2'
+      - name: Install Bundler
+        run: gem install bundler
+        shell: bash
+      - name: Verify gems are accessible
+        run: |
+          if ! bundle check --gemfile Gemfile > /dev/null 2>&1; then
+            echo "Bundle check failed, reinstalling gems..."
+            bundle install --gemfile Gemfile
+          fi
+        shell: bash
       - name: Setup project
         run: ./bin/setup
         shell: bash

cfgs/example_rv64_with_overlay.yaml

@@ -418,6 +418,19 @@ params:
   # corresponds to the `GEILEN` parameter in the RVI specs
   NUM_EXTERNAL_GUEST_INTERRUPTS: 4
 
+  # AIA (Advanced Interrupt Architecture) configuration parameters
+  # Required for Smaia/Ssaia extensions
+
+  # Machine Virtual Interrupts configuration
+  # Specifies which interrupt numbers (13-63) are supported as writable bits in mvien/mvip
+  MACHINE_VIRTUAL_INTERRUPTS:
+    [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
+
+  # Machine Virtual Interrupts that are always enabled (read-only-1)
+  # Must be a subset of MACHINE_VIRTUAL_INTERRUPTS
+  # Empty array means no interrupts are forced to always-enabled
+  MACHINE_VIRTUAL_INTERRUPTS_ALWAYS_ENABLED: []
+
   # Endianness of data in M-mode. Can be one of:
   #
   #  * little:  M-mode data is always little endian

spec/std/isa/csr/Smaia/mtopei.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: mtopei
+long_name: Machine Top External Interrupt
+address: 0x35C
+priv_mode: M
+length: MXLEN
+writable: true
+description: |
+  Provides information about the highest-priority pending-and-enabled external interrupt
+  for machine level, with claim-and-clear semantics on write.
+definedBy: Smaia
+fields:
+  IID:
+    location: 26-16
+    long_name: Interrupt Identity
+    description: |
+      Identity of the highest-priority pending-and-enabled external interrupt.
+
+      When written with a non-zero value, clears the corresponding IMSIC interrupt.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+    sw_write(csr_value): |
+      if (csr_value.IID != 0) {
+        if (implemented?(ExtensionName::Smaia)) {
+          clear_imsic_interrupt(PrivilegeMode::M, csr_value.IID);
+        }
+      }
+      return csr_value.IID;
+  IPRIO:
+    location: 7-0
+    long_name: Interrupt Priority
+    description: |
+      Priority of the highest-priority pending-and-enabled external interrupt.
+
+      Read-only field that reflects the priority of the interrupt in IID field.
+    type: RO
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia

spec/std/isa/csr/Smaia/mvien.yaml

@@ -0,0 +1,70 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: mvien
+long_name: Machine Virtual Interrupt Enable
+address: 0x308
+priv_mode: M
+length: MXLEN
+writable: true
+description: |
+  For interrupt numbers 13-63, implementations may freely choose which bits are writable.
+  Bits corresponding to unimplemented interrupt sources should be read-only zero.
+definedBy: Smaia
+fields:
+  # Fields VSSIE, VSTIE, VSEIE are defined in the RISC-V AIA specification
+  # Section 3.2.1 "Machine Virtual Interrupt Enable Register (mvien)"
+  # These correspond to virtual supervisor software, timer, and external interrupts
+  VSSIE:
+    location: 1
+    long_name: Virtual Supervisor Software Interrupt Enable
+    description: |
+      Virtual supervisor software enable.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+  VSTIE:
+    location: 5
+    long_name: Virtual Supervisor Timer Interrupt Enable
+    description: |
+      Virtual supervisor timer enable.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+  VSEIE:
+    location: 9
+    long_name: Virtual Supervisor External Interrupt Enable
+    description: |
+      Virtual supervisor external enable.
+    type: RW
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+  MACHINE_VIRTUAL_INTERRUPTS_FIELD:
+    location: 63-13
+    long_name: Machine Virtual Interrupts
+    description: |
+      Configurable virtual interrupt enable bits for interrupt numbers 13-63.
+
+      Implementations may freely choose which bits are writable based on the
+      MACHINE_VIRTUAL_INTERRUPTS parameter. Bits corresponding to unimplemented
+      interrupt sources should be read-only zero.
+
+      This is a WARL register where the writable bits are determined by the
+      MACHINE_VIRTUAL_INTERRUPTS configuration parameter.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+    sw_write(csr_value): |
+      # Only allow writes to bits that are configured as writable
+      # Bits not in MACHINE_VIRTUAL_INTERRUPTS are read-only zero
+      Bits<51> writable_mask = 0;
+      for (int i = 13; i <= 63; i++) {
+        if (MACHINE_VIRTUAL_INTERRUPTS.include?(i)) {
+          writable_mask[i-13] = 1;
+        }
+      }
+      return (csr_value & ~writable_mask) | (value & writable_mask);

spec/std/isa/csr/Smaia/mvip.yaml

@@ -0,0 +1,108 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: mvip
+long_name: Machine Virtual Interrupt Pending
+address: 0x309
+priv_mode: M
+length: MXLEN
+writable: true
+description: |
+  If a bit in mvien is read-only zero, the corresponding bit in mvip should also be read-only zero.
+  Bits corresponding to unimplemented interrupt sources should be read-only zero.
+definedBy: Smaia
+fields:
+  # Fields VSSIP, VSTIP, VSEIP are defined in the RISC-V AIA specification
+  # Section 3.2.2 "Machine Virtual Interrupt Pending Register (mvip)"
+  # These correspond to virtual supervisor software, timer, and external interrupts
+  VSSIP:
+    location: 1
+    long_name: Virtual Supervisor Software Interrupt Pending
+    description: |
+      Virtual supervisor software pending.
+
+      This bit can only be written if the corresponding VSSIE bit in mvien is writable and enabled.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+    sw_write(csr_value): |
+      # Check if corresponding mvien bit is enabled
+      Bits<MXLEN> current_mvien = CSR[mvien].sw_read();
+      if (current_mvien[1] == 1) {
+        return value;
+      } else {
+        return 0;  # Force to zero if mvien bit is disabled
+      }
+  VSTIP:
+    location: 5
+    long_name: Virtual Supervisor Timer Interrupt Pending
+    description: |
+      Virtual supervisor timer pending.
+
+      This bit can only be written if the corresponding VSTIE bit in mvien is writable and enabled.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+    sw_write(csr_value): |
+      # Check if corresponding mvien bit is enabled
+      Bits<MXLEN> current_mvien = CSR[mvien].sw_read();
+      if (current_mvien[5] == 1) {
+        return value;
+      } else {
+        return 0;  # Force to zero if mvien bit is disabled
+      }
+  VSEIP:
+    location: 9
+    long_name: Virtual Supervisor External Interrupt Pending
+    description: |
+      Virtual supervisor external pending.
+
+      This bit can only be written if the corresponding VSEIE bit in mvien is writable and enabled.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+    sw_write(csr_value): |
+      # Check if corresponding mvien bit is enabled
+      Bits<MXLEN> current_mvien = CSR[mvien].sw_read();
+      if (current_mvien[9] == 1) {
+        return value;
+      } else {
+        return 0;  # Force to zero if mvien bit is disabled
+      }
+  MACHINE_VIRTUAL_INTERRUPTS_PENDING_FIELD:
+    location: 63-13
+    long_name: Machine Virtual Interrupts Pending
+    description: |
+      Configurable virtual interrupt pending bits for interrupt numbers 13-63.
+
+      The behavior of these bits follows the corresponding mvien bits. If a bit
+      in mvien is read-only zero, the corresponding bit in mvip should also be
+      read-only zero.
+
+      This is a WARL register where the writable bits are determined by the
+      MACHINE_VIRTUAL_INTERRUPTS configuration parameter.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Smaia
+    sw_write(csr_value): |
+      # Only allow writes to bits that are also writable in mvien
+      # If a bit in mvien is read-only zero, the corresponding bit in mvip should also be read-only zero
+      Bits<51> mvien_writable_mask = 0;
+      for (int i = 13; i <= 63; i++) {
+        if (MACHINE_VIRTUAL_INTERRUPTS.include?(i)) {
+          mvien_writable_mask[i-13] = 1;
+        }
+      }
+
+      # Get current mvien value to check which bits are actually enabled
+      Bits<MXLEN> current_mvien = CSR[mvien].sw_read();
+      Bits<51> mvien_enabled_mask = current_mvien[63:13];
+
+      # Only allow writes to bits that are both writable and enabled in mvien
+      Bits<51> effective_mask = mvien_writable_mask & mvien_enabled_mask;
+
+      return (csr_value & ~mvien_writable_mask) | (value & effective_mask);

spec/std/isa/csr/Ssaia/sieh.yaml

@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: sieh
+long_name: Supervisor Interrupt Enable High
+address: 0x114
+priv_mode: S
+length: 32
+base: 32
+writable: true
+description: |
+  Upper 32 bits of sie.
+definedBy: Ssaia
+fields: {}

spec/std/isa/csr/Ssaia/siph.yaml

@@ -0,0 +1,18 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: siph
+long_name: Supervisor Interrupt Pending High
+address: 0x154
+priv_mode: S
+length: 32
+base: 32
+writable: true
+description: |
+  Upper 32 bits of sip.
+definedBy: Ssaia
+fields: {}

spec/std/isa/csr/Ssaia/stopei.yaml

@@ -0,0 +1,45 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: stopei
+long_name: Supervisor Top External Interrupt
+address: 0x15C
+priv_mode: S
+length: SXLEN
+writable: true
+description: |
+  Provides information about the highest-priority pending-and-enabled external interrupt
+  for supervisor level, with claim-and-clear semantics on write.
+definedBy: Ssaia
+fields:
+  IID:
+    location: 26-16
+    long_name: Interrupt Identity
+    description: |
+      Identity of the highest-priority pending-and-enabled external interrupt.
+
+      When written with a non-zero value, clears the corresponding IMSIC interrupt.
+    type: RW-R
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Ssaia
+    sw_write(csr_value): |
+      if (csr_value.IID != 0) {
+        if (implemented?(ExtensionName::Ssaia)) {
+          clear_imsic_interrupt(PrivilegeMode::S, csr_value.IID);
+        }
+      }
+      return csr_value.IID;
+  IPRIO:
+    location: 7-0
+    long_name: Interrupt Priority
+    description: |
+      Priority of the highest-priority pending-and-enabled external interrupt.
+
+      Read-only field that reflects the priority of the interrupt in IID field.
+    type: RO
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Ssaia

spec/std/isa/csr/Ssaia/stopi.yaml

@@ -0,0 +1,38 @@
+# Copyright (c) 2025 Kallal Mukherjee
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: "csr_schema.json#"
+kind: csr
+name: stopi
+long_name: Supervisor Top Interrupt
+address: 0xDB0
+priv_mode: S
+length: SXLEN
+writable: false
+description: |
+  Supervisor-level CSR stopi is read-only with width SXLEN. A read of stopi returns
+  information about the highest-priority pending-and-enabled interrupt for supervisor level,
+  in this format:
+  bits 27:16 IID
+  bits 7:0 IPRIO
+  All other bits of stopi are reserved and read as zeros.
+definedBy: Ssaia
+fields:
+  IID:
+    location: 27-16
+    long_name: Interrupt Identity
+    description: |
+      Identity of the highest-priority pending-and-enabled interrupt.
+    type: RO-H
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Ssaia
+  IPRIO:
+    location: 7-0
+    long_name: Interrupt Priority
+    description: |
+      Priority of the highest-priority pending-and-enabled interrupt.
+    type: RO-H
+    reset_value: UNDEFINED_LEGAL
+    definedBy: Ssaia