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1 parent 6e2acd1 commit 72085aeCopy full SHA for 72085ae
riscv/src/register/mvien.rs
@@ -89,6 +89,8 @@ set_clear_csr!(
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/// Supervisor External Interrupt Enable
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, set_sext, clear_sext, 1 << 9);
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+read_composite_csr!(super::mvienh::read().bits(), read().bits());
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+
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#[cfg(test)]
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mod tests {
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use super::*;
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