From 65df5222bcefbe67b07b56ff6631975a095caf2f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 20 Nov 2025 11:08:43 +0100 Subject: [PATCH 1/4] system(l5) update STM32L5xx HAL Drivers to v1.0.7 Included in STM32CubeL5 FW v1.6.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 145 +++++- .../Inc/stm32l5xx_hal_cortex.h | 52 +- .../Inc/stm32l5xx_hal_cryp_ex.h | 6 +- .../Inc/stm32l5xx_hal_dac.h | 13 +- .../Inc/stm32l5xx_hal_exti.h | 12 +- .../Inc/stm32l5xx_hal_fdcan.h | 4 +- .../Inc/stm32l5xx_hal_gpio.h | 6 +- .../Inc/stm32l5xx_hal_hash.h | 82 ++-- .../Inc/stm32l5xx_hal_hash_ex.h | 74 +-- .../Inc/stm32l5xx_hal_icache.h | 28 +- .../Inc/stm32l5xx_hal_lptim.h | 4 +- .../Inc/stm32l5xx_hal_mmc.h | 4 +- .../Inc/stm32l5xx_hal_nand.h | 2 +- .../Inc/stm32l5xx_hal_ospi.h | 3 +- .../Inc/stm32l5xx_hal_pcd.h | 8 +- .../Inc/stm32l5xx_hal_pcd_ex.h | 1 - .../Inc/stm32l5xx_hal_pwr.h | 2 +- .../Inc/stm32l5xx_hal_pwr_ex.h | 2 +- .../Inc/stm32l5xx_hal_rcc.h | 4 +- .../Inc/stm32l5xx_hal_rcc_ex.h | 2 +- .../Inc/stm32l5xx_hal_rng.h | 1 + .../Inc/stm32l5xx_hal_rng_ex.h | 34 +- .../Inc/stm32l5xx_hal_rtc.h | 20 +- .../Inc/stm32l5xx_hal_rtc_ex.h | 54 +- .../Inc/stm32l5xx_hal_sd.h | 4 +- .../Inc/stm32l5xx_hal_smartcard.h | 6 +- .../Inc/stm32l5xx_hal_spi.h | 46 +- .../Inc/stm32l5xx_hal_tim.h | 43 +- .../Inc/stm32l5xx_hal_uart.h | 13 +- .../Inc/stm32l5xx_hal_usart.h | 15 +- .../Inc/stm32l5xx_hal_wwdg.h | 2 +- .../Inc/stm32l5xx_ll_adc.h | 19 +- .../Inc/stm32l5xx_ll_cortex.h | 46 +- .../Inc/stm32l5xx_ll_crs.h | 19 +- .../Inc/stm32l5xx_ll_dmamux.h | 138 +++--- .../Inc/stm32l5xx_ll_fmc.h | 57 ++- .../Inc/stm32l5xx_ll_gpio.h | 28 +- .../Inc/stm32l5xx_ll_lpuart.h | 4 + .../Inc/stm32l5xx_ll_opamp.h | 30 +- .../Inc/stm32l5xx_ll_pka.h | 13 +- .../Inc/stm32l5xx_ll_rtc.h | 398 +++++++-------- .../Inc/stm32l5xx_ll_sdmmc.h | 289 ++++++++--- .../Inc/stm32l5xx_ll_spi.h | 119 +++-- .../Inc/stm32l5xx_ll_ucpd.h | 57 ++- .../Inc/stm32l5xx_ll_usart.h | 4 + .../Inc/stm32l5xx_ll_usb.h | 9 +- system/Drivers/STM32L5xx_HAL_Driver/README.md | 34 +- .../STM32L5xx_HAL_Driver/Release_Notes.html | 173 ++++++- .../STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c | 2 +- .../Src/stm32l5xx_hal_adc_ex.c | 2 +- .../Src/stm32l5xx_hal_cortex.c | 18 + .../Src/stm32l5xx_hal_crc.c | 8 +- .../Src/stm32l5xx_hal_cryp.c | 74 +-- .../Src/stm32l5xx_hal_cryp_ex.c | 6 +- .../Src/stm32l5xx_hal_dac_ex.c | 15 +- .../Src/stm32l5xx_hal_dma.c | 2 +- .../Src/stm32l5xx_hal_exti.c | 18 +- .../Src/stm32l5xx_hal_fdcan.c | 23 +- .../Src/stm32l5xx_hal_flash.c | 4 +- .../Src/stm32l5xx_hal_flash_ex.c | 6 +- .../Src/stm32l5xx_hal_gpio.c | 9 +- .../Src/stm32l5xx_hal_hash.c | 123 +++-- .../Src/stm32l5xx_hal_hash_ex.c | 79 ++- .../Src/stm32l5xx_hal_i2c.c | 63 ++- .../Src/stm32l5xx_hal_mmc.c | 22 +- .../Src/stm32l5xx_hal_mmc_ex.c | 2 - .../Src/stm32l5xx_hal_nand.c | 42 +- .../Src/stm32l5xx_hal_ospi.c | 30 +- .../Src/stm32l5xx_hal_otfdec.c | 8 +- .../Src/stm32l5xx_hal_pcd.c | 87 ++-- .../Src/stm32l5xx_hal_pcd_ex.c | 27 +- .../Src/stm32l5xx_hal_pka.c | 8 +- .../Src/stm32l5xx_hal_pwr.c | 9 +- .../Src/stm32l5xx_hal_pwr_ex.c | 2 +- .../Src/stm32l5xx_hal_rcc.c | 16 +- .../Src/stm32l5xx_hal_rcc_ex.c | 12 +- .../Src/stm32l5xx_hal_rng.c | 13 +- .../Src/stm32l5xx_hal_rng_ex.c | 19 +- .../Src/stm32l5xx_hal_rtc.c | 20 +- .../Src/stm32l5xx_hal_rtc_ex.c | 54 +- .../Src/stm32l5xx_hal_sd.c | 17 +- .../Src/stm32l5xx_hal_smbus.c | 55 +-- .../Src/stm32l5xx_hal_spi.c | 460 +++++++++--------- .../Src/stm32l5xx_hal_sram.c | 3 + .../Src/stm32l5xx_hal_tim.c | 98 +++- .../Src/stm32l5xx_hal_tim_ex.c | 12 +- .../Src/stm32l5xx_hal_timebase_tim_template.c | 5 + .../Src/stm32l5xx_hal_uart.c | 217 +++++---- .../Src/stm32l5xx_hal_uart_ex.c | 54 +- .../Src/stm32l5xx_hal_usart_ex.c | 2 +- .../Src/stm32l5xx_hal_wwdg.c | 10 +- .../Src/stm32l5xx_ll_crs.c | 4 +- .../Src/stm32l5xx_ll_fmc.c | 37 +- .../Src/stm32l5xx_ll_gpio.c | 2 +- .../Src/stm32l5xx_ll_opamp.c | 2 +- .../Src/stm32l5xx_ll_sdmmc.c | 210 +++++++- .../Src/stm32l5xx_ll_spi.c | 7 +- .../Src/stm32l5xx_ll_tim.c | 2 - .../Src/stm32l5xx_ll_usb.c | 80 ++- .../Src/stm32l5xx_ll_utils.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 101 files changed, 2518 insertions(+), 1717 deletions(-) diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index e4e114e98c..8823752c9a 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -361,7 +361,10 @@ extern "C" { #if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -472,7 +475,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -536,6 +541,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -548,6 +557,19 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -591,6 +613,15 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + #if defined(STM32H5) #define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC #define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC @@ -796,6 +827,21 @@ extern "C" { #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -850,6 +896,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -987,8 +1037,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -1239,10 +1289,10 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32H5) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM -#endif /* STM32H5 */ +#endif /* STM32H5 || STM32H7RS || STM32N6 */ #if defined(STM32WBA) #define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE @@ -1254,27 +1304,27 @@ extern "C" { #define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL #endif /* STM32WBA */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE #define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ -#if defined(STM32F7) +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 || STM32L0 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1441,7 +1491,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1807,7 +1857,7 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) ((cmd == ENABLE)? \ +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) @@ -1989,12 +2039,12 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose * @{ */ -#if defined(STM32H5) || defined(STM32WBA) +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) #define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey #define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock #define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock #define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets -#endif /* STM32H5 || STM32WBA */ +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ /** * @} @@ -2102,6 +2152,13 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + /** * @} */ @@ -2309,8 +2366,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2343,8 +2400,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2401,8 +2458,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2419,7 +2476,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2721,6 +2778,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3644,8 +3707,11 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ - defined(STM32WL) || defined(STM32C0) +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3747,8 +3813,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3892,9 +3960,7 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ - defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ - defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -4188,6 +4254,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h index 92637832f7..7ac181cd1e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cortex.h @@ -121,10 +121,10 @@ typedef struct /** @defgroup CORTEX_MPU_HFNMI_PRIVDEF_Control CORTEX MPU HFNMI and PRIVILEGED Access control * @{ */ -#define MPU_HFNMI_PRIVDEF_NONE 0U -#define MPU_HARDFAULT_NMI 2U -#define MPU_PRIVILEGED_DEFAULT 4U -#define MPU_HFNMI_PRIVDEF 6U +#define MPU_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define MPU_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -132,8 +132,8 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Enable CORTEX MPU Region Enable * @{ */ -#define MPU_REGION_ENABLE 1U -#define MPU_REGION_DISABLE 0U +#define MPU_REGION_ENABLE 1U /*!< Enable region */ +#define MPU_REGION_DISABLE 0U /*!< Disable region */ /** * @} */ @@ -141,8 +141,8 @@ typedef struct /** @defgroup CORTEX_MPU_Instruction_Access CORTEX MPU Instruction Access * @{ */ -#define MPU_INSTRUCTION_ACCESS_ENABLE 0U -#define MPU_INSTRUCTION_ACCESS_DISABLE 1U +#define MPU_INSTRUCTION_ACCESS_ENABLE 0U /*!< Execute attribute */ +#define MPU_INSTRUCTION_ACCESS_DISABLE 1U /*!< Execute never attribute */ /** * @} */ @@ -150,9 +150,9 @@ typedef struct /** @defgroup CORTEX_MPU_Access_Shareable CORTEX MPU Instruction Access Shareable * @{ */ -#define MPU_ACCESS_NOT_SHAREABLE 0U -#define MPU_ACCESS_OUTER_SHAREABLE 2U -#define MPU_ACCESS_INNER_SHAREABLE 3U +#define MPU_ACCESS_NOT_SHAREABLE 0U /*!< Not shareable attribute */ +#define MPU_ACCESS_OUTER_SHAREABLE 2U /*!< Outer shareable attribute */ +#define MPU_ACCESS_INNER_SHAREABLE 3U /*!< Inner shareable attribute */ /** * @} */ @@ -160,10 +160,10 @@ typedef struct /** @defgroup CORTEX_MPU_Region_Permission_Attributes CORTEX MPU Region Permission Attributes * @{ */ -#define MPU_REGION_PRIV_RW 0U -#define MPU_REGION_ALL_RW 1U -#define MPU_REGION_PRIV_RO 2U -#define MPU_REGION_ALL_RO 3U +#define MPU_REGION_PRIV_RW 0U /*!< Read/write privileged-only attribute */ +#define MPU_REGION_ALL_RW 1U /*!< Read/write privileged/unprivileged attribute */ +#define MPU_REGION_PRIV_RO 2U /*!< Read-only privileged-only attribute */ +#define MPU_REGION_ALL_RO 3U /*!< Read-only privileged/unprivileged attribute */ /** * @} */ @@ -201,18 +201,26 @@ typedef struct /** @defgroup CORTEX_MPU_Attributes CORTEX MPU Attributes * @{ */ -#define MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ +/* Device memory attributes */ +#define MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ +/* Normal memory attributes */ +/* To set with INNER_OUTER() macro for both inner/outer cache attributes */ + +/* Non-cacheable memory attribute */ +#define MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ #define MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ #define MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - +/* - transient mode attribute */ #define MPU_TRANSIENT 0x0U /* Normal memory, transient. */ #define MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - +/* - allocation attribute */ #define MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ #define MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ #define MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h index 238cc06022..44287eff56 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_cryp_ex.h @@ -93,8 +93,10 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h index f91e1883d1..48f753ebe3 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_dac.h @@ -276,9 +276,16 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); /** @defgroup DAC_ConnectOnChipPeripheral DAC ConnectOnChipPeripheral * @{ */ -#define DAC_CHIPCONNECT_DISABLE (0x00000000UL) -#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) - +#define DAC_CHIPCONNECT_DISABLE (0x00000000UL) /*!< DAC channel output is connected to external + pin. + Note: Depending on other parameters (mode normal or sample and hold, + output buffer state), output can also be connected to on-chip + peripherals, refer to ref manual. */ +#define DAC_CHIPCONNECT_ENABLE (DAC_MCR_MODE1_0) /*!< DAC channel output is connected to on-chip + peripherals (via internal paths). + Note: Depending on other parameters (mode normal or sample and hold, + output buffer state), output can also be connected to external pin, + refer to ref manual. */ /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_exti.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_exti.h index 5350f24af6..ee2c0bfad9 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_exti.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_exti.h @@ -313,8 +313,8 @@ typedef struct */ /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** @@ -326,10 +326,10 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @{ */ /* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h index 789547a6e5..aa634a7d92 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_fdcan.h @@ -517,8 +517,8 @@ typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */ #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */ #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */ -#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */ -#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Get element from empty FIFO */ +#define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Put element in full FIFO */ #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */ #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */ #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_gpio.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_gpio.h index 74be0cabc4..20a276d43b 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_gpio.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_gpio.h @@ -340,7 +340,7 @@ typedef enum */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** @@ -353,7 +353,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); @@ -373,7 +373,7 @@ void HAL_GPIO_EXTI_Falling_Callback(uint16_t GPIO_Pin); /* IO attributes management functions *****************************************/ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t PinAttributes); -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes); +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes); /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash.h index f35cea7e99..8e7f62aeb4 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash.h @@ -117,13 +117,13 @@ typedef struct { HASH_InitTypeDef Init; /*!< HASH required parameters */ - uint8_t *pHashInBuffPtr; /*!< Pointer to input buffer */ + uint8_t const *pHashInBuffPtr; /*!< Pointer to input buffer */ uint8_t *pHashOutBuffPtr; /*!< Pointer to output buffer (digest) */ uint8_t *pHashKeyBuffPtr; /*!< Pointer to key buffer (HMAC only) */ - uint8_t *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ + uint8_t const *pHashMsgBuffPtr; /*!< Pointer to message buffer (HMAC only) */ uint32_t HashBuffSize; /*!< Size of buffer to be processed */ @@ -476,15 +476,17 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS /* HASH processing using polling *********************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); @@ -497,15 +499,15 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p */ /* HASH processing using IT **************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); /** @@ -517,9 +519,9 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash); */ /* HASH processing using DMA *************************************************/ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -531,9 +533,11 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu */ /* HASH-MAC processing using polling *****************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -544,9 +548,9 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @{ */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -558,8 +562,8 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ /* HASH-HMAC processing using DMA ********************************************/ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -571,13 +575,13 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn /* Peripheral State methods **************************************************/ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash); -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash); -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer); +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash); +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash); +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer); void HAL_HASH_SwFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash); -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash); /** * @} @@ -594,19 +598,27 @@ uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash); */ /* Private functions */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm); -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm); +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm); /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash_ex.h index 1a821466ad..35857c39c2 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_hash_ex.h @@ -50,15 +50,15 @@ extern "C" { * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -69,15 +69,17 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer); /** @@ -87,9 +89,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin /** @addtogroup HASHEx_Exported_Functions_Group3 HASH extended processing functions in DMA mode * @{ */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, uint32_t Timeout); /** @@ -99,9 +101,9 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p /** @addtogroup HASHEx_Exported_Functions_Group4 HMAC extended processing functions in polling mode * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout); /** * @} @@ -111,9 +113,9 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer); /** @@ -124,8 +126,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); /** * @} @@ -135,20 +137,24 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @{ */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); - -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); + +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size); /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h index 769e524bce..2c1dd248c3 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_icache.h @@ -71,7 +71,7 @@ typedef struct /** @defgroup ICACHE_WaysSelection Ways selection * @{ */ -#define ICACHE_1WAY 0U /*!< 1-way cache (direct mapped cache) */ +#define ICACHE_1WAY 0UL /*!< 1-way cache (direct mapped cache) */ #define ICACHE_2WAYS ICACHE_CR_WAYSEL /*!< 2-ways set associative cache (default) */ /** * @} @@ -90,10 +90,10 @@ typedef struct /** @defgroup ICACHE_Region Remapped Region number * @{ */ -#define ICACHE_REGION_0 0U /*!< Region 0 */ -#define ICACHE_REGION_1 1U /*!< Region 1 */ -#define ICACHE_REGION_2 2U /*!< Region 2 */ -#define ICACHE_REGION_3 3U /*!< Region 3 */ +#define ICACHE_REGION_0 0UL /*!< Region 0 */ +#define ICACHE_REGION_1 1UL /*!< Region 1 */ +#define ICACHE_REGION_2 2UL /*!< Region 2 */ +#define ICACHE_REGION_3 3UL /*!< Region 3 */ /** * @} */ @@ -101,13 +101,13 @@ typedef struct /** @defgroup ICACHE_Region_Size Remapped Region size * @{ */ -#define ICACHE_REGIONSIZE_2MB 1U /*!< Region size 2MB */ -#define ICACHE_REGIONSIZE_4MB 2U /*!< Region size 4MB */ -#define ICACHE_REGIONSIZE_8MB 3U /*!< Region size 8MB */ -#define ICACHE_REGIONSIZE_16MB 4U /*!< Region size 16MB */ -#define ICACHE_REGIONSIZE_32MB 5U /*!< Region size 32MB */ -#define ICACHE_REGIONSIZE_64MB 6U /*!< Region size 64MB */ -#define ICACHE_REGIONSIZE_128MB 7U /*!< Region size 128MB */ +#define ICACHE_REGIONSIZE_2MB 1UL /*!< Region size 2MB */ +#define ICACHE_REGIONSIZE_4MB 2UL /*!< Region size 4MB */ +#define ICACHE_REGIONSIZE_8MB 3UL /*!< Region size 8MB */ +#define ICACHE_REGIONSIZE_16MB 4UL /*!< Region size 16MB */ +#define ICACHE_REGIONSIZE_32MB 5UL /*!< Region size 32MB */ +#define ICACHE_REGIONSIZE_64MB 6UL /*!< Region size 64MB */ +#define ICACHE_REGIONSIZE_128MB 7UL /*!< Region size 128MB */ /** * @} */ @@ -115,7 +115,7 @@ typedef struct /** @defgroup ICACHE_Traffic_Route Remapped Traffic route * @{ */ -#define ICACHE_MASTER1_PORT 0U /*!< Master1 port */ +#define ICACHE_MASTER1_PORT 0UL /*!< Master1 port */ #define ICACHE_MASTER2_PORT ICACHE_CRRx_MSTSEL /*!< Master2 port */ /** * @} @@ -124,7 +124,7 @@ typedef struct /** @defgroup ICACHE_Output_Burst_Type Remapped Output burst type * @{ */ -#define ICACHE_OUTPUT_BURST_WRAP 0U /*!< WRAP */ +#define ICACHE_OUTPUT_BURST_WRAP 0UL /*!< WRAP */ #define ICACHE_OUTPUT_BURST_INCR ICACHE_CRRx_HBURST /*!< INCR */ /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h index 0e1a57eb1a..6b2bdc1d2b 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_lptim.h @@ -768,9 +768,9 @@ void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h index 3f4914d076..e3aa9d1498 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_mmc.h @@ -721,9 +721,9 @@ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_Parti * @{ */ HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc); -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTypeDef *pCSD); -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo); HAL_StatusTypeDef HAL_MMC_GetCardExtCSD(MMC_HandleTypeDef *hmmc, uint32_t *pExtCSD, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h index 3b2bf58cc2..acbaff82bf 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_nand.h @@ -193,7 +193,7 @@ HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingT FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing); HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand); -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig); +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig); HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h index d8c73b0370..08032cc05e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_ospi.h @@ -780,6 +780,7 @@ HAL_StatusTypeDef HAL_OSPI_AutoPolling_IT(OSPI_HandleTypeDef *hospi, OSPI_Au /* OSPI memory-mapped mode functions */ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMappedTypeDef *cfg); +uint32_t HAL_OSPI_IsMemoryMapped(OSPI_HandleTypeDef *hospi); /* Callback functions in non-blocking modes ***********************************/ void HAL_OSPI_ErrorCallback(OSPI_HandleTypeDef *hospi); @@ -847,7 +848,7 @@ uint32_t HAL_OSPI_GetState(const OSPI_HandleTypeDef *hospi); #define IS_OSPI_DEVICE_SIZE(SIZE) (((SIZE) >= 1U) && ((SIZE) <= 32U)) -#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 8U)) +#define IS_OSPI_CS_HIGH_TIME(TIME) (((TIME) >= 1U) && ((TIME) <= 64U)) #define IS_OSPI_FREE_RUN_CLK(CLK) (((CLK) == HAL_OSPI_FREERUNCLK_DISABLE) || \ ((CLK) == HAL_OSPI_FREERUNCLK_ENABLE)) diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h index cd6c952200..2263af95ec 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd.h @@ -366,7 +366,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); */ -#define USB_WAKEUP_EXTI_LINE (0x1U << 2) /*!< USB FS EXTI Line WakeUp Interrupt */ +#define USB_WAKEUP_EXTI_LINE (0x1UL << 2) /*!< USB FS EXTI Line WakeUp Interrupt */ /** @@ -418,8 +418,8 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); */ /******************** Bit definition for USB_COUNTn_RX register *************/ -#define USB_CNTRX_NBLK_MSK (0x1FU << 10) -#define USB_CNTRX_BLSIZE (0x1U << 15) +#define USB_CNTRX_NBLK_MSK (0x1FUL << 10) +#define USB_CNTRX_BLSIZE (0x1UL << 15) /* SetENDPOINT */ #define PCD_SET_ENDPOINT(USBx, bEpNum, wRegValue) \ @@ -808,7 +808,7 @@ PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef const *hpcd); \ if ((wCount) == 0U) \ { \ - *(pdwReg) |= USB_CNTRX_BLSIZE; \ + *(pdwReg) |= (uint16_t)USB_CNTRX_BLSIZE; \ } \ else if ((wCount) <= 62U) \ { \ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd_ex.h index 48aa2a0079..9843ac017e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pcd_ex.h @@ -47,7 +47,6 @@ extern "C" { */ - HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr, uint16_t ep_kind, uint32_t pmaadress); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr.h index 06c3242f6e..ffe989050a 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr.h @@ -440,7 +440,7 @@ void HAL_PWR_DisableBkUpAccess(void); */ /* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr_ex.h index 5fbc14a6d3..c435b62269 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_pwr_ex.h @@ -824,7 +824,7 @@ void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_DisablePVM3(void); void HAL_PWREx_EnablePVM4(void); void HAL_PWREx_DisablePVM4(void); -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM); /* Low Power modes configuration functions ************************************/ void HAL_PWREx_EnableLowPowerRunMode(void); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h index d949e973f6..719c9cf3ae 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc.h @@ -3204,7 +3204,7 @@ typedef struct * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK Main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -3555,7 +3555,7 @@ typedef struct /* Initialization and de-initialization functions ******************************/ HAL_StatusTypeDef HAL_RCC_DeInit(void); HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct); -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency); /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc_ex.h index 72b6c0a011..89e3ff04ae 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rcc_ex.h @@ -1923,7 +1923,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void); * @{ */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit); +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit); void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void); void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo); uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h index e91d76274d..ce992c0cd5 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h index 967b2d6326..dd06ccc770 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,11 +196,11 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Exported_Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc.h index 706503a25d..da1a13c478 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc.h @@ -751,14 +751,14 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef const *hrtc); +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef const *hrtc); +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef const *hrtc); +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef const *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc); /** * @} */ @@ -770,7 +770,7 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); @@ -782,7 +782,7 @@ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef const *hrtc); /** * @} */ @@ -791,7 +791,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc); /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc_ex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc_ex.h index 49cc4d7957..3e7add3703 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc_ex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_rtc_ex.h @@ -1344,7 +1344,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); @@ -1361,7 +1361,7 @@ void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr); HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef const *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); @@ -1383,8 +1383,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance); -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef const *hrtc, uint32_t Instance); +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef const *hrtc, uint32_t Instance, uint32_t *Value); /** * @} */ @@ -1403,17 +1403,17 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t /** @defgroup RTCEx_Exported_Functions_Group5 Extended RTC Tamper functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper); -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed); -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper); -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper); -HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef const *hrtc, RTC_TamperTypeDef const *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef const *hrtc, RTC_TamperTypeDef const *sTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef const *sAllTamper); +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t const *pSeed); +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef const *hrtc, uint32_t Tamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef const *hrtc); +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef const *hrtc, uint32_t Tamper, uint32_t Timeout); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef const *hrtc, RTC_InternalTamperTypeDef const *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef const *hrtc, RTC_InternalTamperTypeDef const *sIntTamper); +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef const *hrtc, uint32_t IntTamper); +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef const *hrtc, uint32_t IntTamper, uint32_t Timeout); void HAL_RTCEx_TamperIRQHandler(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc); @@ -1428,12 +1428,12 @@ void HAL_RTCEx_InternalTamper2EventCallback(RTC_HandleTypeDef *hrtc void HAL_RTCEx_InternalTamper3EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper5EventCallback(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc); -void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc); +void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef const *hrtc); +void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef const *hrtc); +void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef const *hrtc); +void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef const *hrtc); +void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef const *hrtc); +void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef const *hrtc); /** * @} */ @@ -1441,8 +1441,8 @@ void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc); /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions * @{ */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef const *hrtc, uint32_t BackupRegister, uint32_t Data); +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef const *hrtc, uint32_t BackupRegister); /** * @} */ @@ -1450,10 +1450,10 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg /** @defgroup RTCEx_Exported_Functions_Group7 Extended RTC secure functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState); #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) -HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState); +HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef const *hrtc, RTC_SecureStateTypeDef const *secureState); #endif /* #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef const *hrtc, RTC_SecureStateTypeDef *secureState); /** * @} */ @@ -1461,8 +1461,8 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureSta /** @defgroup RTCEx_Exported_Functions_Group8 Extended RTC privilege functions * @{ */ -HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState); -HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState); +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef const *hrtc, RTC_PrivilegeStateTypeDef const *privilegeState); +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef const *hrtc, RTC_PrivilegeStateTypeDef *privilegeState); /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h index 0bb5216581..8784f55346 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_sd.h @@ -691,10 +691,10 @@ HAL_StatusTypeDef HAL_SD_ConfigSpeedBusOperation(SD_HandleTypeDef *hsd, uint32_t * @{ */ HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd); -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID); HAL_StatusTypeDef HAL_SD_GetCardCSD(SD_HandleTypeDef *hsd, HAL_SD_CardCSDTypeDef *pCSD); HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypeDef *pStatus); -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo); /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smartcard.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smartcard.h index 43cb1bb604..017116ed0a 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smartcard.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_smartcard.h @@ -722,13 +722,13 @@ typedef enum */ #define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ SMARTCARD_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U <<\ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi.h index 6aa2a6159c..6947878761 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h index 842ae715fb..ed914e7b13 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_tim.h @@ -1749,7 +1749,8 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} @@ -2098,20 +2099,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2125,16 +2121,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) /** * @} diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart.h index ea75979830..fd0d0f8f68 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_uart.h @@ -47,12 +47,10 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the UART communication baud rate. The baud rate register is computed using the following formula: - LPUART: - ======= + @note For LPUART : Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - UART: - ===== + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : - If oversampling is 16 or in LIN mode, Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - If oversampling is 8, @@ -1230,7 +1228,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1245,8 +1243,7 @@ typedef void (*pUART_RxEventCallbackTypeDef) ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h index e614c81737..6f4e708a41 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_usart.h @@ -546,10 +546,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -571,10 +571,10 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ - ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ - ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) + ((__HANDLE__)->Instance->CR2 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -704,8 +704,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == USART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register in 8-bit oversampling mode. * @param __PCLK__ USART clock. diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h index 2182fa79c7..763f7c94df 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_hal_wwdg.h @@ -191,7 +191,7 @@ typedef void (*pWWDG_CallbackTypeDef)(WWDG_HandleTypeDef *hppp); /*!< pointer t /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h index 5c5d4c9340..ba6fe0a0a6 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_adc.h @@ -81,8 +81,6 @@ extern "C" { #define ADC_REG_RANK_15_SQRX_BITOFFSET_POS ( 0UL) /* Equivalent to bitfield "ADC_SQR4_SQ15" position in register */ #define ADC_REG_RANK_16_SQRX_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_SQR4_SQ16" position in register */ - - /* Internal mask for ADC group injected sequencer: */ /* To select into literal LL_ADC_INJ_RANK_x the relevant bits for: */ /* - data register offset */ @@ -107,8 +105,6 @@ extern "C" { #define ADC_INJ_RANK_3_JSQR_BITOFFSET_POS (20UL) /* Equivalent to bitfield "ADC_JSQR_JSQ3" position in register */ #define ADC_INJ_RANK_4_JSQR_BITOFFSET_POS (26UL) /* Equivalent to bitfield "ADC_JSQR_JSQ4" position in register */ - - /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ @@ -137,8 +133,6 @@ extern "C" { #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR_EXTSEL" position in register */ #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR_EXTEN" position in register */ - - /* Internal mask for ADC group injected trigger: */ /* To select into literal LL_ADC_INJ_TRIG_x the relevant bits for: */ /* - injected trigger source */ @@ -167,11 +161,6 @@ extern "C" { #define ADC_INJ_TRIG_EXTSEL_BITOFFSET_POS ( 2UL) /* Equivalent to bitfield "ADC_JSQR_JEXTSEL" position in register */ #define ADC_INJ_TRIG_EXTEN_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_JSQR_JEXTEN" position in register */ - - - - - /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ @@ -368,17 +357,17 @@ extern "C" { /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x0BFA05AAUL)) /* Internal voltage reference, address of +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x0BFA05AAUL)) /* Internal voltage reference, address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF (3000UL) /* Analog voltage reference (Vref+) value with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x0BFA05A8UL)) /* Address of parameter TS_CAL1: On STM32L5, +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x0BFA05A8UL)) /* Address of parameter TS_CAL1: temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x0BFA05CAUL)) /* Address of parameter TS_CAL2: On STM32L5, +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x0BFA05CAUL)) /* Address of parameter TS_CAL2: temperature sensor ADC raw data acquired at temperature 110 DegC (tolerance: +-5 DegC), Vref+ = 3.0 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (30L) /* Temperature at which temperature sensor @@ -394,7 +383,6 @@ extern "C" { * @} */ - /* Private macros ------------------------------------------------------------*/ /** @defgroup ADC_LL_Private_Macros ADC Private Macros * @{ @@ -415,7 +403,6 @@ extern "C" { * @} */ - /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup ADC_LL_ES_INIT ADC Exported Init structure diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h index 9dc17b6512..1c1949ce64 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_cortex.h @@ -101,10 +101,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_HFNMI_PRIVDEF_Control MPU HFNMI and PRIVILEGED Access control * @{ */ -#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U -#define LL_MPU_CTRL_HARDFAULT_NMI 2U -#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U -#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U +#define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE 0U /*!< Background region access not allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HARDFAULT_NMI 2U /*!< Background region access not allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_PRIVILEGED_DEFAULT 4U /*!< Background region privileged-only access allowed, MPU disabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ +#define LL_MPU_CTRL_HFNMI_PRIVDEF 6U /*!< Background region privileged-only access allowed, MPU enabled for Hardfaults, NMIs, and exception handlers when FAULTMASK=1 */ /** * @} */ @@ -112,18 +112,24 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Attributes MPU Attributes * @{ */ -#define LL_MPU_DEVICE_nGnRnE 0x0U /* Device, noGather, noReorder, noEarly acknowledge. */ -#define LL_MPU_DEVICE_nGnRE 0x4U /* Device, noGather, noReorder, Early acknowledge. */ -#define LL_MPU_DEVICE_nGRE 0x8U /* Device, noGather, Reorder, Early acknowledge. */ -#define LL_MPU_DEVICE_GRE 0xCU /* Device, Gather, Reorder, Early acknowledge. */ +/* Device memory attributes */ +#define LL_MPU_DEVICE_nGnRnE 0x0U /*!< Device non-Gathering, non-Reordering, no Early write acknowledgement */ +#define LL_MPU_DEVICE_nGnRE 0x4U /*!< Device non-Gathering, non-Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_nGRE 0x8U /*!< Device non-Gathering, Reordering, Early write acknowledgement */ +#define LL_MPU_DEVICE_GRE 0xCU /*!< Device Gathering, Reordering, Early write acknowledgement */ +/* Normal memory attributes */ +/* Non-cacheable memory attribute */ +#define LL_MPU_NOT_CACHEABLE 0x4U /*!< Normal memory, non-cacheable */ + +/* Cacheable memory attributes: combination of cache write policy, transient and allocation */ +/* - cache write policy */ #define LL_MPU_WRITE_THROUGH 0x0U /* Normal memory, write-through. */ -#define LL_MPU_NOT_CACHEABLE 0x4U /* Normal memory, non-cacheable. */ #define LL_MPU_WRITE_BACK 0x4U /* Normal memory, write-back. */ - +/* - transient mode attribute */ #define LL_MPU_TRANSIENT 0x0U /* Normal memory, transient. */ #define LL_MPU_NON_TRANSIENT 0x8U /* Normal memory, non-transient. */ - +/* - allocation attribute */ #define LL_MPU_NO_ALLOCATE 0x0U /* Normal memory, no allocate. */ #define LL_MPU_W_ALLOCATE 0x1U /* Normal memory, write allocate. */ #define LL_MPU_R_ALLOCATE 0x2U /* Normal memory, read allocate. */ @@ -144,8 +150,8 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Instruction_Access MPU Instruction Access * @{ */ -#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) -#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) +#define LL_MPU_INSTRUCTION_ACCESS_ENABLE (0U << MPU_RBAR_XN_Pos) /*!< Execute attribute */ +#define LL_MPU_INSTRUCTION_ACCESS_DISABLE (1U << MPU_RBAR_XN_Pos) /*!< Execute never attribute */ /** * @} */ @@ -153,9 +159,9 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Access_Shareable MPU Instruction Access Shareable * @{ */ -#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) -#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) +#define LL_MPU_ACCESS_NOT_SHAREABLE (0U << MPU_RBAR_SH_Pos) /*!< Not shareable attribute */ +#define LL_MPU_ACCESS_OUTER_SHAREABLE (2U << MPU_RBAR_SH_Pos) /*!< Outer shareable attribute */ +#define LL_MPU_ACCESS_INNER_SHAREABLE (3U << MPU_RBAR_SH_Pos) /*!< Inner shareable attribute */ /** * @} */ @@ -163,10 +169,10 @@ extern "C" { /** @defgroup CORTEX_LL_MPU_Region_Permission_Attributes MPU Region Permission Attributes * @{ */ -#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) -#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) +#define LL_MPU_REGION_PRIV_RW (0U << MPU_RBAR_AP_Pos) /*!< Read/write privileged-only attribute */ +#define LL_MPU_REGION_ALL_RW (1U << MPU_RBAR_AP_Pos) /*!< Read/write privileged/unprivileged attribute */ +#define LL_MPU_REGION_PRIV_RO (2U << MPU_RBAR_AP_Pos) /*!< Read-only privileged-only attribute */ +#define LL_MPU_REGION_ALL_RO (3U << MPU_RBAR_AP_Pos) /*!< Read-only privileged/unprivileged attribute */ /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crs.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crs.h index 9cc2f0a77e..e18974ef70 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crs.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_crs.h @@ -41,7 +41,6 @@ extern "C" { /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ - /* Exported types ------------------------------------------------------------*/ /* Exported constants --------------------------------------------------------*/ /** @defgroup CRS_LL_Exported_Constants CRS Exported Constants @@ -135,11 +134,12 @@ extern "C" { /** * @brief Reset value of the HSI48 Calibration field - * @note The default value is 64, which corresponds to the middle of the trimming interval. + * @note The default value is 64, + * which corresponds to the middle of the trimming interval. * The trimming step is specified in the product datasheet. * A higher TRIM value corresponds to a higher output frequency. */ -#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U +#define LL_CRS_HSI48CALIBRATION_DEFAULT 0x00000040U /** * @} */ @@ -437,19 +437,22 @@ __STATIC_INLINE uint32_t LL_CRS_GetSyncPolarity(void) * CFGR SYNCDIV LL_CRS_ConfigSynchronization\n * CFGR SYNCSRC LL_CRS_ConfigSynchronization\n * CFGR SYNCPOL LL_CRS_ConfigSynchronization - * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 63 + * @param HSI48CalibrationValue a number between Min_Data = 0 and Max_Data = 127 * @param ErrorLimitValue a number between Min_Data = 0 and Max_Data = 0xFFFF * @param ReloadValue a number between Min_Data = 0 and Max_Data = 255 * @param Settings This parameter can be a combination of the following values: - * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 or @ref LL_CRS_SYNC_DIV_8 - * or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 + * @arg @ref LL_CRS_SYNC_DIV_1 or @ref LL_CRS_SYNC_DIV_2 or @ref LL_CRS_SYNC_DIV_4 + * or @ref LL_CRS_SYNC_DIV_8 or @ref LL_CRS_SYNC_DIV_16 or @ref LL_CRS_SYNC_DIV_32 + * or @ref LL_CRS_SYNC_DIV_64 or @ref LL_CRS_SYNC_DIV_128 * @arg @ref LL_CRS_SYNC_SOURCE_GPIO or @ref LL_CRS_SYNC_SOURCE_LSE or @ref LL_CRS_SYNC_SOURCE_USB * @arg @ref LL_CRS_SYNC_POLARITY_RISING or @ref LL_CRS_SYNC_POLARITY_FALLING * @retval None */ -__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, uint32_t ReloadValue, uint32_t Settings) +__STATIC_INLINE void LL_CRS_ConfigSynchronization(uint32_t HSI48CalibrationValue, uint32_t ErrorLimitValue, + uint32_t ReloadValue, uint32_t Settings) { - MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue); + MODIFY_REG(CRS->CR, CRS_CR_TRIM, HSI48CalibrationValue << CRS_CR_TRIM_Pos); + MODIFY_REG(CRS->CFGR, CRS_CFGR_RELOAD | CRS_CFGR_FELIM | CRS_CFGR_SYNCDIV | CRS_CFGR_SYNCSRC | CRS_CFGR_SYNCPOL, ReloadValue | (ErrorLimitValue << CRS_CFGR_FELIM_Pos) | Settings); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dmamux.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dmamux.h index ceec8b463a..2d3d399b74 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dmamux.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_dmamux.h @@ -529,7 +529,7 @@ extern "C" { * @arg @ref LL_DMAMUX_REQ_UCPD1_RX * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -655,7 +655,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_UCPD1_TX * @arg @ref LL_DMAMUX_REQ_UCPD1_RX */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -685,7 +685,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); @@ -714,7 +714,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); @@ -748,7 +748,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); @@ -781,7 +781,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); @@ -810,7 +810,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); @@ -839,7 +839,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); @@ -868,7 +868,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE))? 1UL : 0UL); @@ -897,7 +897,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); @@ -926,7 +926,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); @@ -955,7 +955,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE))? 1UL : 0UL); @@ -1008,7 +1008,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); @@ -1060,7 +1060,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); @@ -1077,7 +1077,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); @@ -1094,7 +1094,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); @@ -1111,7 +1111,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE))? 1UL : 0UL); @@ -1133,7 +1133,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) { (void)(DMAMUXx); MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); @@ -1154,7 +1154,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); @@ -1173,7 +1173,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) { (void)(DMAMUXx); MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); @@ -1190,7 +1190,7 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); @@ -1231,7 +1231,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) { (void)(DMAMUXx); MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); @@ -1271,7 +1271,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); @@ -1291,7 +1291,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); @@ -1303,7 +1303,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); @@ -1315,7 +1315,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); @@ -1327,7 +1327,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); @@ -1339,7 +1339,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); @@ -1351,7 +1351,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); @@ -1363,7 +1363,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); @@ -1375,7 +1375,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); @@ -1387,7 +1387,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); @@ -1399,7 +1399,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); @@ -1411,7 +1411,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); @@ -1423,7 +1423,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); @@ -1435,7 +1435,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); @@ -1447,7 +1447,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); @@ -1459,7 +1459,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL); @@ -1471,7 +1471,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL); @@ -1483,7 +1483,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); @@ -1495,7 +1495,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); @@ -1507,7 +1507,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); @@ -1519,7 +1519,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); @@ -1531,7 +1531,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef * DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); @@ -1543,7 +1543,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef * DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); @@ -1555,7 +1555,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); @@ -1567,7 +1567,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); @@ -1579,7 +1579,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); @@ -1591,7 +1591,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); @@ -1603,7 +1603,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); @@ -1615,7 +1615,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); @@ -1627,7 +1627,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); @@ -1639,7 +1639,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); @@ -1651,7 +1651,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); @@ -1663,7 +1663,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); @@ -1675,7 +1675,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); @@ -1687,7 +1687,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); @@ -1699,7 +1699,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF14); @@ -1711,7 +1711,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF15); @@ -1723,7 +1723,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); @@ -1735,7 +1735,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); @@ -1747,7 +1747,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); @@ -1759,7 +1759,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); @@ -1796,7 +1796,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); @@ -1825,7 +1825,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); @@ -1854,7 +1854,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_15 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE))? 1UL : 0UL); @@ -1871,7 +1871,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); @@ -1888,7 +1888,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); @@ -1905,7 +1905,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE))? 1UL : 0UL); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_fmc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_fmc.h index c75b8dcff2..af4d98231d 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_fmc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_fmc.h @@ -143,74 +143,75 @@ extern "C" { typedef struct { uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used. - This parameter can be a value of @ref FMC_NORSRAM_Bank */ + This parameter can be a value of @ref FMC_NORSRAM_Bank */ uint32_t DataAddressMux; /*!< Specifies whether the address and data values are multiplexed on the data bus or not. - This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */ + This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing*/ uint32_t MemoryType; /*!< Specifies the type of external memory attached to the corresponding memory device. - This parameter can be a value of @ref FMC_Memory_Type */ + This parameter can be a value of @ref FMC_Memory_Type */ uint32_t MemoryDataWidth; /*!< Specifies the external memory device width. - This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ + This parameter can be a value of @ref FMC_NORSRAM_Data_Width */ uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory, valid only with synchronous burst Flash memories. - This parameter can be a value of @ref FMC_Burst_Access_Mode */ + This parameter can be a value of @ref FMC_Burst_Access_Mode */ uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing the Flash memory in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ + This parameter can be a value of @ref FMC_Wait_Signal_Polarity */ uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one clock cycle before the wait state or during the wait state, valid only when accessing memories in burst mode. - This parameter can be a value of @ref FMC_Wait_Timing */ + This parameter can be a value of @ref FMC_Wait_Timing */ - uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC. - This parameter can be a value of @ref FMC_Write_Operation */ + uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device + by the FMC. + This parameter can be a value of @ref FMC_Write_Operation */ uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait signal, valid for Flash memory access in burst mode. - This parameter can be a value of @ref FMC_Wait_Signal */ + This parameter can be a value of @ref FMC_Wait_Signal */ uint32_t ExtendedMode; /*!< Enables or disables the extended mode. - This parameter can be a value of @ref FMC_Extended_Mode */ + This parameter can be a value of @ref FMC_Extended_Mode */ uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers, valid only with asynchronous Flash memories. - This parameter can be a value of @ref FMC_AsynchronousWait */ + This parameter can be a value of @ref FMC_AsynchronousWait */ uint32_t WriteBurst; /*!< Enables or disables the write burst operation. - This parameter can be a value of @ref FMC_Write_Burst */ + This parameter can be a value of @ref FMC_Write_Burst */ uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Continous_Clock */ + This parameter can be a value of @ref FMC_Continous_Clock */ uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller. This parameter is only enabled through the FMC_BCR1 register, and don't care through FMC_BCR2..4 registers. - This parameter can be a value of @ref FMC_Write_FIFO */ + This parameter can be a value of @ref FMC_Write_FIFO */ uint32_t PageSize; /*!< Specifies the memory page size. - This parameter can be a value of @ref FMC_Page_Size */ + This parameter can be a value of @ref FMC_Page_Size */ uint32_t NBLSetupTime; /*!< Specifies the NBL setup timing clock cycle number - This parameter can be a value of @ref FMC_Byte_Lane */ + This parameter can be a value of @ref FMC_Byte_Lane */ FunctionalState MaxChipSelectPulse; /*!< Enables or disables the maximum chip select pulse management in this NSBank for PSRAM refresh. - This parameter can be set to ENABLE or DISABLE */ + This parameter can be set to ENABLE or DISABLE */ uint32_t MaxChipSelectPulseTime; /*!< Specifies the maximum chip select pulse time in FMC_CLK cycles for synchronous accesses and in HCLK cycles for asynchronous accesses, valid only if MaxChipSelectPulse is ENABLE. This parameter can be a value between Min_Data = 1 and Max_Data = 65535. - @note: This parameter is common to all NSBank. */ + @note: This parameter is common to all NSBank. */ } FMC_NORSRAM_InitTypeDef; /** @@ -259,7 +260,7 @@ typedef struct in NOR Flash memories with synchronous burst mode enable */ uint32_t AccessMode; /*!< Specifies the asynchronous access mode. - This parameter can be a value of @ref FMC_Access_Mode */ + This parameter can be a value of @ref FMC_Access_Mode */ } FMC_NORSRAM_TimingTypeDef; /** @@ -746,11 +747,11 @@ typedef struct * @{ */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init); + const FMC_NORSRAM_InitTypeDef *Init); HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode); HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank); @@ -776,11 +777,11 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Devic /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions * @{ */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init); +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init); HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); /** * @} @@ -791,7 +792,7 @@ HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank); */ HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank); HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank); -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout); /** * @} @@ -800,8 +801,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, u * @} */ - - /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_gpio.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_gpio.h index aab8f30e53..af933eec30 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_gpio.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_gpio.h @@ -308,7 +308,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->MODER, (GPIO_MODER_MODE0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); @@ -377,7 +377,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) >> POSITION_VAL(Pin)); } @@ -451,7 +451,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, (GPIO_OSPEEDR_OSPEED0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); @@ -517,7 +517,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->PUPDR, (GPIO_PUPDR_PUPD0 << (POSITION_VAL(Pin) * 2U))) >> (POSITION_VAL(Pin) * 2U)); @@ -594,7 +594,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[0], (GPIO_AFRL_AFSEL0 << (POSITION_VAL(Pin) * 4U))) >> (POSITION_VAL(Pin) * 4U)); @@ -672,7 +672,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { return (uint32_t)(READ_BIT(GPIOx->AFR[1], (GPIO_AFRH_AFSEL8 << (POSITION_VAL(Pin >> 8U) * 4U))) >> (POSITION_VAL(Pin >> 8U) * 4U)); @@ -742,7 +742,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -753,7 +753,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -772,7 +772,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -801,7 +801,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -824,7 +824,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -853,7 +853,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -1033,7 +1033,7 @@ __STATIC_INLINE void LL_GPIO_DisablePinSecure(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->SECCFGR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -1048,7 +1048,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsEnabledPinSecure(GPIO_TypeDef *GPIOx, uint32_ * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h index 11140a1b4d..e91f83b741 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_opamp.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_opamp.h index 50a96405fe..9cebc4a3be 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_opamp.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_opamp.h @@ -375,7 +375,7 @@ typedef struct * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH * @retval None */ -__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) +__STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(const OPAMP_Common_TypeDef *OPAMPxy_COMMON, uint32_t PowerRange) { /* Prevent unused parameter warning */ (void)(*OPAMPxy_COMMON); @@ -394,7 +394,7 @@ __STATIC_INLINE void LL_OPAMP_SetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_ * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_LOW * @arg @ref LL_OPAMP_POWERSUPPLY_RANGE_HIGH */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(OPAMP_Common_TypeDef *OPAMPxy_COMMON) +__STATIC_INLINE uint32_t LL_OPAMP_GetCommonPowerRange(const OPAMP_Common_TypeDef *OPAMPxy_COMMON) { /* Prevent unused parameter warning */ (void)(*OPAMPxy_COMMON); @@ -433,7 +433,7 @@ __STATIC_INLINE void LL_OPAMP_SetPowerMode(OPAMP_TypeDef *OPAMPx, uint32_t Power * @arg @ref LL_OPAMP_POWERMODE_NORMALPOWER * @arg @ref LL_OPAMP_POWERMODE_LOWPOWER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPowerMode(const OPAMP_TypeDef *OPAMPx) { uint32_t power_mode = (READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPALPM)); @@ -479,7 +479,7 @@ __STATIC_INLINE void LL_OPAMP_SetMode(OPAMP_TypeDef *OPAMPx, uint32_t Mode) * @arg @ref LL_OPAMP_MODE_FUNCTIONAL * @arg @ref LL_OPAMP_MODE_CALIBRATION */ -__STATIC_INLINE uint32_t LL_OPAMP_GetMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALON)); } @@ -515,7 +515,7 @@ __STATIC_INLINE void LL_OPAMP_SetFunctionalMode(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_MODE_FOLLOWER * @arg @ref LL_OPAMP_MODE_PGA */ -__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetFunctionalMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMODE)); } @@ -550,7 +550,7 @@ __STATIC_INLINE void LL_OPAMP_SetPGAGain(OPAMP_TypeDef *OPAMPx, uint32_t PGAGain * @arg @ref LL_OPAMP_PGA_GAIN_8 * @arg @ref LL_OPAMP_PGA_GAIN_16 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetPGAGain(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_PGGAIN)); } @@ -585,7 +585,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputNonInverting(OPAMP_TypeDef *OPAMPx, uint32 * @arg @ref LL_OPAMP_INPUT_NONINVERT_IO0 * @arg @ref LL_OPAMP_INPUT_NONINV_DAC1_CH1 */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputNonInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VPSEL)); } @@ -618,7 +618,7 @@ __STATIC_INLINE void LL_OPAMP_SetInputInverting(OPAMP_TypeDef *OPAMPx, uint32_t * @arg @ref LL_OPAMP_INPUT_INVERT_IO1 * @arg @ref LL_OPAMP_INPUT_INVERT_CONNECT_NO */ -__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetInputInverting(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_VMSEL)); } @@ -672,7 +672,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingMode(OPAMP_TypeDef *OPAMPx, uint32_t Tr * @arg @ref LL_OPAMP_TRIMMING_FACTORY * @arg @ref LL_OPAMP_TRIMMING_USER */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingMode(const OPAMP_TypeDef *OPAMPx) { return (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_USERTRIM)); } @@ -707,7 +707,7 @@ __STATIC_INLINE void LL_OPAMP_SetCalibrationSelection(OPAMP_TypeDef *OPAMPx, uin * @arg @ref LL_OPAMP_TRIMMING_NMOS * @arg @ref LL_OPAMP_TRIMMING_PMOS */ -__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(const OPAMP_TypeDef *OPAMPx) { uint32_t CalibrationSelection = (uint32_t)(READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALSEL)); @@ -724,7 +724,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_GetCalibrationSelection(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_CALOUT) == OPAMP_CSR_CALOUT) ? 1UL : 0UL); } @@ -747,7 +747,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsCalibrationOutputSet(OPAMP_TypeDef *OPAMPx) * @param TrimmingValue 0x00...0x1F * @retval None */ -__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue) +__STATIC_INLINE void LL_OPAMP_SetTrimmingValue(const OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair, uint32_t TrimmingValue) { __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); @@ -777,7 +777,7 @@ __STATIC_INLINE void LL_OPAMP_SetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t P * @arg @ref LL_OPAMP_TRIMMING_PMOS * @retval 0x0...0x1F */ -__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) +__STATIC_INLINE uint32_t LL_OPAMP_GetTrimmingValue(const OPAMP_TypeDef* OPAMPx, uint32_t PowerMode, uint32_t TransistorsDiffPair) { const __IO uint32_t *preg = __OPAMP_PTR_REG_OFFSET(OPAMPx->OTR, (PowerMode & OPAMP_POWERMODE_OTR_REGOFFSET_MASK)); @@ -828,7 +828,7 @@ __STATIC_INLINE void LL_OPAMP_Disable(OPAMP_TypeDef *OPAMPx) * @param OPAMPx OPAMP instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) +__STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(const OPAMP_TypeDef *OPAMPx) { return ((READ_BIT(OPAMPx->CSR, OPAMP_CSR_OPAMPxEN) == (OPAMP_CSR_OPAMPxEN)) ? 1UL : 0UL); } @@ -843,7 +843,7 @@ __STATIC_INLINE uint32_t LL_OPAMP_IsEnabled(OPAMP_TypeDef *OPAMPx) */ ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef *OPAMPx); -ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct); +ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, const LL_OPAMP_InitTypeDef *OPAMP_InitStruct); void LL_OPAMP_StructInit(LL_OPAMP_InitTypeDef *OPAMP_InitStruct); /** diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h index 89d13b427c..eddbca387e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_pka.h @@ -459,7 +459,18 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); } - +#if defined(PKA_SR_INITOK) +/** + * @brief Get PKA init ok flag. + * @rmtoll SR INITOK LL_PKA_IsActiveFlag_INITOK + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_INITOK(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_INITOK) == (PKA_SR_INITOK)) ? 1UL : 0UL); +} +#endif /* PKA_SR_INITOK */ /** * @brief Clear PKA address error flag. * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h index 4aa6afd661..b781566053 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_rtc.h @@ -973,7 +973,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -1005,7 +1005,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -1032,7 +1032,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); } @@ -1088,7 +1088,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1122,7 +1122,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); } @@ -1183,7 +1183,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1194,7 +1194,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1252,7 +1252,7 @@ __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); } @@ -1285,7 +1285,7 @@ __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); } @@ -1321,7 +1321,7 @@ __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); } @@ -1362,7 +1362,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1397,7 +1397,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1432,7 +1432,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1467,7 +1467,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1521,7 +1521,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef const *RTCx) { uint32_t temp; @@ -1561,7 +1561,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); } @@ -1603,7 +1603,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Sub second value (number between 0 and 65535) */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1660,7 +1660,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1699,7 +1699,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1753,7 +1753,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1783,7 +1783,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1851,7 +1851,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef const *RTCx) { uint32_t temp; @@ -1930,7 +1930,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1980,7 +1980,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -2017,7 +2017,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -2044,7 +2044,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -2072,7 +2072,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2100,7 +2100,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2128,7 +2128,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2175,7 +2175,7 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTime(RTC_TypeDef const *RTCx) { return (uint32_t)((LL_RTC_ALMA_GetHour(RTCx) << RTC_OFFSET_HOUR) | (LL_RTC_ALMA_GetMinute(RTCx) << RTC_OFFSET_MINUTE) | LL_RTC_ALMA_GetSecond(RTCx)); } @@ -2200,7 +2200,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2223,7 +2223,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SS)); } @@ -2296,7 +2296,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2346,7 +2346,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2383,7 +2383,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2410,7 +2410,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2438,7 +2438,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2466,7 +2466,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2494,7 +2494,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef const *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2566,7 +2566,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2589,7 +2589,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SS)); } @@ -2675,7 +2675,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2688,7 +2688,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2701,7 +2701,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2714,7 +2714,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2727,7 +2727,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2745,7 +2745,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2764,7 +2764,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2789,7 +2789,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2802,7 +2802,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2819,7 +2819,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2830,7 +2830,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -2876,7 +2876,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef const *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR1, Tamper); @@ -2892,7 +2892,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef const *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR1, Tamper); @@ -2909,7 +2909,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef const *RTCx, uint32_t Mask) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Mask); @@ -2925,7 +2925,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef const *RTCx, uint32_t Mask) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Mask); @@ -2941,7 +2941,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef const *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Tamper); @@ -2957,7 +2957,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef const *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Tamper); @@ -2969,7 +2969,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t T * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); @@ -2981,7 +2981,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); @@ -2998,7 +2998,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef const *RTCx, uint32_t Duration) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); @@ -3014,7 +3014,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); @@ -3031,7 +3031,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef const *RTCx, uint32_t FilterCount) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); @@ -3047,7 +3047,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); @@ -3068,7 +3068,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef const *RTCx, uint32_t SamplingFreq) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); @@ -3088,7 +3088,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); @@ -3104,7 +3104,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef const *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Tamper); @@ -3120,7 +3120,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef const *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Tamper); @@ -3144,7 +3144,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef const *RTCx, uint32_t InternalTamper) { UNUSED(RTCx); SET_BIT(TAMP->CR1, InternalTamper); @@ -3163,7 +3163,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t Inte * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef const *RTCx, uint32_t InternalTamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR1, InternalTamper); @@ -3385,7 +3385,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); } @@ -3422,7 +3422,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3446,7 +3446,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3499,7 +3499,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef const *RTCx, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -3551,7 +3551,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR31 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef const *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3599,7 +3599,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3626,7 +3626,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); } @@ -3659,7 +3659,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3684,7 +3684,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef const *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3721,7 +3721,7 @@ __STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U); } @@ -3740,7 +3740,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U); } @@ -3751,7 +3751,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); } @@ -3762,7 +3762,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); } @@ -3773,7 +3773,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); } @@ -3784,7 +3784,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); } @@ -3795,7 +3795,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); } @@ -3806,7 +3806,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); } @@ -3883,7 +3883,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); } @@ -3894,7 +3894,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); } @@ -3916,7 +3916,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); } @@ -3927,7 +3927,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); } @@ -3938,7 +3938,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); } @@ -3949,7 +3949,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); } @@ -3960,7 +3960,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); } @@ -3971,7 +3971,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); } @@ -3982,7 +3982,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); } @@ -3993,7 +3993,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); } @@ -4004,7 +4004,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U); } @@ -4015,7 +4015,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); @@ -4027,7 +4027,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); @@ -4039,7 +4039,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); @@ -4050,7 +4050,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP4F) == (TAMP_SR_TAMP4F)) ? 1U : 0U); @@ -4061,7 +4061,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP5F) == (TAMP_SR_TAMP5F)) ? 1U : 0U); @@ -4072,7 +4072,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP6F) == (TAMP_SR_TAMP6F)) ? 1U : 0U); @@ -4083,7 +4083,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP7F) == (TAMP_SR_TAMP7F)) ? 1U : 0U); @@ -4094,7 +4094,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP8F) == (TAMP_SR_TAMP8F)) ? 1U : 0U); @@ -4106,7 +4106,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP1F) == (TAMP_SR_ITAMP1F)) ? 1U : 0U); @@ -4118,7 +4118,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP2F) == (TAMP_SR_ITAMP2F)) ? 1U : 0U); @@ -4130,7 +4130,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); @@ -4143,7 +4143,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); @@ -4155,7 +4155,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); @@ -4167,7 +4167,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); @@ -4179,7 +4179,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); @@ -4191,7 +4191,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); @@ -4202,7 +4202,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP4MF) == (TAMP_MISR_TAMP4MF)) ? 1U : 0U); @@ -4213,7 +4213,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP4M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP5MF) == (TAMP_MISR_TAMP5MF)) ? 1U : 0U); @@ -4224,7 +4224,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP5M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP6MF) == (TAMP_MISR_TAMP6MF)) ? 1U : 0U); @@ -4235,7 +4235,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP6M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP7MF) == (TAMP_MISR_TAMP7MF)) ? 1U : 0U); @@ -4246,7 +4246,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP7M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP8MF) == (TAMP_MISR_TAMP8MF)) ? 1U : 0U); @@ -4258,7 +4258,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP8M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP1MF) == (TAMP_MISR_ITAMP1MF)) ? 1U : 0U); @@ -4270,7 +4270,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP1M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP2MF) == (TAMP_MISR_ITAMP2MF)) ? 1U : 0U); @@ -4282,7 +4282,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP2M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); @@ -4294,7 +4294,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); @@ -4306,7 +4306,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); @@ -4318,7 +4318,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); @@ -4330,7 +4330,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); @@ -4342,7 +4342,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); @@ -4353,7 +4353,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP4F); @@ -4364,7 +4364,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP5F); @@ -4375,7 +4375,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP6F); @@ -4386,7 +4386,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP7F); @@ -4397,7 +4397,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP8F); @@ -4409,7 +4409,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP1F); @@ -4421,7 +4421,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP2F); @@ -4433,7 +4433,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); @@ -4445,7 +4445,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); @@ -4457,7 +4457,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); @@ -4522,7 +4522,7 @@ __STATIC_INLINE void LL_RTC_SetRtcSecure(RTC_TypeDef *RTCx, uint32_t rtcSecure) * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRA * @arg @ref LL_RTC_UNSECURE_FEATURE_ALRB */ -__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef const *RTCx) { return READ_BIT(RTCx->SMCR, RTC_SMCR_DECPROT | RTC_SMCR_INITDPROT | RTC_SMCR_CALDPROT | RTC_SMCR_TSDPROT | RTC_SMCR_WUTDPROT | RTC_SMCR_ALRADPROT | RTC_SMCR_ALRBDPROT); } @@ -4537,7 +4537,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetRtcSecure(RTC_TypeDef *RTCx) * @arg @ref LL_TAMP_SECURE_FULL_NO * @retval None */ -__STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure) +__STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef const *RTCx, uint32_t tampSecure) { UNUSED(RTCx); MODIFY_REG(TAMP->SMCR, TAMP_SMCR_TAMPDPROT, tampSecure); @@ -4552,7 +4552,7 @@ __STATIC_INLINE void LL_RTC_SetTampSecure(RTC_TypeDef *RTCx, uint32_t tampSecure * @arg @ref LL_TAMP_SECURE_FULL_YES * @arg @ref LL_TAMP_SECURE_FULL_NO */ -__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetTampSecure(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->SMCR, TAMP_SMCR_TAMPDPROT); @@ -4614,7 +4614,7 @@ __STATIC_INLINE void LL_RTC_SetRtcPrivilege(RTC_TypeDef *RTCx, uint32_t rtcPrivi * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRA * @arg @ref LL_RTC_PRIVILEGE_FEATURE_ALRB */ -__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef const *RTCx) { return READ_BIT(RTCx->PRIVCR, RTC_PRIVCR_PRIV | RTC_PRIVCR_INITPRIV | RTC_PRIVCR_CALPRIV | RTC_PRIVCR_TSPRIV | RTC_PRIVCR_WUTPRIV | RTC_PRIVCR_ALRAPRIV | RTC_PRIVCR_ALRBPRIV); } @@ -4628,7 +4628,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetRtcPrivilege(RTC_TypeDef *RTCx) * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO * @retval None */ -__STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef *RTCx, uint32_t tampPrivilege) +__STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef const *RTCx, uint32_t tampPrivilege) { UNUSED(RTCx); MODIFY_REG(TAMP->PRIVCR, TAMP_PRIVCR_TAMPPRIV, tampPrivilege); @@ -4642,7 +4642,7 @@ __STATIC_INLINE void LL_RTC_SetTampPrivilege(RTC_TypeDef *RTCx, uint32_t tampPri * @arg @ref LL_TAMP_PRIVILEGE_FULL_YES * @arg @ref LL_TAMP_PRIVILEGE_FULL_NO */ -__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->PRIVCR, TAMP_PRIVCR_TAMPPRIV); @@ -4661,7 +4661,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetTampPrivilege(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL * @retval None */ -__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef *RTCx, uint32_t bckupRegisterPrivilege) +__STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef const *RTCx, uint32_t bckupRegisterPrivilege) { UNUSED(RTCx); MODIFY_REG(TAMP->PRIVCR, (TAMP_PRIVCR_BKPWPRIV | TAMP_PRIVCR_BKPRWPRIV), bckupRegisterPrivilege); @@ -4678,7 +4678,7 @@ __STATIC_INLINE void LL_RTC_SetBackupRegisterPrivilege(RTC_TypeDef *RTCx, uint32 * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_2 * @arg @ref LL_RTC_PRIVILEGE_BKUP_ZONE_ALL */ -__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->PRIVCR, (TAMP_PRIVCR_BKPWPRIV | TAMP_PRIVCR_BKPRWPRIV)); @@ -4769,7 +4769,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetBackupRegisterPrivilege(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_BKP_DR31 * @retval None */ -__STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t startZone2, uint32_t startZone3) +__STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef const *RTCx, uint32_t startZone2, uint32_t startZone3) { UNUSED(RTCx); MODIFY_REG(TAMP->SMCR, (TAMP_SMCR_BKPRWDPROT_Msk | TAMP_SMCR_BKPWDPROT_Msk), (startZone2 << TAMP_SMCR_BKPRWDPROT_Pos) | (startZone3 << TAMP_SMCR_BKPWDPROT_Pos)); @@ -4784,7 +4784,7 @@ __STATIC_INLINE void LL_RTC_SetBackupRegProtection(RTC_TypeDef *RTCx, uint32_t s * @param RTCx RTC Instance * @retval Start zone 2 */ -__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->SMCR, TAMP_SMCR_BKPRWDPROT_Msk) >> TAMP_SMCR_BKPRWDPROT_Pos; @@ -4799,7 +4799,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone2(RTC_TypeDef *RT * @param RTCx RTC Instance * @retval Start zone 2 */ -__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBackupRegProtectionStartZone3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return READ_BIT(TAMP->SMCR, TAMP_SMCR_BKPWDPROT_Msk) >> TAMP_SMCR_BKPWDPROT_Pos; @@ -4914,7 +4914,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); } @@ -4925,7 +4925,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); } @@ -4936,7 +4936,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); } @@ -4947,7 +4947,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef const *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); } @@ -4958,7 +4958,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); @@ -4970,7 +4970,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); @@ -4982,7 +4982,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); @@ -4994,7 +4994,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); @@ -5006,7 +5006,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); @@ -5017,7 +5017,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); @@ -5028,7 +5028,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP4IE); @@ -5039,7 +5039,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP4IE); @@ -5051,7 +5051,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP5IE); @@ -5062,7 +5062,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP5IE); @@ -5074,7 +5074,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP6IE); @@ -5085,7 +5085,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP6IE); @@ -5097,7 +5097,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP7IE); @@ -5108,7 +5108,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP7IE); @@ -5120,7 +5120,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP8IE); @@ -5131,7 +5131,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP8IE); @@ -5143,7 +5143,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); @@ -5155,7 +5155,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP1IE); @@ -5167,7 +5167,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); @@ -5179,7 +5179,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP2IE); @@ -5191,7 +5191,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); @@ -5202,7 +5202,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); @@ -5214,7 +5214,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); @@ -5225,7 +5225,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); @@ -5237,7 +5237,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); @@ -5248,7 +5248,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); @@ -5260,7 +5260,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); @@ -5272,7 +5272,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); @@ -5284,7 +5284,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); @@ -5295,7 +5295,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP4IE) == (TAMP_IER_TAMP4IE)) ? 1U : 0U); @@ -5306,7 +5306,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP4(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP5IE) == (TAMP_IER_TAMP5IE)) ? 1U : 0U); @@ -5317,7 +5317,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP6IE) == (TAMP_IER_TAMP6IE)) ? 1U : 0U); @@ -5328,7 +5328,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP7IE) == (TAMP_IER_TAMP7IE)) ? 1U : 0U); @@ -5339,7 +5339,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP7(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP8IE) == (TAMP_IER_TAMP8IE)) ? 1U : 0U); @@ -5351,7 +5351,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP1IE) == (TAMP_IER_ITAMP1IE)) ? 1U : 0U); @@ -5363,7 +5363,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP2IE) == (TAMP_IER_ITAMP2IE)) ? 1U : 0U); @@ -5375,7 +5375,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); @@ -5387,7 +5387,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); @@ -5399,7 +5399,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); @@ -5412,7 +5412,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None. */ -__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef const *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->COUNTR, 0u); @@ -5424,7 +5424,7 @@ __STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Monotonic counter value. */ -__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef const *RTCx) { UNUSED(RTCx); return READ_REG(TAMP->COUNTR); @@ -5436,7 +5436,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableTemperatureMonitoring(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableTemperatureMonitoring(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN); @@ -5448,7 +5448,7 @@ __STATIC_INLINE void LL_RTC_EnableTemperatureMonitoring(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableTemperatureMonitoring(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableTemperatureMonitoring(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_TMONEN); @@ -5460,7 +5460,7 @@ __STATIC_INLINE void LL_RTC_DisableTemperatureMonitoring(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableVoltageMonitoring(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableVoltageMonitoring(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN); @@ -5472,7 +5472,7 @@ __STATIC_INLINE void LL_RTC_EnableVoltageMonitoring(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableVoltageMonitoring(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableVoltageMonitoring(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_VMONEN); @@ -5484,7 +5484,7 @@ __STATIC_INLINE void LL_RTC_DisableVoltageMonitoring(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableWUTMonitoring(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableWUTMonitoring(RTC_TypeDef const *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN); @@ -5496,7 +5496,7 @@ __STATIC_INLINE void LL_RTC_EnableWUTMonitoring(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableWUTMonitoring(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableWUTMonitoring(RTC_TypeDef const *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->CFGR, TAMP_CFGR_WUTMONEN); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h index 47df027b8d..f5428428e4 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_sdmmc.h @@ -61,10 +61,10 @@ typedef struct uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller. This parameter can be a value between Min_Data = 0 and Max_Data = 1023 */ -#if (USE_SD_TRANSCEIVER != 0U) +#if (USE_SD_TRANSCEIVER != 0U) || (USE_SDIO_TRANSCEIVER != 0U) uint32_t TranceiverPresent; /*!< Specifies if there is a 1V8 Transceiver/Switcher. This parameter can be a value of @ref SDMMC_LL_TRANSCEIVER_PRESENT */ -#endif /* USE_SD_TRANSCEIVER */ +#endif /* USE_SD_TRANSCEIVER || USE_SDIO_TRANSCEIVER */ } SDMMC_InitTypeDef; @@ -160,84 +160,128 @@ typedef struct #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */ #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */ +/** + * @brief Masks for R5 Response + */ +/** this is the reserved for future use in spec RFU */ +#define SDMMC_SDIO_R5_ERROR ((uint32_t)0x00000400U) +/** Out of range error */ +#define SDMMC_SDIO_R5_OUT_OF_RANGE ((uint32_t)0x00000100U) +/** Invalid function number */ +#define SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER ((uint32_t)0x00000200U) +/** General or an unknown error */ +#define SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00000800U) +/** SDIO Card current state + * 00=DIS (card not selected) + * 01=CMD (data line free) + * 10=TRN (transfer on data lines) */ +#define SDMMC_SDIO_R5_IO_CURRENT_STATE ((uint32_t)0x00003000U) +/** Illegal command error */ +#define SDMMC_SDIO_R5_ILLEGAL_CMD ((uint32_t)0x00004000U) +/** CRC check of previous cmd failed */ +#define SDMMC_SDIO_R5_COM_CRC_FAILED ((uint32_t)0x00008000U) + +#define SDMMC_SDIO_R5_ERRORBITS (SDMMC_SDIO_R5_COM_CRC_FAILED | \ + SDMMC_SDIO_R5_ILLEGAL_CMD | \ + SDMMC_SDIO_R5_GENERAL_UNKNOWN_ERROR | \ + SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER | \ + SDMMC_SDIO_R5_OUT_OF_RANGE) +/** + * @brief SDIO_CMD53_MODE + */ +#define SDMMC_SDIO_MODE_BYTE 0x00U /*!< Byte Mode */ +#define SDMMC_SDIO_MODE_BLOCK 0x01U /*!< Block Mode */ + +/** + * @brief SDIO_CMD53_OP_CODE + */ +#define SDMMC_SDIO_NO_INC 0x00U /*!< No auto indentation */ +#define SDMMC_SDIO_AUTO_INC 0x01U /*!< Auto indentation */ + +/** + * @brief SDIO_CMD53_RAW + */ +#define SDMMC_SDIO_WO 0x00U /*!< Write only Flag */ +#define SDMMC_SDIO_RAW 0x01U /*!< Read after write Flag */ + /** * @brief SDMMC Commands Index */ -#define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */ -#define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */ -#define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ -#define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */ -#define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */ -#define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ -#define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ -#define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ -#define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ -#define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ -#define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ -#define SDMMC_CMD_VOLTAGE_SWITCH ((uint8_t)11U) /*!< SD card Voltage switch to 1.8V mode. */ -#define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */ -#define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */ -#define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */ -#define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */ -#define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ +#define SDMMC_CMD_GO_IDLE_STATE 0U /*!< Resets the SD memory card. */ +#define SDMMC_CMD_SEND_OP_COND 1U /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDMMC_CMD_ALL_SEND_CID 2U /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDMMC_CMD_SET_REL_ADDR 3U /*!< Asks the card to publish a new relative address (RCA). */ +#define SDMMC_CMD_SET_DSR 4U /*!< Programs the DSR of all cards. */ +#define SDMMC_CMD_SDMMC_SEN_OP_COND 5U /*!< Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line.*/ +#define SDMMC_CMD_HS_SWITCH 6U /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDMMC_CMD_SEL_DESEL_CARD 7U /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDMMC_CMD_HS_SEND_EXT_CSD 8U /*!< Sends SD Memory Card interface condition, which includes host supply voltage information and asks the card whether card supports voltage. */ +#define SDMMC_CMD_SEND_CSD 9U /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDMMC_CMD_SEND_CID 10U /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDMMC_CMD_VOLTAGE_SWITCH 11U /*!< SD card Voltage switch to 1.8V mode. */ +#define SDMMC_CMD_STOP_TRANSMISSION 12U /*!< Forces the card to stop transmission. */ +#define SDMMC_CMD_SEND_STATUS 13U /*!< Addressed card sends its status register. */ +#define SDMMC_CMD_HS_BUSTEST_READ 14U /*!< Reserved */ +#define SDMMC_CMD_GO_INACTIVE_STATE 15U /*!< Sends an addressed card into the inactive state. */ +#define SDMMC_CMD_SET_BLOCKLEN 16U /*!< Sets the block length (in bytes for SDSC) for all following block commands (read, write, lock). Default block length is fixed to 512 Bytes. Not effective */ /*!< for SDHS and SDXC. */ -#define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ -#define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ -#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */ -#define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */ -#define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ -#define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ -#define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */ -#define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */ -#define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */ -#define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */ -#define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */ -#define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ -#define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ -#define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ -#define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */ -#define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */ -#define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ -#define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ -#define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ -#define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */ +#define SDMMC_CMD_READ_SINGLE_BLOCK 17U /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_READ_MULT_BLOCK 18U /*!< Continuously transfers data blocks from card to host until interrupted by STOP_TRANSMISSION command. */ +#define SDMMC_CMD_HS_BUSTEST_WRITE 19U /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDMMC_CMD_WRITE_DAT_UNTIL_STOP 20U /*!< Speed class control command. */ +#define SDMMC_CMD_SET_BLOCK_COUNT 23U /*!< Specify block count for CMD18 and CMD25. */ +#define SDMMC_CMD_WRITE_SINGLE_BLOCK 24U /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed 512 bytes in case of SDHC and SDXC. */ +#define SDMMC_CMD_WRITE_MULT_BLOCK 25U /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDMMC_CMD_PROG_CID 26U /*!< Reserved for manufacturers. */ +#define SDMMC_CMD_PROG_CSD 27U /*!< Programming of the programmable bits of the CSD. */ +#define SDMMC_CMD_SET_WRITE_PROT 28U /*!< Sets the write protection bit of the addressed group. */ +#define SDMMC_CMD_CLR_WRITE_PROT 29U /*!< Clears the write protection bit of the addressed group. */ +#define SDMMC_CMD_SEND_WRITE_PROT 30U /*!< Asks the card to send the status of the write protection bits. */ +#define SDMMC_CMD_SD_ERASE_GRP_START 32U /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDMMC_CMD_SD_ERASE_GRP_END 33U /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDMMC_CMD_ERASE_GRP_START 35U /*!< Sets the address of the first write block to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE_GRP_END 36U /*!< Sets the address of the last write block of the continuous range to be erased. Reserved for each command system set by switch function command (CMD6). */ +#define SDMMC_CMD_ERASE 38U /*!< Reserved for SD security applications. */ +#define SDMMC_CMD_FAST_IO 39U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_GO_IRQ_STATE 40U /*!< SD card doesn't support it (Reserved). */ +#define SDMMC_CMD_LOCK_UNLOCK 42U /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by the SET_BLOCK_LEN command. */ +#define SDMMC_CMD_APP_CMD 55U /*!< Indicates to the card that the next command is an application specific command rather than a standard command. */ +#define SDMMC_CMD_GEN_CMD 56U /*!< Used either to transfer a data block to the card or to get a data block from the card for general purpose/application specific commands. */ +#define SDMMC_CMD_NO_CMD 64U /*!< No command */ /** * @brief Following commands are SD Card Specific commands. * SDMMC_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ -#define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */ -#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ -#define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ -#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ -#define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */ -#define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */ -#define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_APP_SD_SET_BUSWIDTH 6U /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus widths are given in SCR register. */ +#define SDMMC_CMD_SD_APP_STATUS 13U /*!< (ACMD13) Sends the SD status. */ +#define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS 22U /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 32bit+CRC data block. */ +#define SDMMC_CMD_SD_APP_OP_COND 41U /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT 42U /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDMMC_CMD_SD_APP_SEND_SCR 51U /*!< Reads the SD Configuration Register (SCR). */ +#define SDMMC_CMD_SDMMC_RW_DIRECT 52U /*!< For SD I/O card only, reserved for security specification. */ +#define SDMMC_CMD_SDMMC_RW_EXTENDED 53U /*!< For SD I/O card only, reserved for security specification. */ /** * @brief Following commands are MMC Specific commands. */ -#define SDMMC_CMD_MMC_SLEEP_AWAKE ((uint8_t)5U) /*!< Toggle the device between Sleep state and Standby state. */ +#define SDMMC_CMD_MMC_SLEEP_AWAKE 5U /*!< Toggle the device between Sleep state and Standby state. */ /** * @brief Following commands are SD Card Specific security commands. * SDMMC_CMD_APP_CMD should be sent before sending these commands. */ -#define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U) -#define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U) -#define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U) -#define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U) -#define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U) -#define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U) -#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U) -#define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U) -#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U) -#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U) +#define SDMMC_CMD_SD_APP_GET_MKB 43U +#define SDMMC_CMD_SD_APP_GET_MID 44U +#define SDMMC_CMD_SD_APP_SET_CER_RN1 45U +#define SDMMC_CMD_SD_APP_GET_CER_RN2 46U +#define SDMMC_CMD_SD_APP_SET_CER_RES2 47U +#define SDMMC_CMD_SD_APP_GET_CER_RES1 48U +#define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK 18U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK 25U +#define SDMMC_CMD_SD_APP_SECURE_ERASE 38U +#define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA 49U +#define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB 48U /** * @brief Masks for errors Card Status R1 (OCR Register) @@ -291,12 +335,12 @@ typedef struct #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U) #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U) -#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (ms) */ +#ifndef SDMMC_DATATIMEOUT /*Hardware Data Timeout (cycles) */ #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_DATATIMEOUT */ #ifndef SDMMC_SWDATATIMEOUT /*Software Data Timeout (ms) */ -#define SDMMC_SWDATATIMEOUT SDMMC_DATATIMEOUT +#define SDMMC_SWDATATIMEOUT ((uint32_t)0xFFFFFFFFU) #endif /* SDMMC_SWDATATIMEOUT */ #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU) @@ -666,6 +710,82 @@ typedef struct * @} */ +/** @defgroup SDMMC_SDIO_CCCR_Registers + * @{ + */ +/*-------------------------------- CCCR0 ----------------------------------*/ +#define SDMMC_SDIO_CCCR0 0x000U /*!< SDIOS Card Common Control Register 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE0 0x000U /*!< SDIOS Card Common Control Register 0 Byte 0 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE1 0x001U /*!< SDIOS Card Common Control Register 0 Byte 1 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE2 0x002U /*!< SDIOS Card Common Control Register 0 Byte 2 */ +#define SDMMC_SDIO_CCCR0_SD_BYTE3 0x003U /*!< SDIOS Card Common Control Register 0 Byte 3 */ + +/*-------------------------------- CCCR4 ----------------------------------*/ +#define SDMMC_SDIO_CCCR4 0x004U /*!< SDIOS Card Common Control Register 4 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE0 0x004U /*!< SDIOS Card Common Control Register 4 Byte 0 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE1 0x005U /*!< SDIOS Card Common Control Register 4 Byte 1 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE2 0x006U /*!< SDIOS Card Common Control Register 4 Byte 2 */ +#define SDMMC_SDIO_CCCR4_SD_BYTE3 0x007U /*!< SDIOS Card Common Control Register 4 Byte 3 */ + +/*-------------------------------- CCCR8 ----------------------------------*/ +#define SDMMC_SDIO_CCCR8 0x008U /*!< SDIOS Card Common Control Register 8 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE0 0x008U /*!< SDIOS Card Common Control Register 8 Byte 0 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE1 0x009U /*!< SDIOS Card Common Control Register 8 Byte 1 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE2 0x00AU /*!< SDIOS Card Common Control Register 8 Byte 2 */ +#define SDMMC_SDIO_CCCR8_SD_BYTE3 0x00BU /*!< SDIOS Card Common Control Register 8 Byte 3 */ + +/*-------------------------------- CCCR12 ---------------------------------*/ +#define SDMMC_SDIO_CCCR12 0x00CU /*!< SDIOS Card Common Control Register 12 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE0 0x00CU /*!< SDIOS Card Common Control Register 12 Byte 0 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE1 0x00DU /*!< SDIOS Card Common Control Register 12 Byte 1 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE2 0x00EU /*!< SDIOS Card Common Control Register 12 Byte 2 */ +#define SDMMC_SDIO_CCCR12_SD_BYTE3 0x00FU /*!< SDIOS Card Common Control Register 12 Byte 3 */ + +/*-------------------------------- CCCR16 ---------------------------------*/ +#define SDMMC_SDIO_CCCR16 0x010U /*!< SDIOS Card Common Control Register 16 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE0 0x010U /*!< SDIOS Card Common Control Register 16 Byte 0 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE1 0x011U /*!< SDIOS Card Common Control Register 16 Byte 1 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE2 0x012U /*!< SDIOS Card Common Control Register 16 Byte 2 */ +#define SDMMC_SDIO_CCCR16_SD_BYTE3 0x013U /*!< SDIOS Card Common Control Register 16 Byte 3 */ + +/*-------------------------------- CCCR20 ---------------------------------*/ +#define SDMMC_SDIO_CCCR20 0x014U /*!< SDIOS Card Common Control Register 20 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE0 0x014U /*!< SDIOS Card Common Control Register 20 Byte 0 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE1 0x015U /*!< SDIOS Card Common Control Register 20 Byte 1 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE2 0x016U /*!< SDIOS Card Common Control Register 20 Byte 2 */ +#define SDMMC_SDIO_CCCR20_SD_BYTE3 0x017U /*!< SDIOS Card Common Control Register 20 Byte 3 */ + +/*-------------------------------- F1BR0 ----------------------------------*/ +#define SDMMC_SDIO_F1BR0 0x100U /*!< SDIOS Function 1 Basic Register 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE0 0x100U /*!< SDIOS Function 1 Basic Register 0 Byte 0 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE1 0x101U /*!< SDIOS Function 1 Basic Register 0 Byte 1 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE2 0x102U /*!< SDIOS Function 1 Basic Register 0 Byte 2 */ +#define SDMMC_SDIO_F1BR0_SD_BYTE3 0x103U /*!< SDIOS Function 1 Basic Register 0 Byte 3 */ + +/*-------------------------------- F1BR8 ----------------------------------*/ +#define SDMMC_SDIO_F1BR8 0x108U /*!< SDIOS Function 1 Basic Register 8 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE0 0x108U /*!< SDIOS Function 1 Basic Register 8 Byte 0 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE1 0x109U /*!< SDIOS Function 1 Basic Register 8 Byte 1 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE2 0x10AU /*!< SDIOS Function 1 Basic Register 8 Byte 2 */ +#define SDMMC_SDIO_F1BR8_SD_BYTE3 0x10BU /*!< SDIOS Function 1 Basic Register 8 Byte 3 */ + +/*-------------------------------- F1BR12 ---------------------------------*/ +#define SDMMC_SDIO_F1BR12 0x10CU /*!< SDIOS Function 1 Basic Register 12 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE0 0x10CU /*!< SDIOS Function 1 Basic Register 12 Byte 0 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE1 0x10DU /*!< SDIOS Function 1 Basic Register 12 Byte 1 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE2 0x10EU /*!< SDIOS Function 1 Basic Register 12 Byte 2 */ +#define SDMMC_SDIO_F1BR12_SD_BYTE3 0x10FU /*!< SDIOS Function 1 Basic Register 12 Byte 3 */ + +/*-------------------------------- F1BR16 ---------------------------------*/ +#define SDMMC_SDIO_F1BR16 0x110U /*!< SDIOS Function 1 Basic Register 16 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE0 0x110U /*!< SDIOS Function 1 Basic Register 16 Byte 0 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE1 0x111U /*!< SDIOS Function 1 Basic Register 16 Byte 1 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE2 0x112U /*!< SDIOS Function 1 Basic Register 16 Byte 2 */ +#define SDMMC_SDIO_F1BR16_SD_BYTE3 0x113U /*!< SDIOS Function 1 Basic Register 16 Byte 3 */ +/** + * @} + */ + /** * @} */ @@ -880,6 +1000,38 @@ typedef struct */ #define __SDMMC_GET_IT(__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__)) +/** + * @brief Checks the source of specified interrupt. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. + * This parameter can be one of the following values: + * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt + * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt + * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt + * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt + * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt + * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt + * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt + * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt + * @arg SDMMC_IT_DATAEND: Data end (data counter, DATACOUNT, is zero) interrupt + * @arg SDMMC_IT_DHOLD: Data transfer Hold interrupt + * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt + * @arg SDMMC_IT_DABORT: Data transfer aborted by CMD12 interrupt + * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt + * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt + * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt + * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt + * @arg SDMMC_IT_BUSYD0END: End of SDMMC_D0 Busy following a CMD response detected interrupt + * @arg SDMMC_IT_SDIOIT: SDIO interrupt received interrupt + * @arg SDMMC_IT_ACKFAIL: Boot Acknowledgment received interrupt + * @arg SDMMC_IT_ACKTIMEOUT: Boot Acknowledgment timeout interrupt + * @arg SDMMC_IT_VSWEND: Voltage switch critical timing section completion interrupt + * @arg SDMMC_IT_CKSTOP: SDMMC_CK stopped in Voltage switch procedure interrupt + * @arg SDMMC_IT_IDMABTC: IDMA buffer transfer complete interrupt + * @retval The new state of SDMMC_IT (SET or RESET). + */ +#define __SDMMC_GET_IT_SOURCE(__INSTANCE__, __INTERRUPT__) (((__HANDLE__)->Instance->STA & (__INTERRUPT__))) + /** * @brief Clears the SDMMC's interrupt pending bits. * @param __INSTANCE__ Pointer to SDMMC register base @@ -1034,12 +1186,12 @@ HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx); /* Command path state machine (CPSM) management functions */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command); +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command); uint8_t SDMMC_GetCommandResponse(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response); /* Data path state machine (DPSM) management functions */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data); +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data); uint32_t SDMMC_GetDataCounter(const SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetFIFOCount(const SDMMC_TypeDef *SDMMCx); @@ -1083,6 +1235,9 @@ uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument); uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse); +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument); +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp); /** * @} */ @@ -1094,6 +1249,8 @@ uint32_t SDMMC_CmdBlockCount(SDMMC_TypeDef *SDMMCx, uint32_t BlockCount); uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout); uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx); uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx); +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp); +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData); uint32_t SDMMC_GetCmdResp6(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint16_t *pRCA); uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx); /** diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_spi.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_spi.h index 16ae583983..7b3cf14ad2 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_spi.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h index 2727a43bac..a52623a84c 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_ucpd.h @@ -847,7 +847,7 @@ __STATIC_INLINE void LL_UCPD_EnableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Enable Rx hard resrt interrupt + * @brief Enable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_EnableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1012,7 +1012,7 @@ __STATIC_INLINE void LL_UCPD_DisableIT_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Disable Rx hard resrt interrupt + * @brief Disable Rx hard reset interrupt * @rmtoll IMR RXHRSTDETIE LL_UCPD_DisableIT_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1177,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsEnableIT_RxOvr(UCPD_TypeDef const *const UCPD } /** - * @brief Check if Rx hard resrt interrupt enabled + * @brief Check if Rx hard reset interrupt enabled * @rmtoll IMR RXHRSTDETIE LL_UCPD_IsEnableIT_RxHRST * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1350,7 +1350,7 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_RxOvr(UCPD_TypeDef *UCPDx) } /** - * @brief Clear Rx hard resrt interrupt + * @brief Clear Rx hard reset interrupt * @rmtoll ICR RXHRSTDETIE LL_UCPD_ClearFlag_RxHRST * @param UCPDx UCPD Instance * @retval None @@ -1446,10 +1446,10 @@ __STATIC_INLINE void LL_UCPD_ClearFlag_TxMSGDISC(UCPD_TypeDef *UCPDx) */ /** - * @brief Check if FRS interrupt + * @brief Check if FRS Event Flag is active * @rmtoll SR FRSEVT LL_UCPD_IsActiveFlag_FRS * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPDx) { @@ -1460,7 +1460,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_FRS(UCPD_TypeDef const *const UCPD * @brief Check if type c event on CC2 * @rmtoll SR TYPECEVT2 LL_UCPD_IsActiveFlag_TypeCEventCC2 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const *const UCPDx) { @@ -1471,7 +1471,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC2(UCPD_TypeDef const * * @brief Check if type c event on CC1 * @rmtoll SR TYPECEVT1 LL_UCPD_IsActiveFlag_TypeCEventCC1 * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const *const UCPDx) { @@ -1479,10 +1479,21 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TypeCEventCC1(UCPD_TypeDef const * } /** - * @brief Check if Rx message end interrupt + * @brief Check if Rx error flag is active + * @rmtoll SR RXERR LL_UCPD_IsActiveFlag_RxErr + * @param UCPDx UCPD Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxErr(UCPD_TypeDef const *const UCPDx) +{ + return ((READ_BIT(UCPDx->SR, UCPD_SR_RXERR) == UCPD_SR_RXERR) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx message end flag is active * @rmtoll SR RXMSGEND LL_UCPD_IsActiveFlag_RxMsgEnd * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const UCPDx) { @@ -1490,10 +1501,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxMsgEnd(UCPD_TypeDef const *const } /** - * @brief Check if Rx overrun interrupt + * @brief Check if Rx overrun flag is active * @rmtoll SR RXOVR LL_UCPD_IsActiveFlag_RxOvr * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UCPDx) { @@ -1501,10 +1512,10 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOvr(UCPD_TypeDef const *const UC } /** - * @brief Check if Rx hard resrt interrupt + * @brief Check if Rx hard reset flag is active * @rmtoll SR RXHRSTDET LL_UCPD_IsActiveFlag_RxHRST * @param UCPDx UCPD Instance - * @retval None + * @retval State of bit (1 or 0). */ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const UCPDx) { @@ -1512,7 +1523,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxHRST(UCPD_TypeDef const *const U } /** - * @brief Check if Rx orderset interrupt + * @brief Check if Rx orderset flag is active * @rmtoll SR RXORDDET LL_UCPD_IsActiveFlag_RxOrderSet * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1523,7 +1534,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxOrderSet(UCPD_TypeDef const *con } /** - * @brief Check if Rx non empty interrupt + * @brief Check if Rx non empty flag is active * @rmtoll SR RXNE LL_UCPD_IsActiveFlag_RxNE * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1534,7 +1545,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_RxNE(UCPD_TypeDef const *const UCP } /** - * @brief Check if TX underrun interrupt + * @brief Check if TX underrun flag is active * @rmtoll SR TXUND LL_UCPD_IsActiveFlag_TxUND * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1545,7 +1556,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxUND(UCPD_TypeDef const *const UC } /** - * @brief Check if hard reset sent interrupt + * @brief Check if hard reset sent flag is active * @rmtoll SR HRSTSENT LL_UCPD_IsActiveFlag_TxHRSTSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1556,7 +1567,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTSENT(UCPD_TypeDef const *con } /** - * @brief Check if hard reset discard interrupt + * @brief Check if hard reset discard flag is active * @rmtoll SR HRSTDISC LL_UCPD_IsActiveFlag_TxHRSTDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1567,7 +1578,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxHRSTDISC(UCPD_TypeDef const *con } /** - * @brief Check if Tx message abort interrupt + * @brief Check if Tx message abort flag is active * @rmtoll SR TXMSGABT LL_UCPD_IsActiveFlag_TxMSGABT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1578,7 +1589,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGABT(UCPD_TypeDef const *const } /** - * @brief Check if Tx message sent interrupt + * @brief Check if Tx message sent flag is active * @rmtoll SR TXMSGSENT LL_UCPD_IsActiveFlag_TxMSGSENT * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1589,7 +1600,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGSENT(UCPD_TypeDef const *cons } /** - * @brief Check if Tx message discarded interrupt + * @brief Check if Tx message discarded flag is active * @rmtoll SR TXMSGDISC LL_UCPD_IsActiveFlag_TxMSGDISC * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). @@ -1600,7 +1611,7 @@ __STATIC_INLINE uint32_t LL_UCPD_IsActiveFlag_TxMSGDISC(UCPD_TypeDef const *cons } /** - * @brief Check if Tx data receive interrupt + * @brief Check if Tx data interrupt flag is active * @rmtoll SR TXIS LL_UCPD_IsActiveFlag_TxIS * @param UCPDx UCPD Instance * @retval State of bit (1 or 0). diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h index 8d5bdcc2fc..1b44e20e2e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usart.h @@ -56,6 +56,10 @@ static const uint32_t USART_PRESCALER_TAB[] = 32UL, 64UL, 128UL, + 256UL, + 256UL, + 256UL, + 256UL, 256UL }; /** diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h index 0d44bc08cd..3cbc332423 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h +++ b/system/Drivers/STM32L5xx_HAL_Driver/Inc/stm32l5xx_ll_usb.h @@ -75,6 +75,7 @@ typedef struct uint8_t battery_charging_enable; /*!< Enable or disable Battery charging. */ } USB_CfgTypeDef; +#if defined (HAL_PCD_MODULE_ENABLED) typedef struct { uint8_t num; /*!< Endpoint number @@ -119,6 +120,7 @@ typedef struct uint8_t xfer_fill_db; /*!< double buffer Need to Fill new buffer used with bulk_in */ } USB_EPTypeDef; +#endif /* defined (HAL_PCD_MODULE_ENABLED) */ /* Exported constants --------------------------------------------------------*/ @@ -161,7 +163,7 @@ typedef struct #define PMA_ACCESS 1U #ifndef USB_EP_RX_STRX -#define USB_EP_RX_STRX (0x3U << 12) +#define USB_EP_RX_STRX (0x3UL << 12) #endif /* USB_EP_RX_STRX */ #define EP_ADDR_MSK 0x7U @@ -186,11 +188,11 @@ typedef struct */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_DevInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg); HAL_StatusTypeDef USB_EnableGlobalInt(USB_TypeDef *USBx); HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx); -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode); +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode); HAL_StatusTypeDef USB_FlushRxFifo(USB_TypeDef const *USBx); HAL_StatusTypeDef USB_FlushTxFifo(USB_TypeDef const *USBx, uint32_t num); @@ -239,5 +241,4 @@ void USB_ReadPMA(USB_TypeDef const *USBx, uint8_t *pbUsrBuf, } #endif /* __cplusplus */ - #endif /* STM32L5xx_LL_USB_H */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/README.md b/system/Drivers/STM32L5xx_HAL_Driver/README.md index 14c194ad4e..c97b28efea 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/README.md +++ b/system/Drivers/STM32L5xx_HAL_Driver/README.md @@ -1,21 +1,21 @@ # STM32CubeL5 HAL Driver MCU Component -![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32l5xx_hal_driver.svg?color=brightgreen) +![latest tag](https://img.shields.io/github/v/tag/STMicroelectronics/stm32l5xx-hal-driver.svg?color=brightgreen) -## Overview +## Overview of the STM32Cube MCU offer on GitHub -**STM32Cube** is an STMicroelectronics original initiative to ease developers' life by reducing efforts, time and cost. +**STM32Cube** is an original initiative by STMicroelectronics to **simplify** prototyping and development by **reducing** effort, time, and cost. It supports the entire ARM™ Cortex-based STM32 microcontroller portfolio and provides a **comprehensive** software solution including: + * The CMSIS Core and Device interfaces enabling access to processor core features and device-specific peripherals of STM32 microcontrollers. + * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. + * The BSP drivers enabling access to peripherals on the STM32 development boards, external to the microcontroller itself. + * A consistent set of middleware libraries offering standardized, high-level functionalities — such as USB, TCP/IP, file systems, and graphics. + * A full set of software projects (basic examples, applications, and demonstrations) that showcase specific functionalities or use cases, and provided with support for multiple IDEs. -**STM32Cube** covers the overall STM32 products portfolio. It includes a comprehensive embedded software platform delivered for each STM32 series. - * The CMSIS modules (core and device) corresponding to the ARM(tm) core implemented in this STM32 product. - * The STM32 HAL-LL drivers, an abstraction layer offering a set of APIs ensuring maximized portability across the STM32 portfolio. - * The BSP drivers of each evaluation, demonstration or nucleo board provided for this STM32 series. - * A consistent set of middleware libraries such as RTOS, USB, FatFS, graphics, touch sensing library... - * A full set of software projects (basic examples, applications, and demonstrations) for each board provided for this STM32 series. +The **STM32Cube embedded software** is available in two flavors: + * The **MCU Firmware** _monolithic_ offer, where **all** software components (Drivers, Middleware, Projects, Utilities) are included in a **single** repository for each STM32 series. + * The **MCU Software Components** _modular_ offer, where **each** software component (mainly Drivers and Middleware) is provided in a **dedicated** repository, allowing users to **select** only the components they need. -Two models of publication are proposed for the STM32Cube embedded software: - * The monolithic **MCU Package**: all STM32Cube software modules of one STM32 series are present (Drivers, Middleware, Projects, Utilities) in the repository (usual name **STM32Cubexx**, xx corresponding to the STM32 series). - * The **MCU component**: each STM32Cube software module being part of the STM32Cube MCU Package, is delivered as an individual repository, allowing the user to select and get only the required software functions. +The complete list of repositories is available [here](https://github.com/STMicroelectronics/STM32Cube_MCU_Overall_Offer/blob/master/README.md#content). ## Description @@ -23,16 +23,12 @@ This **stm32l5xx_hal_driver** MCU component repo is one element of the STM32Cube ## Release note -Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32l5xx_hal_driver/blob/master/Release_Notes.html). +Details about the content of this release are available in the release note [here](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/stm32l5xx-hal-driver/blob/master/Release_Notes.html). ## Compatibility information It is **crucial** that you use a consistent set of versions for the CMSIS Core - CMSIS Device - HAL, as mentioned in [this](https://htmlpreview.github.io/?https://github.com/STMicroelectronics/STM32CubeL5/blob/master/Release_Notes.html) release note. -The full **STM32CubeL5** MCU package is available [here](https://github.com/STMicroelectronics/STM32CubeL5). +## Feedback and contributions -## Troubleshooting - -If you have any issue with the **software content** of this repository, you can file an issue [here](https://github.com/STMicroelectronics/stm32l5xx_hal_driver/issues/new/choose). - -For any other question related to the product, the tools, the environment, you can submit a topic on the [ST Community/STM32 MCUs forum](https://community.st.com/s/group/0F90X000000AXsASAW/stm32-mcus). +Please refer to the [CONTRIBUTING.md](CONTRIBUTING.md) guide. \ No newline at end of file diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html index 3ab30419f2..85ef7ad373 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32L5xx_HAL_Driver/Release_Notes.html @@ -41,7 +41,7 @@

Purpose

Update History

- +

Main Changes

Maintenance release

@@ -51,6 +51,129 @@

Contents

HAL Drivers updates

    +
  • HAL ADC +
      +
    • Correct length parameter definition in HAL_ADCEx_MultiModeStart_DMA() API.
      • +
    • +
  • HAL CRC +
      +
    • Replace successive ‘if’ statements by ‘else if’ to improve checksum calculation performance in CRC_Handle_8() static function.
      • +
    • +
  • HAL DAC +
      +
    • Update HAL_DACEx_SelfCalibrate() API to handle calibration factor equal to the range maximum value.
      • +
    • +
  • HAL CRYP +
      +
    • Remove __HAL_UNLOCK() invocation when __HAL_LOCK() is not present.
      • +
    • Prevent reading outside the boundaries of local array for all data type.
      • +
    • +
  • HAL FDCAN +
      +
    • Fix assert issue when Standard or Extended filter numbers are zeros.
      • +
    • Fix GetIndex computation overflow in overwrite mode in HAL_FDCAN_GetRxMessage() API.
      • +
    • +
  • HAL GPIO +
      +
    • Add Pull down capability in analog mode.
      • +
    • +
  • HAL PWR +
      +
    • Add guidance for HAL_PWR_ConfigAttributes() API description.
      • +
    • +
  • HAL RCC +
      +
    • Add guidance for HAL_RCC_ConfigAttributes() API description.
      • +
    • +
  • HAL FLASH +
      +
    • Change timeout calculation method in FLASH_WaitForLastOperation() function for improved handling.
      • +
    • Update the description of FLASH_OB_UserConfig() function.
      • +
    • +
  • HAL HASH +
      +
    • Remove commented code section.
      • +
    • Enhance HASH_Start_IT() function to properly handle remaining data smaller than 4 bytes during the processing phase.
      • +
    • +
  • HAL Cortex +
      +
    • Add MPU attributes description.
      • +
    • +
  • HAL I2C +
      +
    • Move variable declaration at the beginning in I2C_TransferCofig() function.
      • +
    • Update HAL_I2C_IsDeviceReady() API to consider number of trials.
      • +
    • +
  • HAL SMBUS +
      +
    • Improve HAL_SMBUS_IsDeviceReady() API to better handle STOP flag timing issues by allowing automatic retries and improved error recovery.
      • +
    • +
  • HAL NAND +
      +
    • Correct buffer assignment to ensure proper volatile access improving data integrity and preventing compiler optimization issues.
      • +
    • Remove unused local variables.
      • +
    • +
  • HAL OSPI +
      +
    • Add new helper HAL_OSPI_IsMemoryMapped() API to verify whether memory-mapped mode is configured or not.
      • +
    • change ChipSelectHighTime max limits to 64 to feat with specification.
      • +
    • Keep BSY flag high at the end of data transfer in SPI_EndRxTransaction() static API.
      • +
    • +
  • HAL RNG +
      +
    • Distinguish errors from RecoverSeedError and SeedError.
      • +
    • Modify CR register configuration in HAL_RNG_Init() API to be compliant with NIST.
      • +
    • +
  • HAL SPI +
      +
    • Add note clarifying HAL_SPI_Receive() API behavior in master mode.
      • +
    • Add units to physical measurements.
      • +
    • Avoid buffer overflow in SPI_WaitFifoStateUntilTimeout() function.
      • +
    • Check data size before changing state in reception API.
      • +
    • Keep BSY bit high to the end of a data transfer.
      • +
    • +
  • HAL TIM +
      +
    • Fix update flag (UIF) clearing in TIM_Base_SetConfig() function.
      • +
    • Update TIM_CCER_CCxE_MASK to support internal TIM Channel 5 and 6.
      • +
    • Fix complementary channel being systematically disabled by TIM_OCx_SetConfig() function.
      • +
    • +
  • HAL UART +
      +
    • Report an Idle event (HAL_UART_RXEVENT_IDLE) during DMA Circular mode reception by invoking the appropriate Rx Event callback.
      • +
    • Align prescaler value used by default in UART_GET_DIV_FACTOR macro with reference manual.
      • +
    • Correct DMA Rx abort procedure impact on ongoing Tx transfer in polling mode in static function UART_DMAAbortOnError().
      • +
    • Correct references to HAL_UARTEx_WakeupCallback and to HAL_UART_WAKEUP_CB_ID define, according to serie capabilities
      • +
    • Correct wrong comment in HAL_UARTEx_DisableFifoMode() API.
      • +
    • Ensure UART Rx buffer is not written beyond boundaries during RX FIFO reception in Interrupt mode.
      • +
    • Improve Rx Event callback by reporting accurate position for remaining DMA transfers.
      • +
    • +
  • HAL USART +
      +
    • Align prescaler value used by default in USART_GET_DIV_FACTOR macro with reference manual.
      • +
    • Correct wrong comment in HAL_USARTEx_DisableFifoMode() API.
      • +
    • +
  • HAL USB +
      +
    • Fix security advisory SA0035.
      • +
    • +
+

Notes

+

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

+

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+
    +
  • General updates to fix known defects and implementation enhancements.
    • +
+

HAL Drivers updates

+
  • HAL code quality enhancement for MISRA-C2012 Rule-8.13 by adding const qualifiers.
  • HAL Generic
      @@ -197,7 +320,7 @@

      HAL Drivers updates

    • Update LL_InitTick() API documentation: update “Ticks” parameter description.
-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

@@ -205,14 +328,14 @@

Notes

-

Main Changes

+

Main Changes

Maintenance release

-

Contents

+

Contents

  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
-

HAL Drivers updates

+

HAL Drivers updates

  • HAL Generic
      @@ -410,7 +533,7 @@

      HAL Drivers updates

    • Update the way to declare licenses.
-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

@@ -418,12 +541,12 @@

Notes

-

Main Changes

+

Main Changes

Maintenance release

-

Contents

+

Contents

Maintenance release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices

Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)

-

HAL Drivers updates

+

HAL Drivers updates

  • HAL ADC driver
      @@ -572,7 +695,7 @@

      LL Drivers updates

    • Remove useless IS_LL_USART_BRR_MAX() macro
-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

@@ -580,12 +703,12 @@

Notes

-

Main Changes

+

Main Changes

Fourth release

-

Contents

+

Contents

Fourth release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices

Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)

-

HAL Drivers updates

+

HAL Drivers updates

  • Global removal of ‘register’ storage class qualifier deprecated since C++ 11
  • HAL generic driver @@ -699,7 +822,7 @@

    LL Drivers updates

  • Change default CFGR1 register values in LL_UCPD_StructInit()
-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

@@ -707,12 +830,12 @@

Notes

-

Main Changes

+

Main Changes

Third release

-

Contents

+

Contents

Third official release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices

Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)

-

HAL Drivers updates

+

HAL Drivers updates

  • HAL FLASH driver
      @@ -745,7 +868,7 @@

      LL Drivers updates

-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

Known Limitations

@@ -760,12 +883,12 @@

Known Limitations

-

Main Changes

+

Main Changes

Second release

-

Contents

+

Contents

Second official release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices

Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)

-

HAL Drivers updates

+

HAL Drivers updates

  • HAL FLASH driver
      @@ -824,7 +947,7 @@

      LL Drivers updates

    • Add LL_SetFlashLatency() API
-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

@@ -832,9 +955,9 @@

Notes

-

Main Changes

+

Main Changes

First release

-

Contents

+

Contents

First official release of HAL and Low Layer drivers for STM32L552xx/STM32L562xx devices

Superset features device STM32L562xx API User Manual available (STM32L562xx_User_Manual.chm)

HAL Drivers

@@ -846,7 +969,7 @@

LL Drivers

  • ADC, BUS, COMP, CORTEX, CRC, CRS, CRYP, DAC, DMA, DMAMUX, EXTI, GPIO, I2C, IWDG, LPTIM, LPUART, OPAMP, PKA, PWR, RCC, RNG, RTC, SDMMC, SPI, SYSTEM, TIM, UCPD, USART, UTILS, WWDG
-

Notes

+

Notes

For HAL drivers usage, stm32l5xx_hal_conf_template.h file must be copied in user application as stm32l5xx_hal_conf.h with optional configuration update.

For LL drivers usage, stm32_assert_template.h file must be copied in user application as stm32_assert.h with optional assert configuration update.

diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c index e2fc0fc0cb..d3070768f5 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal.c @@ -53,7 +53,7 @@ */ #define STM32L5XX_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */ #define STM32L5XX_HAL_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define STM32L5XX_HAL_VERSION_SUB2 (0x06U) /*!< [15:8] sub2 version */ +#define STM32L5XX_HAL_VERSION_SUB2 (0x07U) /*!< [15:8] sub2 version */ #define STM32L5XX_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */ #define STM32L5XX_HAL_VERSION ((STM32L5XX_HAL_VERSION_MAIN << 24U)\ |(STM32L5XX_HAL_VERSION_SUB1 << 16U)\ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_adc_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_adc_ex.c index 341e973885..a91764a94a 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_adc_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_adc_ex.c @@ -849,7 +849,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef *hadc) * conversions. * @param hadc ADC handle of ADC master (handle of ADC slave must not be used) * @param pData Destination Buffer address. - * @param Length Length of data to be transferred from ADC peripheral to memory (in bytes). + * @param Length Length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef *hadc, uint32_t *pData, uint32_t Length) diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c index 590a0a2e59..732b40277b 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cortex.c @@ -73,6 +73,24 @@ (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function (++) Reload Value should not exceed 0xFFFFFF + [..] + *** How to configure MPU regions using CORTEX HAL driver *** + ============================================================ + [..] + This section provides functions allowing to configure the Memory Protection Unit (MPU). + + (#) Disable the MPU using HAL_MPU_Disable(). + (#) Configure the necessary MPU memory attributes using HAL_MPU_ConfigMemoryAttributes(). + (#) Configure the necessary MPU regions using HAL_MPU_ConfigRegion() ennsuring that the MPU region configuration link to + the right MPU attributes number. + (#) Enable the MPU using HAL_MPU_Enable() function. + + -@- The memory management fault exception is enabled in HAL_MPU_Enable() function and the system will enter the memory + management fault handler MemManage_Handler() when an illegal memory access is performed. + -@- If the MPU has previously been programmed, disable the unused regions to prevent any previous region configuration + from affecting the new MPU configuration. + -@- MPU APIs ending with '_NS' allow to control the non-secure Memory Protection Unit (MPU_NS) from the secure context + @endverbatim ****************************************************************************** diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c index 58770ef64c..5dcbbd691c 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_crc.c @@ -452,13 +452,13 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ { *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[4U * i]; /* Derogation MisraC2012 R.11.5 */ } - if ((BufferLength % 4U) == 2U) + else if ((BufferLength % 4U) == 2U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ *pReg = data; } - if ((BufferLength % 4U) == 3U) + else if ((BufferLength % 4U) == 3U) { data = ((uint16_t)(pBuffer[4U * i]) << 8U) | (uint16_t)pBuffer[(4U * i) + 1U]; pReg = (__IO uint16_t *)(__IO void *)(&hcrc->Instance->DR); /* Derogation MisraC2012 R.11.5 */ @@ -466,6 +466,10 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_ *(__IO uint8_t *)(__IO void *)(&hcrc->Instance->DR) = pBuffer[(4U * i) + 2U]; /* Derogation MisraC2012 R.11.5 */ } + else + { + /* Nothing to do */ + } } /* Return the CRC computed value */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c index daa48ef5b5..e16da4b262 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp.c @@ -629,9 +629,6 @@ HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD } else { - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Busy error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; return HAL_ERROR; @@ -685,9 +682,6 @@ HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeD } else { - /* Process Unlocked */ - __HAL_UNLOCK(hcryp); - /* Busy error code field */ hcryp->ErrorCode |= HAL_CRYP_ERROR_BUSY; return HAL_ERROR; @@ -2519,10 +2513,11 @@ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /* Stop the DMA transfers to the IN FIFO by clearing to "0" the DMAINEN */ CLEAR_BIT(hcryp->Instance->CR, AES_CR_DMAINEN); @@ -2628,7 +2623,7 @@ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) uint32_t count; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t mode; CRYP_HandleTypeDef *hcryp = (CRYP_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; @@ -2869,7 +2864,7 @@ static HAL_StatusTypeDef CRYP_SetHeaderDMAConfig(CRYP_HandleTypeDef *hcryp, uint static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t i; /* Write the input block in the IN FIFO */ @@ -2931,7 +2926,7 @@ static void CRYP_AES_ProcessData(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) */ static void CRYP_AES_IT(CRYP_HandleTypeDef *hcryp) { - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t i; if (hcryp->State == HAL_CRYP_STATE_BUSY) @@ -3085,7 +3080,7 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t tickstart; uint32_t wordsize = ((uint32_t)hcryp->Size / 4U) ; uint32_t npblb; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t index; uint32_t lastwordsize; uint32_t incount; /* Temporary CrypInCount Value */ @@ -3293,10 +3288,11 @@ static HAL_StatusTypeDef CRYP_AESGCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -3762,7 +3758,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process(CRYP_HandleTypeDef *hcryp, uint32_t uint32_t loopcounter; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4] ; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t incount; /* Temporary CrypInCount Value */ uint32_t outcount; /* Temporary CrypOutCount Value */ uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ @@ -3965,10 +3961,11 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_IT(CRYP_HandleTypeDef *hcryp) uint32_t DoKeyIVConfig = 1U; /* By default, carry out peripheral Key and IV configuration */ uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) if ((hcryp->Phase == CRYP_PHASE_HEADER_SUSPENDED) || (hcryp->Phase == CRYP_PHASE_PAYLOAD_SUSPENDED)) @@ -4418,7 +4415,7 @@ static HAL_StatusTypeDef CRYP_AESCCM_Process_DMA(CRYP_HandleTypeDef *hcryp) static void CRYP_GCMCCM_SetPayloadPhase_IT(CRYP_HandleTypeDef *hcryp) { uint32_t loopcounter; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t lastwordsize; uint32_t npblb; uint32_t mode; @@ -4576,7 +4573,7 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetPayloadPhase_DMA(CRYP_HandleTypeDef *hcr uint32_t index; uint32_t npblb; uint32_t lastwordsize; - uint32_t temp[4]; /* Temporary CrypOutBuff */ + uint32_t temp[4] = {0U}; /* Temporary CrypOutBuff */ uint32_t count; uint32_t reg; @@ -4709,10 +4706,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, u uint32_t loopcounter; uint32_t size_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4870,10 +4868,11 @@ static HAL_StatusTypeDef CRYP_GCMCCM_SetHeaderPhase_DMA(CRYP_HandleTypeDef *hcry uint32_t loopcounter; uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; /***************************** Header phase for GCM/GMAC or CCM *********************************/ if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) @@ -4993,10 +4992,11 @@ static void CRYP_GCMCCM_SetHeaderPhase_IT(CRYP_HandleTypeDef *hcryp) uint32_t mode; uint32_t headersize_in_bytes; uint32_t tmp; - static const uint32_t mask[12U] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ - 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ - 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU - }; /* 8-bit data type */ + const uint32_t mask[16] = {0x0U, 0xFF000000U, 0xFFFF0000U, 0xFFFFFF00U, /* 32-bit data type */ + 0x0U, 0x0000FF00U, 0x0000FFFFU, 0xFF00FFFFU, /* 16-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU, /* 8-bit data type */ + 0x0U, 0x000000FFU, 0x0000FFFFU, 0x00FFFFFFU /* 1-bit data type */ + }; if (hcryp->Init.HeaderWidthUnit == CRYP_HEADERWIDTHUNIT_WORD) { diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c index a4ef77d1b5..53d69528dd 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_cryp_ex.c @@ -95,7 +95,8 @@ * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout) { uint32_t tickstart; /* Assume first Init.HeaderSize is in words */ @@ -216,7 +217,8 @@ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, u * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout) +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, + uint32_t Timeout) { uint32_t tagaddr = (uint32_t)AuthTag; uint32_t tickstart; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c index de24089e54..569dafd575 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dac_ex.c @@ -666,8 +666,8 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo /* Init trimming counter */ /* Medium value */ - trimmingvalue = 16UL; - delta = 8UL; + trimmingvalue = 0x10UL; + delta = 0x08UL; while (delta != 0UL) { /* Set candidate trimming */ @@ -713,8 +713,12 @@ HAL_StatusTypeDef HAL_DACEx_SelfCalibrate(DAC_HandleTypeDef *hdac, DAC_ChannelCo if ((hdac->Instance->SR & (DAC_SR_CAL_FLAG1 << (Channel & 0x10UL))) == 0UL) { - /* Trimming is actually one value more */ - trimmingvalue++; + /* Check trimming value below maximum */ + if (trimmingvalue < 0x1FU) + { + /* Trimming is actually one value more */ + trimmingvalue++; + } /* Set right trimming */ MODIFY_REG(hdac->Instance->CCR, (DAC_CCR_OTRIM1 << (Channel & 0x10UL)), (trimmingvalue << (Channel & 0x10UL))); } @@ -787,8 +791,7 @@ HAL_StatusTypeDef HAL_DACEx_SetUserTrimming(DAC_HandleTypeDef *hdac, DAC_Channel * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @retval Trimming value : range: 0->31 - * + * @retval TrimmingValue Value between Min_Data=0x00 and Max_Data=0x1F */ uint32_t HAL_DACEx_GetTrimOffset(const DAC_HandleTypeDef *hdac, uint32_t Channel) { diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dma.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dma.c index cc4f9f2e02..fdf118e77d 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dma.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_dma.c @@ -879,7 +879,7 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma) * the configuration information for the specified DMA Channel. * @param CallbackID User Callback identifier * a HAL_DMA_CallbackIDTypeDef ENUM as parameter. - * @param pCallback pointer to private callbacsk function which has pointer to + * @param pCallback pointer to private callback function which has pointer to * a DMA_HandleTypeDef structure as parameter. * @retval HAL status */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c index 36a2216ad6..caf4a5051a 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_exti.c @@ -258,9 +258,9 @@ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param pExtiConfig Pointer on structure to store Exti configuration. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) +HAL_StatusTypeDef HAL_EXTI_GetConfigLine(const EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -352,7 +352,7 @@ HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigT * @param hexti Exti handle. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti) +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @param hexti Exti handle. * @retval none. */ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t regval; @@ -546,9 +546,9 @@ void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti) * @arg @ref EXTI_TRIGGER_FALLING * @retval 1 if interrupt is pending else 0. */ -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t regval; uint32_t linepos; uint32_t maskline; @@ -590,7 +590,7 @@ uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @arg @ref EXTI_TRIGGER_FALLING * @retval None. */ -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge) { __IO uint32_t *regaddr; uint32_t maskline; @@ -626,7 +626,7 @@ void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge) * @param hexti Exti handle. * @retval None. */ -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti) +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti) { __IO uint32_t *regaddr; uint32_t maskline; @@ -752,7 +752,7 @@ void HAL_EXTI_ConfigLineAttributes(uint32_t ExtiLine, uint32_t LineAttributes) */ HAL_StatusTypeDef HAL_EXTI_GetConfigLineAttributes(uint32_t ExtiLine, uint32_t *pLineAttributes) { - __IO uint32_t *regaddr; + const __IO uint32_t *regaddr; uint32_t linepos; uint32_t maskline; uint32_t offset; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c index 94f91bdb8c..9bdc8d71da 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_fdcan.c @@ -1302,7 +1302,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA if (sFilterConfig->IdType == FDCAN_STANDARD_ID) { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.StdFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.StdFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x7FFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x7FFU)); assert_param(IS_FDCAN_STD_FILTER_TYPE(sFilterConfig->FilterType)); @@ -1322,7 +1322,7 @@ HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, const FDCA else /* sFilterConfig->IdType == FDCAN_EXTENDED_ID */ { /* Check function parameters */ - assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterIndex, (hfdcan->Init.ExtFiltersNbr - 1U))); + assert_param(IS_FDCAN_MAX_VALUE((sFilterConfig->FilterIndex + 1U), hfdcan->Init.ExtFiltersNbr)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID1, 0x1FFFFFFFU)); assert_param(IS_FDCAN_MAX_VALUE(sFilterConfig->FilterID2, 0x1FFFFFFFU)); assert_param(IS_FDCAN_EXT_FILTER_TYPE(sFilterConfig->FilterType)); @@ -2217,7 +2217,7 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R uint32_t *RxAddress; uint8_t *pData; uint32_t ByteCounter; - uint32_t GetIndex = 0; + uint32_t GetIndex; HAL_FDCAN_StateTypeDef state = hfdcan->State; /* Check function parameters */ @@ -2237,19 +2237,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Calculate Rx FIFO 0 element index */ + GetIndex = ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); + /* Check that the Rx FIFO 0 is full & overwrite mode is on */ if (((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0F) >> FDCAN_RXF0S_F0F_Pos) == 1U) { if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F0OM) >> FDCAN_RXGFC_F0OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) { /* When overwrite status is on discard first message in FIFO */ - GetIndex = 1U; + /* GetIndex is incremented by one and wraps to 0 in case it overflows the FIFO size */ + GetIndex = (GetIndex + 1U) & SRAMCAN_RF0_NBR; } } - /* Calculate Rx FIFO 0 element index */ - GetIndex += ((hfdcan->Instance->RXF0S & FDCAN_RXF0S_F0GI) >> FDCAN_RXF0S_F0GI_Pos); - /* Calculate Rx FIFO 0 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO0SA + (GetIndex * SRAMCAN_RF0_SIZE)); } @@ -2266,18 +2267,20 @@ HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t R } else { + /* Calculate Rx FIFO 1 element index */ + GetIndex = ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); + /* Check that the Rx FIFO 1 is full & overwrite mode is on */ if (((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1F) >> FDCAN_RXF1S_F1F_Pos) == 1U) { if (((hfdcan->Instance->RXGFC & FDCAN_RXGFC_F1OM) >> FDCAN_RXGFC_F1OM_Pos) == FDCAN_RX_FIFO_OVERWRITE) { /* When overwrite status is on discard first message in FIFO */ - GetIndex = 1U; + /* GetIndex is incremented by one and wraps to 0 in case it overflows the FIFO size */ + GetIndex = (GetIndex + 1U) & SRAMCAN_RF1_NBR; } } - /* Calculate Rx FIFO 1 element index */ - GetIndex += ((hfdcan->Instance->RXF1S & FDCAN_RXF1S_F1GI) >> FDCAN_RXF1S_F1GI_Pos); /* Calculate Rx FIFO 1 element address */ RxAddress = (uint32_t *)(hfdcan->msgRam.RxFIFO1SA + (GetIndex * SRAMCAN_RF1_SIZE)); } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash.c index 37da2e5053..7601174e85 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash.c @@ -598,7 +598,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) Even if the FLASH operation fails, the BUSY flag will be reset and an error flag will be set */ - uint32_t timeout = HAL_GetTick() + Timeout; + uint32_t tickstart = HAL_GetTick(); uint32_t error; __IO uint32_t *reg_sr; @@ -606,7 +606,7 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout) { if(Timeout != HAL_MAX_DELAY) { - if(HAL_GetTick() >= timeout) + if(((HAL_GetTick() - tickstart) >= Timeout) || (Timeout == 0U)) { return HAL_TIMEOUT; } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash_ex.c index 5da5e629c2..4378e953b0 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_flash_ex.c @@ -946,9 +946,9 @@ static void FLASH_OB_RDPConfig(uint32_t RDPLevel) * @ref FLASH_OB_USER_nRST_SHUTDOWN, @ref FLASH_OB_USER_IWDG_SW, * @ref FLASH_OB_USER_IWDG_STOP, @ref FLASH_OB_USER_IWDG_STANDBY, * @ref FLASH_OB_USER_WWDG_SW, @ref OB_USER_SWAP_BANK, - * @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_DBANK, - * @ref FLASH_OB_USER_SRAM2_PAR, @ref FLASH_OB_USER_SRAM2_RST, - * @ref OB_USER_nSWBOOT0, @ref OB_USER_nBOOT0, @ref FLASH_OB_USER_PA15_PUPEN + * @ref FLASH_OB_USER_DUALBANK, @ref FLASH_OB_USER_SRAM2_PAR, + * @ref FLASH_OB_USER_SRAM2_RST, @ref OB_USER_nSWBOOT0, + * @ref OB_USER_nBOOT0, @ref FLASH_OB_USER_PA15_PUPEN * and @ref OB_USER_TZEN * * @retval None diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c index 1d2c29c2fb..3c09d22975 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_gpio.c @@ -156,7 +156,7 @@ * the configuration information for the specified GPIO peripheral. * @retval None */ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init) { uint32_t position = 0U; uint32_t iocurrent; @@ -196,7 +196,8 @@ void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init) } /* Activate the Pull-up or Pull down resistor for the current IO */ - if ((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) + if (((GPIO_Init->Mode & GPIO_MODE) != MODE_ANALOG) || + (((GPIO_Init->Mode & GPIO_MODE) == MODE_ANALOG) && (GPIO_Init->Pull != GPIO_PULLUP))) { /* Check the Pull parameter */ assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); @@ -364,7 +365,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin) * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin) { GPIO_PinState bitstatus; @@ -587,7 +588,7 @@ void HAL_GPIO_ConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32 * @param pPinAttributes pointer to return the pin attributes. * @retval HAL Status. */ -HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes) +HAL_StatusTypeDef HAL_GPIO_GetConfigPinAttributes(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, uint32_t *pPinAttributes) { /* Check null pointer */ if (pPinAttributes == NULL) diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c index 7e02640d2e..793fa9e01a 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash.c @@ -272,10 +272,10 @@ */ static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma); static void HASH_DMAError(DMA_HandleTypeDef *hdma); -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size); +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size); static HAL_StatusTypeDef HASH_WaitOnFlagUntilTimeout(HASH_HandleTypeDef *hhash, uint32_t Flag, FlagStatus Status, uint32_t Timeout); -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size); +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size); static HAL_StatusTypeDef HASH_IT(HASH_HandleTypeDef *hhash); static uint32_t HASH_Write_Block_Data(HASH_HandleTypeDef *hhash); static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Timeout); @@ -764,7 +764,8 @@ HAL_StatusTypeDef HAL_HASH_UnRegisterCallback(HASH_HandleTypeDef *hhash, HAL_HAS * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -790,7 +791,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -805,7 +806,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -822,7 +823,8 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -848,7 +850,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -863,7 +865,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBu * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -911,7 +913,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *p * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -935,7 +937,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -949,7 +951,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -965,7 +967,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -990,7 +992,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1004,7 +1006,7 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASH_SHA1_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1077,7 +1079,7 @@ void HAL_HASH_IRQHandler(HASH_HandleTypeDef *hhash) * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1107,7 +1109,7 @@ HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBu * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASH_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1164,7 +1166,8 @@ HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutB * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_MD5); @@ -1183,7 +1186,8 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA1); @@ -1225,7 +1229,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuf * @param pOutBuffer pointer to the computed digest. Digest size is 16 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_MD5); @@ -1243,7 +1247,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param pOutBuffer pointer to the computed digest. Digest size is 20 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA1); @@ -1254,7 +1258,6 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn */ - /** @defgroup HASH_Exported_Functions_Group7 HMAC processing functions in DMA mode * @brief HMAC processing functions using DMA modes. * @@ -1297,7 +1300,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); } @@ -1322,7 +1325,7 @@ HAL_StatusTypeDef HAL_HMAC_MD5_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pIn * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); } @@ -1369,7 +1372,7 @@ HAL_StatusTypeDef HAL_HMAC_SHA1_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pI * @param hhash HASH handle. * @retval HAL HASH state */ -HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) +HAL_HASH_StateTypeDef HAL_HASH_GetState(const HASH_HandleTypeDef *hhash) { return hhash->State; } @@ -1382,7 +1385,7 @@ HAL_HASH_StateTypeDef HAL_HASH_GetState(HASH_HandleTypeDef *hhash) * @param hhash HASH handle. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) +HAL_StatusTypeDef HAL_HASH_GetStatus(const HASH_HandleTypeDef *hhash) { return hhash->Status; } @@ -1400,7 +1403,7 @@ HAL_StatusTypeDef HAL_HASH_GetStatus(HASH_HandleTypeDef *hhash) * must be at least (HASH_NUMBER_OF_CSR_REGISTERS + 3) * 4 uint8 long. * @retval None */ -void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextSaving(const HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1441,7 +1444,7 @@ void HAL_HASH_ContextSaving(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) * beforehand). * @retval None */ -void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, uint8_t *pMemBuffer) +void HAL_HASH_ContextRestoring(HASH_HandleTypeDef *hhash, const uint8_t *pMemBuffer) { uint32_t mem_ptr = (uint32_t)pMemBuffer; uint32_t csr_ptr = (uint32_t)HASH->CSR; @@ -1620,7 +1623,7 @@ HAL_StatusTypeDef HAL_HASH_DMAFeed_ProcessSuspend(HASH_HandleTypeDef *hhash) * @param hhash pointer to a HASH_HandleTypeDef structure. * @retval HASH Error Code */ -uint32_t HAL_HASH_GetError(HASH_HandleTypeDef *hhash) +uint32_t HAL_HASH_GetError(const HASH_HandleTypeDef *hhash) { /* Return HASH Error Code */ return hhash->ErrorCode; @@ -1821,7 +1824,7 @@ static void HASH_DMAError(DMA_HandleTypeDef *hdma) * suspension time is stored in the handle for resumption later on. * @retval HAL status */ -static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { uint32_t buffercounter; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -1917,8 +1920,8 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB if ((Size % 4U) == 3U) { tmp = *(uint8_t *)inputaddr; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 1U) << 8U; - tmp |= (uint32_t)*(uint8_t *)(inputaddr + 2U) << 16U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 1U) << 8U; + tmp |= (uint32_t) * (uint8_t *)(inputaddr + 2U) << 16U; HASH->DIN = tmp; } @@ -1927,7 +1930,6 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB { HASH->DIN = *(uint32_t *)inputaddr; } - /*hhash->HashInCount += 4U;*/ } @@ -1940,7 +1942,7 @@ static HAL_StatusTypeDef HASH_WriteData(HASH_HandleTypeDef *hhash, uint8_t *pInB * @param Size message digest size in bytes. * @retval None */ -static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) +static void HASH_GetDigest(const uint8_t *pMsgDigest, uint8_t Size) { uint32_t msgdigest = (uint32_t)pMsgDigest; @@ -2005,7 +2007,6 @@ static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size) } - /** * @brief Handle HASH processing Timeout. * @param hhash HASH handle. @@ -2491,10 +2492,11 @@ static HAL_StatusTypeDef HMAC_Processing(HASH_HandleTypeDef *hhash, uint32_t Tim * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2526,7 +2528,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Set the phase */ @@ -2542,7 +2544,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; Size_tmp = hhash->HashInCount; } /* ... or multi-buffer HASH processing end */ @@ -2550,7 +2552,7 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint { /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; + pInBuffer_tmp = (const uint8_t *)pInBuffer; Size_tmp = Size; /* Configure the number of valid bits in last word of the message */ __HAL_HASH_SET_NBVALIDBITS(Size); @@ -2628,9 +2630,10 @@ HAL_StatusTypeDef HASH_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { - uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ + const uint8_t *pInBuffer_tmp; /* input data address, input parameter of HASH_WriteData() */ uint32_t Size_tmp; /* input data size (in bytes), input parameter of HASH_WriteData() */ HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2662,7 +2665,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* Since this is resumption, pInBuffer_tmp and Size_tmp are not set to the API input parameters but to those saved beforehand by HASH_WriteData() when the processing was suspended */ - pInBuffer_tmp = hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)hhash->pHashInBuffPtr; /* pInBuffer_tmp is set to the input data address */ Size_tmp = hhash->HashInCount; /* Size_tmp contains the input data size in bytes */ } @@ -2673,7 +2676,7 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, /* pInBuffer_tmp and Size_tmp are initialized to be used afterwards as input parameters of HASH_WriteData() */ - pInBuffer_tmp = pInBuffer; /* pInBuffer_tmp is set to the input data address */ + pInBuffer_tmp = (const uint8_t *)pInBuffer; /* pInBuffer_tmp is set to the input data address */ Size_tmp = Size; /* Size_tmp contains the input data size in bytes */ /* Check if initialization phase has already be performed */ @@ -2731,7 +2734,8 @@ HAL_StatusTypeDef HASH_Accumulate(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; __IO uint32_t inputaddr = (uint32_t) pInBuffer; @@ -2841,7 +2845,6 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff } - /** * @brief Initialize the HASH peripheral, next process pInBuffer then * read the computed digest in interruption mode. @@ -2853,7 +2856,8 @@ HAL_StatusTypeDef HASH_Accumulate_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuff * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -2902,6 +2906,19 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ } + else if ((hhash->Phase == HAL_HASH_PHASE_PROCESS) && (SizeVar < 4U)) + { + if (__HAL_HASH_GET_FLAG(HASH_FLAG_DINIS)) + { + /* It remains data to enter and the Peripheral is ready to trigger DINIE,carry on as usual. + Update HashInCount and pHashInBuffPtr accordingly. */ + hhash->HashInCount = SizeVar; + hhash->pHashInBuffPtr = (uint8_t *)inputaddr; + /* Update the configuration of the number of valid bits in last word of the message */ + __HAL_HASH_SET_NBVALIDBITS(SizeVar); + hhash->pHashOutBuffPtr = pOutBuffer; /* Points at the computed digest */ + } + } else { initialization_skipped = 1; /* info user later on in case of multi-buffer */ @@ -3011,7 +3028,8 @@ HAL_StatusTypeDef HASH_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HASH_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; @@ -3188,7 +3206,8 @@ HAL_StatusTypeDef HASH_Finish(HASH_HandleTypeDef *hhash, uint8_t *pOutBuffer, ui * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Timeout, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3252,7 +3271,6 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint } - /** * @brief Initialize the HASH peripheral in HMAC mode, next process pInBuffer then * read the computed digest in interruption mode. @@ -3266,7 +3284,8 @@ HAL_StatusTypeDef HMAC_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t *pOutBuffer, +HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint8_t *pOutBuffer, uint32_t Algorithm) { HAL_HASH_StateTypeDef State_tmp = hhash->State; @@ -3361,7 +3380,6 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u } - /** * @brief Initialize the HASH peripheral in HMAC mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -3377,7 +3395,8 @@ HAL_StatusTypeDef HMAC_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, u * @param Algorithm HASH algorithm. * @retval HAL status */ -HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint32_t Algorithm) +HAL_StatusTypeDef HMAC_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, + uint32_t Algorithm) { uint32_t inputaddr; uint32_t inputSize; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash_ex.c index 356b77ec7b..31fe875b73 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_hash_ex.c @@ -86,8 +86,6 @@ #include "stm32l5xx_hal.h" - - /** @addtogroup STM32L5xx_HAL_Driver * @{ */ @@ -148,7 +146,7 @@ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -174,7 +172,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -189,7 +187,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -206,7 +204,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -247,7 +245,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HASH_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -290,7 +288,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End(HASH_HandleTypeDef *hhash, uint8_ * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -314,7 +312,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -328,7 +326,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -344,7 +343,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -368,7 +367,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes, must be a multiple of 4. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Accumulate_IT(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -382,7 +381,8 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size, uint8_t *pOutBuffer) { return HASH_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); @@ -422,8 +422,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin */ - - /** * @brief Initialize the HASH peripheral in SHA224 mode then initiate a DMA transfer * to feed the input buffer to the Peripheral. @@ -434,7 +432,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Accmlt_End_IT(HASH_HandleTypeDef *hhash, uin * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -464,7 +462,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HASH_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -507,7 +505,6 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest. @@ -521,7 +518,7 @@ HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t *p * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA224); @@ -540,7 +537,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param Timeout Timeout value. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer, uint32_t Timeout) { return HMAC_Start(hhash, pInBuffer, Size, pOutBuffer, Timeout, HASH_ALGOSELECTION_SHA256); @@ -570,7 +567,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode, next process pInBuffer then * read the computed digest in interrupt mode. @@ -583,7 +579,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pI * @param pOutBuffer pointer to the computed digest. Digest size is 28 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA224); @@ -601,15 +597,13 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param pOutBuffer pointer to the computed digest. Digest size is 32 bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size, uint8_t *pOutBuffer) { return HMAC_Start_IT(hhash, pInBuffer, Size, pOutBuffer, HASH_ALGOSELECTION_SHA256); } - - /** * @} */ @@ -639,7 +633,6 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t */ - /** * @brief Initialize the HASH peripheral in HMAC SHA224 mode then initiate the required * DMA transfers to feed the key and the input buffer to the Peripheral. @@ -659,7 +652,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); } @@ -683,7 +676,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); } @@ -759,7 +752,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Start_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -780,7 +773,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -806,7 +799,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *p * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_MD5); @@ -829,7 +822,7 @@ HAL_StatusTypeDef HAL_HMACEx_MD5_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -850,7 +843,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -876,7 +869,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA1); @@ -898,7 +891,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA1_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -919,7 +913,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -945,7 +939,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA224); @@ -967,7 +962,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA224_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = SET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); @@ -988,7 +984,7 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step1_2_DMA(HASH_HandleTypeDef *hhash, uint8 * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, uint32_t Size) { if (hhash->DigestCalculationDisable != SET) { @@ -1014,7 +1010,8 @@ HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_DMA(HASH_HandleTypeDef *hhash, uint8_t * @param Size length of the input buffer in bytes. * @retval HAL status */ -HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size) +HAL_StatusTypeDef HAL_HMACEx_SHA256_Step2_3_DMA(HASH_HandleTypeDef *hhash, const uint8_t *const pInBuffer, + uint32_t Size) { hhash->DigestCalculationDisable = RESET; return HMAC_Start_DMA(hhash, pInBuffer, Size, HASH_ALGOSELECTION_SHA256); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c index b1038d6836..8f0d320a94 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_i2c.c @@ -3324,33 +3324,46 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd /* Wait until STOPF flag is reset */ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + if (hi2c->ErrorCode == HAL_I2C_ERROR_AF) + { + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + + /* Reset the error code for next trial */ + hi2c->ErrorCode = HAL_I2C_ERROR_NONE; + } } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); - /* Device is ready */ - hi2c->State = HAL_I2C_STATE_READY; + /* Device is ready */ + hi2c->State = HAL_I2C_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hi2c); + /* Process Unlocked */ + __HAL_UNLOCK(hi2c); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + /* Wait until STOPF flag is reset */ + if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) == HAL_OK) + { + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF); + } } /* Increment Trials */ @@ -6349,7 +6362,7 @@ static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6505,7 +6518,7 @@ static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags) /* Increment Buffer pointer */ hi2c->pBuffPtr++; - if ((hi2c->XferSize > 0U)) + if (hi2c->XferSize > 0U) { hi2c->XferSize--; hi2c->XferCount--; @@ -6953,7 +6966,7 @@ static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uin { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)) + if (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -6993,7 +7006,7 @@ static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, { if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7032,7 +7045,7 @@ static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if (((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7110,7 +7123,7 @@ static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, /* Check for the Timeout */ if ((((HAL_GetTick() - Tickstart) > Timeout) || (Timeout == 0U)) && (status == HAL_OK)) { - if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)) + if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET) { hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT; hi2c->State = HAL_I2C_STATE_READY; @@ -7277,15 +7290,17 @@ static HAL_StatusTypeDef I2C_IsErrorOccurred(I2C_HandleTypeDef *hi2c, uint32_t T static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request) { + uint32_t tmp; + /* Check the parameters */ assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance)); assert_param(IS_TRANSFER_MODE(Mode)); assert_param(IS_TRANSFER_REQUEST(Request)); /* Declaration of tmp to prevent undefined behavior of volatile usage */ - uint32_t tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ - (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ - (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); + tmp = ((uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | \ + (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | \ + (uint32_t)Mode | (uint32_t)Request) & (~0x80000000U)); /* update CR2 register */ MODIFY_REG(hi2c->Instance->CR2, \ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c index 048cd48b53..8e5a595be3 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc.c @@ -490,7 +490,7 @@ HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc) HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) { uint32_t errorstate; - MMC_InitTypeDef Init; + MMC_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for MMC card initialization */ @@ -507,7 +507,14 @@ HAL_StatusTypeDef HAL_MMC_InitCard(MMC_HandleTypeDef *hmmc) hmmc->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk / (2U * MMC_INIT_FREQ); + if (sdmmc_clk <= MMC_INIT_FREQ) + { + Init.ClockDiv = 0U; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * MMC_INIT_FREQ)) + 1U; + } #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = SDMMC_TRANSCEIVER_NOT_PRESENT; @@ -2163,7 +2170,7 @@ HAL_StatusTypeDef HAL_MMC_UnRegisterCallback(MMC_HandleTypeDef *hmmc, HAL_MMC_Ca * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardCID(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_MMC_GetCardCID(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hmmc->CID[0] & 0xFF000000U) >> 24U); @@ -2314,7 +2321,7 @@ HAL_StatusTypeDef HAL_MMC_GetCardCSD(MMC_HandleTypeDef *hmmc, HAL_MMC_CardCSDTyp * will contain the MMC card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_MMC_GetCardInfo(MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_MMC_GetCardInfo(const MMC_HandleTypeDef *hmmc, HAL_MMC_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hmmc->MmcCard.CardType); pCardInfo->Class = (uint32_t)(hmmc->MmcCard.Class); @@ -3411,7 +3418,7 @@ HAL_StatusTypeDef HAL_MMC_SleepDevice(MMC_HandleTypeDef *hmmc) { /* Send CMD5 CMD_MMC_SLEEP_AWAKE with RCA and SLEEP as argument */ errorstate = SDMMC_CmdSleepMmc(hmmc->Instance, - ((hmmc->MmcCard.RelCardAdd << 16U) | (0x1U << 15U))); + ((hmmc->MmcCard.RelCardAdd << 16UL) | (0x1UL << 15UL))); if (errorstate == HAL_MMC_ERROR_NONE) { /* Wait that the device is ready by checking the D0 line */ @@ -4029,7 +4036,7 @@ static uint32_t MMC_HighSpeed(MMC_HandleTypeDef *hmmc, FunctionalState state) uint32_t response = 0U; uint32_t count; uint32_t sdmmc_clk; - SDMMC_InitTypeDef Init; + SDMMC_InitTypeDef Init = {0U}; if (((hmmc->Instance->CLKCR & SDMMC_CLKCR_BUSSPEED) != 0U) && (state == DISABLE)) { @@ -4345,7 +4352,6 @@ static uint32_t MMC_PwrClassUpdate(MMC_HandleTypeDef *hmmc, uint32_t Wide, uint3 * @brief Used to select the partition. * @param hmmc: Pointer to MMC handle * @param Partition: Partition type - * @param Timeout: Specify timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_MMC_SwitchPartition(MMC_HandleTypeDef *hmmc, HAL_MMC_PartitionTypeDef Partition) @@ -4726,7 +4732,7 @@ HAL_StatusTypeDef HAL_MMC_RPMB_ProgramAuthenticationKey(MMC_HandleTypeDef *hmmc, /** * @brief Allows to get the value of write counter within the RPMB partition. * @param hmmc: Pointer to MMC handle - * @param Nonce: pointer to the value of nonce (16 bytes) + * @param pNonce: pointer to the value of nonce (16 bytes) * @param Timeout: Specify timeout value * @retval write counter value. */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c index 8c0ccd5fbf..5916a1efcb 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_mmc_ex.c @@ -60,7 +60,6 @@ */ - /** @addtogroup MMCEx_Exported_Functions_Group1 * @brief Multibuffer functions * @@ -334,7 +333,6 @@ HAL_StatusTypeDef HAL_MMCEx_ChangeDMABuffer(MMC_HandleTypeDef *hmmc, HAL_MMCEx_D return HAL_OK; } - /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c index 954a068f40..a22fcb6030 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_nand.c @@ -492,7 +492,7 @@ HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand) * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure * @retval HAL status */ -HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig) +HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, const NAND_DeviceConfigTypeDef *pDeviceConfig) { hnand->Config.PageSize = pDeviceConfig->PageSize; hnand->Config.SpareAreaSize = pDeviceConfig->SpareAreaSize; @@ -520,7 +520,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpagesread = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; uint8_t *buff = pBuffer; @@ -635,13 +634,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, const NAND_Ad /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint8_t *)deviceaddress; + *buff = *(__IO uint8_t *)deviceaddress; buff++; } - /* Increment read pages number */ - numpagesread++; - /* Decrement pages to read */ nbpages--; @@ -678,7 +674,6 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpagesread = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToRead; uint16_t *buff = pBuffer; @@ -803,13 +798,10 @@ HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, const NAND_A /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.PageSize; index++) { - *buff = *(uint16_t *)deviceaddress; + *buff = *(__IO uint16_t *)deviceaddress; buff++; } - /* Increment read pages number */ - numpagesread++; - /* Decrement pages to read */ nbpages--; @@ -846,7 +838,6 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; const uint8_t *buff = pBuffer; @@ -960,9 +951,6 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, const NAND_A } } - /* Increment written pages number */ - numpageswritten++; - /* Decrement pages to write */ nbpages--; @@ -999,7 +987,6 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numpageswritten = 0U; uint32_t nandaddress; uint32_t nbpages = NumPageToWrite; const uint16_t *buff = pBuffer; @@ -1124,9 +1111,6 @@ HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, const NAND_ } } - /* Increment written pages number */ - numpageswritten++; - /* Decrement pages to write */ nbpages--; @@ -1163,7 +1147,6 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numsparearearead = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; @@ -1285,13 +1268,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, const NA /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint8_t *)deviceaddress; + *buff = *(__IO uint8_t *)deviceaddress; buff++; } - /* Increment read spare areas number */ - numsparearearead++; - /* Decrement spare areas to read */ nbspare--; @@ -1328,7 +1308,6 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numsparearearead = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaToRead; @@ -1450,13 +1429,10 @@ HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, const N /* Get Data into Buffer */ for (index = 0U; index < hnand->Config.SpareAreaSize; index++) { - *buff = *(uint16_t *)deviceaddress; + *buff = *(__IO uint16_t *)deviceaddress; buff++; } - /* Increment read spare areas number */ - numsparearearead++; - /* Decrement spare areas to read */ nbspare--; @@ -1493,7 +1469,6 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; @@ -1617,9 +1592,6 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, const N } } - /* Increment written spare areas number */ - numspareareawritten++; - /* Decrement spare areas to write */ nbspare--; @@ -1656,7 +1628,6 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const uint32_t index; uint32_t tickstart; uint32_t deviceaddress; - uint32_t numspareareawritten = 0U; uint32_t nandaddress; uint32_t columnaddress; uint32_t nbspare = NumSpareAreaTowrite; @@ -1780,9 +1751,6 @@ HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, const } } - /* Increment written spare areas number */ - numspareareawritten++; - /* Decrement spare areas to write */ nbspare--; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c index 05f88360ef..95ef695c62 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_ospi.c @@ -134,6 +134,7 @@ [..] After the configuration, the OctoSPI will be used as soon as an access on the AHB is done on the address range. HAL_OSPI_TimeOutCallback() will be called when the timeout expires. + HAL_OSPI_IsMemoryMapped() can be used to verify whether memory-mapped mode is configured or not. *** Errors management and abort functionality *** ================================================= @@ -1134,7 +1135,8 @@ HAL_StatusTypeDef HAL_OSPI_Transmit(OSPI_HandleTypeDef *hospi, uint8_t *pData, u *((__IO uint8_t *)data_reg) = *hospi->pBuffPtr; hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1227,7 +1229,8 @@ HAL_StatusTypeDef HAL_OSPI_Receive(OSPI_HandleTypeDef *hospi, uint8_t *pData, ui *hospi->pBuffPtr = *((__IO uint8_t *)data_reg); hospi->pBuffPtr++; hospi->XferCount--; - } while (hospi->XferCount > 0U); + } + while (hospi->XferCount > 0U); if (status == HAL_OK) { @@ -1847,6 +1850,29 @@ HAL_StatusTypeDef HAL_OSPI_MemoryMapped(OSPI_HandleTypeDef *hospi, OSPI_MemoryMa return status; } +/** + * @brief Check whether the OCTOSPI is configured in Memory-mapped mode or not. + * @param hospi : OSPI handle + * @retval Status (0: Memory-mapped disabled or OCTOSPI not initialized, 1: Memory-mapped enabled) + */ +uint32_t HAL_OSPI_IsMemoryMapped(OSPI_HandleTypeDef *hospi) +{ + /* Check the OSPI handle allocation */ + if (hospi == NULL) + { + return (0UL); + } + /* Check if driver is in Reset state */ + else if (hospi->State == HAL_OSPI_STATE_RESET) + { + return (0UL); + } + else + { + return ((READ_BIT(hospi->Instance->CR, OCTOSPI_CR_FMODE) == OCTOSPI_CR_FMODE) ? 1UL : 0UL); + } +} + /** * @brief Transfer Error callback. * @param hospi : OSPI handle diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c index 343f70d338..c301587db8 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_otfdec.c @@ -525,9 +525,6 @@ __weak void HAL_OTFDEC_ErrorCallback(OTFDEC_HandleTypeDef *hotfdec) * @} */ - - - /** @defgroup OTFDEC_Exported_Functions_Group3 Peripheral Control functions * @brief Peripheral control functions. * @@ -1120,9 +1117,8 @@ HAL_StatusTypeDef HAL_OTFDEC_RegionGetConfig(OTFDEC_HandleTypeDef *hotfdec, uint Config->EndAddress = READ_REG(region->REG_END_ADDR); /* Read Version */ - Config->Version = (uint16_t)(READ_REG(region->REG_CONFIGR) & - OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos; - + Config->Version = (uint16_t)((READ_REG(region->REG_CONFIGR) & + OTFDEC_REG_CONFIGR_VERSION) >> OTFDEC_REG_CONFIGR_VERSION_Pos); /* Release Lock */ __HAL_UNLOCK(hotfdec); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c index 4d116938fc..462b58ce79 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd.c @@ -49,6 +49,9 @@ (#)Enable PCD transmission and reception: (##) HAL_PCD_Start(); + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** */ @@ -1389,7 +1392,7 @@ HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address) HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type) { - HAL_StatusTypeDef ret = HAL_OK; + HAL_StatusTypeDef ret = HAL_OK; PCD_EPTypeDef *ep; if ((ep_addr & 0x80U) == 0x80U) @@ -1404,7 +1407,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, } ep->num = ep_addr & EP_ADDR_MSK; - ep->maxpacket = ep_mps; + ep->maxpacket = (uint32_t)ep_mps & 0x7FFU; ep->type = ep_type; /* Set initial data PID. */ @@ -1770,6 +1773,18 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get SETUP Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); + if (ep->xfer_count != 8U) + { + /* Set Stall condition for EP0 IN/OUT */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_STALL); + PCD_SET_EP_TX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_TX_STALL); + + /* SETUP bit kept frozen while CTR_RX = 1 */ + PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); + + return HAL_OK; + } + USB_ReadPMA(hpcd->Instance, (uint8_t *)hpcd->Setup, ep->pmaadress, (uint16_t)ep->xfer_count); @@ -1790,27 +1805,27 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Get Control Data OUT Packet */ ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num); - if ((ep->xfer_count != 0U) && (ep->xfer_buff != 0U)) + if (ep->xfer_count == 0U) + { + /* Status phase re-arm for next setup */ + PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } + else { - USB_ReadPMA(hpcd->Instance, ep->xfer_buff, - ep->pmaadress, (uint16_t)ep->xfer_count); + if (ep->xfer_buff != 0U) + { + USB_ReadPMA(hpcd->Instance, ep->xfer_buff, + ep->pmaadress, (uint16_t)ep->xfer_count); /* max 64bytes */ - ep->xfer_buff += ep->xfer_count; + ep->xfer_buff += ep->xfer_count; - /* Process Control Data OUT Packet */ + /* Process Control Data OUT Packet */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->DataOutStageCallback(hpcd, 0U); + hpcd->DataOutStageCallback(hpcd, 0U); #else - HAL_PCD_DataOutStageCallback(hpcd, 0U); + HAL_PCD_DataOutStageCallback(hpcd, 0U); #endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } - - wEPVal = (uint16_t)PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0); - - if (((wEPVal & USB_EP_SETUP) == 0U) && ((wEPVal & USB_EP_RX_STRX) != USB_EP_RX_VALID)) - { - PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket); - PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID); + } } } } @@ -1876,7 +1891,6 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* multi-packet on the NON control OUT endpoint */ ep->xfer_count += count; - ep->xfer_buff += count; if ((ep->xfer_len == 0U) || (count < ep->maxpacket)) { @@ -1889,6 +1903,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) } else { + ep->xfer_buff += count; (void)USB_EPStartXfer(hpcd->Instance, ep); } } @@ -1930,7 +1945,7 @@ static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd) /* Manage Single Buffer Transaction */ if ((wEPVal & USB_EP_KIND) == 0U) { - /* multi-packet on the NON control IN endpoint */ + /* Multi-packet on the NON control IN endpoint */ TxPctSize = (uint16_t)PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num); if (ep->xfer_len > TxPctSize) @@ -2006,7 +2021,7 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK to OUT endpoint since double buffer is enabled */ + /* Set NAK to OUT endpoint since double buffer is enabled */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } @@ -2038,11 +2053,11 @@ static uint16_t HAL_PCD_EP_DB_Receive(PCD_HandleTypeDef *hpcd, if (ep->xfer_len == 0U) { - /* set NAK on the current endpoint */ + /* Set NAK on the current endpoint */ PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_NAK); } - /*Need to FreeUser Buffer*/ + /* Need to FreeUser Buffer */ if ((wEPVal & USB_EP_DTOG_TX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 0U); @@ -2092,6 +2107,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2103,10 +2124,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) != 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2137,7 +2160,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } /* Write remaining Data to Buffer */ - /* Set the Double buffer counter for pma buffer1 */ + /* Set the Double buffer counter for pma buffer0 */ PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy user buffer to USB PMA */ @@ -2165,6 +2188,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, PCD_SET_EP_DBUF0_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, 0U); + if (ep->type == EP_TYPE_BULK) + { + /* Set Bulk endpoint in NAK state */ + PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); + } + /* TX COMPLETE */ #if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) hpcd->DataInStageCallback(hpcd, ep->num); @@ -2177,10 +2206,12 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); } + + return HAL_OK; } else /* Transfer is not yet Done */ { - /* need to Free USB Buff */ + /* Need to Free USB Buffer */ if ((wEPVal & USB_EP_DTOG_RX) == 0U) { PCD_FREE_USER_BUFFER(hpcd->Instance, ep->num, 1U); @@ -2210,7 +2241,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, ep->xfer_fill_db = 0; } - /* Set the Double buffer counter for pmabuffer1 */ + /* Set the Double buffer counter for pma buffer1 */ PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len); /* Copy the user buffer to USB PMA */ @@ -2219,7 +2250,7 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, } } - /*enable endpoint IN*/ + /* Enable endpoint IN */ PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID); return HAL_OK; @@ -2227,13 +2258,11 @@ static HAL_StatusTypeDef HAL_PCD_EP_DB_Transmit(PCD_HandleTypeDef *hpcd, #endif /* (USE_USB_DOUBLE_BUFFER == 1U) */ - /** * @} */ #endif /* defined (USB) */ #endif /* HAL_PCD_MODULE_ENABLED */ - /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd_ex.c index 245616f764..4da559f9de 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pcd_ex.c @@ -82,7 +82,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { PCD_EPTypeDef *ep; - /* initialize ep structure*/ + /* Initialize ep structure */ if ((0x80U & ep_addr) == 0x80U) { ep = &hpcd->IN_ep[ep_addr & EP_ADDR_MSK]; @@ -97,6 +97,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Single Buffer */ ep->doublebuffer = 0U; + /* Configure the PMA */ ep->pmaadress = (uint16_t)pmaadress; } @@ -105,6 +106,7 @@ HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, uint16_t ep_addr { /* Double Buffer Endpoint */ ep->doublebuffer = 1U; + /* Configure the PMA */ ep->pmaaddr0 = (uint16_t)(pmaadress & 0xFFFFU); ep->pmaaddr1 = (uint16_t)((pmaadress & 0xFFFF0000U) >> 16); @@ -124,13 +126,11 @@ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) USB_TypeDef *USBx = hpcd->Instance; hpcd->battery_charging_active = 1U; - /* Enable BCD feature */ - USBx->BCDR |= USB_BCDR_BCDEN; - - /* Enable DCD : Data Contact Detect */ USBx->BCDR &= ~(USB_BCDR_PDEN); USBx->BCDR &= ~(USB_BCDR_SDEN); - USBx->BCDR |= USB_BCDR_DCDEN; + + /* Enable BCD feature */ + USBx->BCDR |= USB_BCDR_BCDEN; return HAL_OK; } @@ -162,21 +162,10 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) uint32_t tickstart = HAL_GetTick(); /* Wait for Min DCD Timeout */ - HAL_Delay(300U); + HAL_Delay(350U); - /* Data Pin Contact ? Check Detect flag */ - if ((USBx->BCDR & USB_BCDR_DCDET) == USB_BCDR_DCDET) - { -#if (USE_HAL_PCD_REGISTER_CALLBACKS == 1U) - hpcd->BCDCallback(hpcd, PCD_BCD_CONTACT_DETECTION); -#else - HAL_PCDEx_BCD_Callback(hpcd, PCD_BCD_CONTACT_DETECTION); -#endif /* USE_HAL_PCD_REGISTER_CALLBACKS */ - } /* Primary detection: checks if connected to Standard Downstream Port (without charging capability) */ - USBx->BCDR &= ~(USB_BCDR_DCDEN); - HAL_Delay(50U); USBx->BCDR |= (USB_BCDR_PDEN); HAL_Delay(50U); @@ -242,7 +231,6 @@ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) } } - /** * @brief Activate LPM feature. * @param hpcd PCD handle @@ -279,7 +267,6 @@ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) } - /** * @brief Send LPM message to user layer callback. * @param hpcd PCD handle diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c index db3078c7a6..9f3c8e74e4 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pka.c @@ -2079,20 +2079,20 @@ void PKA_ModExpFastMode_Set(PKA_HandleTypeDef *hpka, PKA_ModExpFastModeInTypeDef /* Move the input parameters pOp1 to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT_BASE], in->pOp1, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT_BASE + ((in->OpSize + 3UL) / 4UL)); /* Move the exponent to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_EXPONENT], in->pExp, in->expSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + (in->expSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_EXPONENT + ((in->expSize + 3UL) / 4UL)); /* Move the modulus to PKA RAM */ PKA_Memcpy_u8_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MODULUS], in->pMod, in->OpSize); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MODULUS + ((in->OpSize + 3UL) / 4UL)); /* Move the Montgomery parameter to PKA RAM */ PKA_Memcpy_u32_to_u32(&hpka->Instance->RAM[PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM], in->pMontgomeryParam, in->OpSize / 4UL); - __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + (in->OpSize / 4UL)); + __PKA_RAM_PARAM_END(hpka->Instance->RAM, PKA_MODULAR_EXP_IN_MONTGOMERY_PARAM + ((in->OpSize + 3UL) / 4UL)); } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c index 9c4f258c6c..595005233e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr.c @@ -307,7 +307,7 @@ void HAL_PWR_DisableBkUpAccess(void) * detection level. * @retval None */ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD) +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD) { /* Check the parameters */ assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel)); @@ -658,6 +658,13 @@ __weak void HAL_PWR_PVDCallback(void) * @note Secure and non-secure attributes can only be set from the secure * state when the system implements the security (TZEN=1). * @note Security and privilege attributes can be set independently. + * @note As the privileged attribute concerns all secure and non-secure PWR + * resources accesses and not each PWR individual items access attribute, + * the application must ensure that the privileged access attribute configuration + * is coherent amongst the security level set on PWR individual items so not + * to overwrite a previous more restricted access rule (consider either all secure + * and non-secure PWR resources accesses by privileged-only transactions + * or privileged and unprivileged transactions). * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref PWR_items * @param Attributes can be one or a combination of the following values: diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c index 7e543ab2c4..194f182ee6 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_pwr_ex.c @@ -664,7 +664,7 @@ void HAL_PWREx_DisablePVM4(void) * detection level and to each monitored supply. * @retval HAL status */ -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM) +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM) { HAL_StatusTypeDef status = HAL_OK; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c index 12d2191e94..603e5b06e9 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc.c @@ -1135,7 +1135,7 @@ HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct) * (for more details refer to section above "Initialization/de-initialization functions") * @retval None */ -HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) +HAL_StatusTypeDef HAL_RCC_ClockConfig(const RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency) { uint32_t tickstart; uint32_t pllfreq; @@ -1360,7 +1360,7 @@ HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, ui * @arg @ref RCC_MCO1SOURCE_SYSCLK system clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_MSI MSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_HSI HSI clock selected as MCO source - * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO sourcee + * @arg @ref RCC_MCO1SOURCE_HSE HSE clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_PLLCLK main PLL clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSI LSI clock selected as MCO source * @arg @ref RCC_MCO1SOURCE_LSE LSE clock selected as MCO source @@ -1802,6 +1802,12 @@ uint32_t HAL_RCC_GetResetSource(void) * @note Secure and non-secure attributes can only be set from the secure * state when the system implements the security (TZEN=1). * @note Security and privilege attributes can be set independently. + * @note As the privileged attribute concerns all secure and non-secure + * RCC resources accesses and not each RCC individual items access attribute, + * the application must ensure that the privilege access attribute configuration + * is coherent amongst the security level set on RCC individual items so not to overwrite + * a previous more restricted access rule (consider either all secure and non-secure RCC resources + * accesses by privileged-only transactions or privileged and unprivileged transactions) * @param Item Item(s) to set attributes on. * This parameter can be a one or a combination of @ref RCC_items * @param Attributes can be one or a combination of the following values: @@ -2039,9 +2045,9 @@ static uint32_t RCC_GetSysClockFreqFromPLLSource(void) { /* MSIRANGE from RCC_CR applies */ msirange = READ_BIT(RCC->CR, RCC_CR_MSIRANGE) >> RCC_CR_MSIRANGE_Pos; } - /*MSI frequency range in HZ*/ - pllvco = MSIRangeTable[msirange]; - break; + /*MSI frequency range in HZ*/ + pllvco = MSIRangeTable[msirange]; + break; default: /* unexpected */ pllvco = 0; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc_ex.c index 28756377f2..b7e97953af 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rcc_ex.c @@ -72,9 +72,9 @@ * @{ */ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource); -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(const RCC_PLLSAI1InitTypeDef *pPllSai1, uint32_t Divider); static uint32_t RCCEx_PLLSAI1_GetVCOFreq(void); -static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *pPllSai2, uint32_t Divider); +static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(const RCC_PLLSAI2InitTypeDef *pPllSai2, uint32_t Divider); static uint32_t RCCEx_PLLSAI2_GetVCOFreq(void); static uint32_t RCCEx_GetSAIxPeriphCLKFreq(uint32_t PeriphClk, uint32_t InputFrequency); @@ -1937,7 +1937,7 @@ __weak void HAL_RCCEx_LSECSS_Callback(void) */ void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource) { - GPIO_InitTypeDef GPIO_InitStruct; + GPIO_InitTypeDef GPIO_InitStruct = {0}; FlagStatus pwrclkchanged = RESET; FlagStatus backupchanged = RESET; @@ -2111,7 +2111,7 @@ void HAL_RCCEx_DisableMSIPLLMode(void) * @param pInit Pointer on RCC_CRSInitTypeDef structure * @retval None */ -void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit) +void HAL_RCCEx_CRSConfig(const RCC_CRSInitTypeDef *pInit) { uint32_t value; @@ -2519,7 +2519,7 @@ static HAL_StatusTypeDef RCCEx_PLLSource_Enable(uint32_t PllSource) * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(const RCC_PLLSAI1InitTypeDef *pPllSai1, uint32_t Divider) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; @@ -2659,7 +2659,7 @@ static HAL_StatusTypeDef RCCEx_PLLSAI1_Config(RCC_PLLSAI1InitTypeDef *pPllSai1, * * @retval HAL status */ -static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(RCC_PLLSAI2InitTypeDef *pPllSai2, uint32_t Divider) +static HAL_StatusTypeDef RCCEx_PLLSAI2_Config(const RCC_PLLSAI2InitTypeDef *pPllSai2, uint32_t Divider) { HAL_StatusTypeDef status = HAL_OK; uint32_t tickstart; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c index ca33d9f7a6..55ed5683dc 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng.c @@ -115,7 +115,8 @@ */ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ -#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliance */ +#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ +#define RNG_CRCFG 0x00F00D00U /** * @} */ @@ -206,12 +207,12 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) /* Disable RNG */ __HAL_RNG_DISABLE(hrng); - /* Clock Error Detection Configuration when CONDRT bit is set to 1 */ - MODIFY_REG(hrng->Instance->CR, RNG_CR_CED | RNG_CR_CONDRST, hrng->Init.ClockErrorDetection | RNG_CR_CONDRST); + /* Recommended value for NIST compliance, refer to application note AN4230 */ + WRITE_REG(hrng->Instance->CR, RNG_CRCFG | RNG_CR_CONDRST | hrng->Init.ClockErrorDetection); #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -253,7 +254,7 @@ HAL_StatusTypeDef HAL_RNG_Init(RNG_HandleTypeDef *hrng) if ((HAL_GetTick() - tickstart) > RNG_TIMEOUT_VALUE) { /* New check to avoid false timeout detection in case of preemption */ - if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_SECS) != RESET) + if (__HAL_RNG_GET_FLAG(hrng, RNG_FLAG_DRDY) != SET) { hrng->State = HAL_RNG_STATE_ERROR; hrng->ErrorCode = HAL_RNG_ERROR_TIMEOUT; @@ -656,6 +657,8 @@ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t status = RNG_RecoverSeedError(hrng); if (status == HAL_ERROR) { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; return status; } } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c index 19171ae0e3..862979f5ed 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rng_ex.c @@ -30,7 +30,7 @@ #if defined(RNG) -/** @addtogroup RNG_Ex +/** @addtogroup RNGEx * @brief RNG Extended HAL module driver. * @{ */ @@ -44,13 +44,13 @@ */ /* Health test control register information to use in CCM algorithm */ #define RNG_HTCFG_1 0x17590ABCU /*!< Magic number */ -#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliance */ +#define RNG_HTCFG 0x0000A2B3U /*!< Recommended value for NIST compliance, refer to application note AN4230 */ /** * @} */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -/** @addtogroup RNG_Ex_Private_Constants +/** @addtogroup RNGEx_Private_Constants * @{ */ #define RNG_TIMEOUT_VALUE 2U @@ -62,11 +62,11 @@ /* Private functions --------------------------------------------------------*/ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @defgroup RNGEx_Exported_Functions RNGEx Exported Functions * @{ */ -/** @defgroup RNG_Ex_Exported_Functions_Group1 Configuration and lock functions +/** @defgroup RNGEx_Exported_Functions_Group1 Configuration and lock functions * @brief Configuration functions * @verbatim @@ -137,7 +137,7 @@ HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigT #if defined(RNG_VER_3_2) || defined(RNG_VER_3_1) || defined(RNG_VER_3_0) /*!< magic number must be written immediately before to RNG_HTCRG */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG_1); - /* for best latency and to be compliant with NIST */ + /* Recommended value for NIST compliance, refer to application note AN4230 */ WRITE_REG(hrng->Instance->HTCR, RNG_HTCFG); #endif /* RNG_VER_3_2 || RNG_VER_3_1 || RNG_VER_3_0 */ @@ -279,7 +279,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng) * @} */ -/** @defgroup RNG_Ex_Exported_Functions_Group2 Recover from seed error function +/** @defgroup RNGEx_Exported_Functions_Group2 Recover from seed error function * @brief Recover from seed error function * @verbatim @@ -316,6 +316,11 @@ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng) /* sequence to fully recover from a seed error */ status = RNG_RecoverSeedError(hrng); + if (status == HAL_ERROR) + { + /* Update the error code */ + hrng->ErrorCode = HAL_RNG_ERROR_RECOVERSEED; + } } else { diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc.c index 4f8b789367..d2654824fa 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc.c @@ -929,7 +929,7 @@ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTim * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format) { uint32_t tmpreg; @@ -1058,7 +1058,7 @@ HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef const *hrtc, RTC_DateTypeDef *sDate, uint32_t Format) { uint32_t datetmpreg; @@ -1092,7 +1092,7 @@ HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDat * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef const *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1106,7 +1106,7 @@ void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef const *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1120,7 +1120,7 @@ void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef const *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1133,7 +1133,7 @@ void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) +void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef const *hrtc) { UNUSED(hrtc); __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc); @@ -1146,7 +1146,7 @@ void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval operation see RTC_StoreOperation_Definitions */ -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef const *hrtc) { UNUSED(hrtc); return READ_BIT(RTC->CR, RTC_CR_BKP); @@ -1513,7 +1513,7 @@ HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alar * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) +HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef const *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format) { uint32_t tmpreg, subsecondtmpreg; @@ -1730,7 +1730,7 @@ HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t T * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef const *hrtc) { uint32_t tickstart; @@ -1775,7 +1775,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval HAL state */ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc) +HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef const *hrtc) { /* Return RTC handle state */ return hrtc->State; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc_ex.c index a1c4b5f5c3..14b89f4a2e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_rtc_ex.c @@ -359,7 +359,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc) * @arg RTC_FORMAT_BCD: BCD data format * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef const *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format) { uint32_t tmptime, tmpdate; @@ -740,7 +740,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval Counter value */ -uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc) +uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef const *hrtc) { UNUSED(hrtc); /* Get the counter value */ @@ -1311,7 +1311,7 @@ HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc) * @arg RTC_MONOTONIC_COUNTER_1 * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, uint32_t Instance) +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef const *hrtc, uint32_t Instance) { UNUSED(hrtc); UNUSED(Instance); @@ -1331,7 +1331,7 @@ HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterIncrement(RTC_HandleTypeDef *hrtc, u * @param Value Pointer to the counter monotonic counter value * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef *hrtc, uint32_t Instance, uint32_t *Value) +HAL_StatusTypeDef HAL_RTCEx_MonotonicCounterGet(RTC_HandleTypeDef const *hrtc, uint32_t Instance, uint32_t *Value) { UNUSED(hrtc); UNUSED(Instance); @@ -1446,7 +1446,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef const *hrtc, RTC_TamperTypeDef const *sTamper) { uint32_t tmpreg; @@ -1513,7 +1513,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef * @param sTamper Pointer to Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef *sTamper) +HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef const *hrtc, RTC_TamperTypeDef const *sTamper) { uint32_t tmpreg; @@ -1588,7 +1588,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperType * @arg RTC_TAMPER_8 * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper) +HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef const *hrtc, uint32_t Tamper) { UNUSED(hrtc); assert_param(IS_RTC_TAMPER(Tamper)); @@ -1614,7 +1614,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t T * @param sAllTamper Pointer to active Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef *sAllTamper) +HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_ActiveTampersTypeDef const *sAllTamper) { uint32_t IER, CR1, CR2, ATCR1, ATCR2, CR, i, tickstart; @@ -1724,7 +1724,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveTampers(RTC_HandleTypeDef *hrtc, RTC_Active * @param pSeed Pointer to active tamper seed values. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSeed) +HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t const *pSeed) { uint32_t i, tickstart; @@ -1758,7 +1758,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetActiveSeed(RTC_HandleTypeDef *hrtc, uint32_t *pSe * @param hrtc RTC handle * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) +HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef const *hrtc) { /* Get Active tampers */ uint32_t ATamp_mask = READ_BIT(TAMP->ATCR1, TAMP_ALL); @@ -1802,7 +1802,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateActiveTampers(RTC_HandleTypeDef *hrtc) * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t Tamper, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef const *hrtc, uint32_t Tamper, uint32_t Timeout) { UNUSED(hrtc); assert_param(IS_RTC_TAMPER(Tamper)); @@ -1834,7 +1834,7 @@ HAL_StatusTypeDef HAL_RTCEx_PollForTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef const *hrtc, RTC_InternalTamperTypeDef const *sIntTamper) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -1871,7 +1871,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper(RTC_HandleTypeDef *hrtc, RTC_Inter * @param sIntTamper Pointer to Internal Tamper Structure. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_InternalTamperTypeDef *sIntTamper) +HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef const *hrtc, RTC_InternalTamperTypeDef const *sIntTamper) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -1914,7 +1914,7 @@ HAL_StatusTypeDef HAL_RTCEx_SetInternalTamper_IT(RTC_HandleTypeDef *hrtc, RTC_In * This parameter can be any combination of existing internal tampers. * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, uint32_t IntTamper) +HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef const *hrtc, uint32_t IntTamper) { UNUSED(hrtc); assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); @@ -1940,7 +1940,7 @@ HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTamper(RTC_HandleTypeDef *hrtc, ui * @param Timeout Timeout duration * @retval HAL status */ -HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef *hrtc, uint32_t IntTamper, uint32_t Timeout) +HAL_StatusTypeDef HAL_RTCEx_PollForInternalTamperEvent(RTC_HandleTypeDef const *hrtc, uint32_t IntTamper, uint32_t Timeout) { UNUSED(hrtc); assert_param(IS_RTC_INTERNAL_TAMPER(IntTamper)); @@ -2514,7 +2514,7 @@ __weak void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef const *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -2526,7 +2526,7 @@ void HAL_RTCEx_EnableTemperatureMonitoring(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef const *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -2538,7 +2538,7 @@ void HAL_RTCEx_DisableTemperatureMonitoring(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef const *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -2550,7 +2550,7 @@ void HAL_RTCEx_EnableVoltageMonitoring(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef const *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -2563,7 +2563,7 @@ void HAL_RTCEx_DisableVoltageMonitoring(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef const *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -2576,7 +2576,7 @@ void HAL_RTCEx_EnableWUTMonitoring(RTC_HandleTypeDef *hrtc) * @param hrtc RTC handle * @retval None */ -void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc) +void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef const *hrtc) { /* Prevent unused argument(s) compilation warning */ UNUSED(hrtc); @@ -2617,7 +2617,7 @@ void HAL_RTCEx_DisableWUTMonitoring(RTC_HandleTypeDef *hrtc) * @param Data Data to be written in the specified Backup data register. * @retval None */ -void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data) +void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef const *hrtc, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -2640,7 +2640,7 @@ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint3 * This parameter can be RTC_BKP_DRx where x can be from 0 to RTC_BACKUP_NB * @retval Read value */ -uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) +uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef const *hrtc, uint32_t BackupRegister) { uint32_t tmp; @@ -2681,7 +2681,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister) * @param secureState Secure state * @retval HAL_StatusTypeDef */ -HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) +HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef const *hrtc, RTC_SecureStateTypeDef *secureState) { UNUSED(hrtc); /* Read registers */ @@ -2714,7 +2714,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeGet(RTC_HandleTypeDef *hrtc, RTC_SecureSta * @param secureState Secure state * @retval HAL_StatusTypeDef */ -HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureStateTypeDef *secureState) +HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef const *hrtc, RTC_SecureStateTypeDef const *secureState) { UNUSED(hrtc); assert_param(IS_RTC_SECURE_FULL(secureState->rtcSecureFull)); @@ -2763,7 +2763,7 @@ HAL_StatusTypeDef HAL_RTCEx_SecureModeSet(RTC_HandleTypeDef *hrtc, RTC_SecureSta * @param privilegeState Privilege state * @retval HAL_StatusTypeDef */ -HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef const *hrtc, RTC_PrivilegeStateTypeDef const *privilegeState) { UNUSED(hrtc); assert_param(IS_RTC_PRIVILEGE_FULL(privilegeState->rtcPrivilegeFull)); @@ -2799,7 +2799,7 @@ HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeSet(RTC_HandleTypeDef *hrtc, RTC_Privil * @param privilegeState Privilege state * @retval HAL_StatusTypeDef */ -HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) +HAL_StatusTypeDef HAL_RTCEx_PrivilegeModeGet(RTC_HandleTypeDef const *hrtc, RTC_PrivilegeStateTypeDef *privilegeState) { /* Read registers */ uint32_t rtc_privcr = READ_REG(RTC->PRIVCR); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c index 4b9279fde7..49c1ff5bc6 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sd.c @@ -469,7 +469,7 @@ HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd) HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) { uint32_t errorstate; - SD_InitTypeDef Init; + SD_InitTypeDef Init = {0U}; uint32_t sdmmc_clk; /* Default SDMMC peripheral configuration for SD card initialization */ @@ -486,7 +486,14 @@ HAL_StatusTypeDef HAL_SD_InitCard(SD_HandleTypeDef *hsd) hsd->ErrorCode = SDMMC_ERROR_INVALID_PARAMETER; return HAL_ERROR; } - Init.ClockDiv = sdmmc_clk / (2U * SD_INIT_FREQ); + if (sdmmc_clk <= SD_INIT_FREQ) + { + Init.ClockDiv = 0U; + } + else + { + Init.ClockDiv = (sdmmc_clk / (2U * SD_INIT_FREQ)) + 1U; + } #if (USE_SD_TRANSCEIVER != 0U) Init.TranceiverPresent = hsd->Init.TranceiverPresent; @@ -2154,7 +2161,7 @@ HAL_StatusTypeDef HAL_SD_UnRegisterTransceiverCallback(SD_HandleTypeDef *hsd) * contains all CID register parameters * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardCID(SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) +HAL_StatusTypeDef HAL_SD_GetCardCID(const SD_HandleTypeDef *hsd, HAL_SD_CardCIDTypeDef *pCID) { pCID->ManufacturerID = (uint8_t)((hsd->CID[0] & 0xFF000000U) >> 24U); @@ -2370,7 +2377,7 @@ HAL_StatusTypeDef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusT * will contain the SD card status information * @retval HAL status */ -HAL_StatusTypeDef HAL_SD_GetCardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) +HAL_StatusTypeDef HAL_SD_GetCardInfo(const SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypeDef *pCardInfo) { pCardInfo->CardType = (uint32_t)(hsd->SdCard.CardType); pCardInfo->CardVersion = (uint32_t)(hsd->SdCard.CardVersion); @@ -3149,7 +3156,7 @@ static uint32_t SD_PowerON(SD_HandleTypeDef *hsd) /* CMD8: SEND_IF_COND: Command available only on V2.0 cards */ errorstate = SDMMC_CmdOperCond(hsd->Instance); - if (errorstate == SDMMC_ERROR_TIMEOUT) /* No response to CMD8 */ + if (errorstate == SDMMC_ERROR_CMD_RSP_TIMEOUT) /* No response to CMD8 */ { hsd->SdCard.CardVersion = CARD_V1_X; /* CMD0: GO_IDLE_STATE */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c index e3e88b3f62..e6a60fde49 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_smbus.c @@ -1543,55 +1543,50 @@ HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t /* Wait until STOPF flag is reset */ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) { - return HAL_ERROR; + /* A non acknowledge appear during STOP Flag waiting process, a new trial must be performed */ + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + + /* Reset the error code for next trial */ + hsmbus->ErrorCode = HAL_SMBUS_ERROR_NONE; } + else + { + /* A acknowledge appear during STOP Flag waiting process, this mean that device respond to its address */ - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); + /* Clear STOP Flag */ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - /* Device is ready */ - hsmbus->State = HAL_SMBUS_STATE_READY; + /* Device is ready */ + hsmbus->State = HAL_SMBUS_STATE_READY; - /* Process Unlocked */ - __HAL_UNLOCK(hsmbus); + /* Process Unlocked */ + __HAL_UNLOCK(hsmbus); - return HAL_OK; + return HAL_OK; + } } else { - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) - { - return HAL_ERROR; - } + /* A non acknowledge is detected, this mean that device not respond to its address, + a new trial must be performed */ /* Clear NACK Flag */ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF); - /* Clear STOP Flag, auto generated with autoend*/ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); - } - - /* Check if the maximum allowed number of trials has been reached */ - if (SMBUS_Trials == Trials) - { - /* Generate Stop */ - hsmbus->Instance->CR2 |= I2C_CR2_STOP; - /* Wait until STOPF flag is reset */ - if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK) + if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) == HAL_OK) { - return HAL_ERROR; + /* Clear STOP Flag, auto generated with autoend*/ + __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } - - /* Clear STOP Flag */ - __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF); } /* Increment Trials */ SMBUS_Trials++; } while (SMBUS_Trials < Trials); + /* Update SMBUS state */ hsmbus->State = HAL_SMBUS_STATE_READY; /* Update SMBUS error code */ @@ -1959,7 +1954,7 @@ static HAL_StatusTypeDef SMBUS_Master_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; @@ -2387,7 +2382,7 @@ static HAL_StatusTypeDef SMBUS_Slave_ISR(SMBUS_HandleTypeDef *hsmbus, uint32_t S /* Increment Buffer pointer */ hsmbus->pBuffPtr++; - if ((hsmbus->XferSize > 0U)) + if (hsmbus->XferSize > 0U) { hsmbus->XferSize--; hsmbus->XferCount--; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c index 12c3b4d215..7422eeb933 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_spi.c @@ -44,7 +44,8 @@ (+++) Configure the DMA handle parameters (+++) Configure the DMA Tx or Rx Stream/Channel (+++) Associate the initialized hdma_tx(or _rx) handle to the hspi DMA Tx or Rx handle - (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Stream/Channel + (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx + or Rx Stream/Channel (#) Program the Mode, BidirectionalMode , Data size, Baudrate Prescaler, NSS management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure. @@ -190,7 +191,8 @@ @note The max SPI frequency depend on SPI data size (4bits, 5bits,..., 8bits,...15bits, 16bits), SPI mode(2 Lines fullduplex, 2 lines RxOnly, 1 line TX/RX) and Process mode (Polling, IT, DMA). @note - (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and HAL_SPI_TransmitReceive_DMA() + (#) TX/RX processes are HAL_SPI_TransmitReceive(), HAL_SPI_TransmitReceive_IT() and + HAL_SPI_TransmitReceive_DMA() (#) RX processes are HAL_SPI_Receive(), HAL_SPI_Receive_IT() and HAL_SPI_Receive_DMA() (#) TX processes are HAL_SPI_Transmit(), HAL_SPI_Transmit_IT() and HAL_SPI_Transmit_DMA() @@ -813,43 +815,40 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @brief Transmit an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout) { uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; uint16_t initial_TxXferCount; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); initial_TxXferCount = Size; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -888,7 +887,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -898,7 +897,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Wait until TXE flag is set to send data */ if (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; } @@ -907,9 +906,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -922,13 +921,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr ++; hspi->TxXferCount--; } @@ -941,13 +940,13 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint if (hspi->TxXferCount > 1U) { /* write on the data register in packing mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *((__IO uint8_t *)&hspi->Instance->DR) = (*hspi->pTxBuffPtr); + *((__IO uint8_t *)&hspi->Instance->DR) = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -957,9 +956,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -984,29 +983,31 @@ HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint __HAL_SPI_CLEAR_OVRFLAG(hspi); } + hspi->State = HAL_SPI_STATE_READY; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be received - * @param Timeout Timeout duration + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received + * @param Timeout Timeout duration in ms * @retval HAL status + * @note In master mode, if the direction is set to SPI_DIRECTION_2LINES + * the receive buffer is written to data register (DR) to generate + * clock pulses and receive data */ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout) { @@ -1016,12 +1017,15 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 __IO uint8_t tmpreg8 = 0; #endif /* USE_SPI_CRC */ uint32_t tickstart; - HAL_StatusTypeDef errorcode = HAL_OK; if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES)) @@ -1031,17 +1035,11 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout); } - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } + /* Process Locked */ + __HAL_LOCK(hspi); /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; @@ -1113,9 +1111,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1137,9 +1135,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 /* Timeout management */ if ((((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1156,8 +1154,8 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { /* the latest data has not been received */ - errorcode = HAL_TIMEOUT; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Receive last data in 16 Bit mode */ @@ -1175,8 +1173,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 if (SPI_WaitFlagStateUntilTimeout(hspi, SPI_FLAG_RXNE, SET, Timeout, tickstart) != HAL_OK) { SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC to Flush DR and RXNE flag */ @@ -1202,8 +1201,9 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1229,32 +1229,31 @@ HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint1 } #endif /* USE_SPI_CRC */ + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit and Receive an amount of data in blocking mode. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received - * @param Timeout Timeout duration + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received + * @param Timeout Timeout duration in ms * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout) +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout) { uint16_t initial_TxXferCount; uint16_t initial_RxXferCount; @@ -1271,14 +1270,10 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Variable used to alternate Rx and Tx during transfer */ uint32_t txallowed = 1U; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - /* Init tickstart for timeout management*/ tickstart = HAL_GetTick(); @@ -1293,18 +1288,20 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD #endif /* USE_SPI_CRC */ if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -1316,7 +1313,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD hspi->pRxBuffPtr = (uint8_t *)pRxData; hspi->RxXferCount = Size; hspi->RxXferSize = Size; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferCount = Size; hspi->TxXferSize = Size; @@ -1356,7 +1353,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if ((hspi->Init.Mode == SPI_MODE_SLAVE) || (initial_TxXferCount == 0x01U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -1379,7 +1376,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD /* Check TXE flag */ if ((__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE)) && (hspi->TxXferCount > 0U) && (txallowed == 1U)) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; /* Next Data is a reception (Rx). Tx not allowed */ @@ -1410,9 +1407,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if (((HAL_GetTick() - tickstart) >= Timeout) && (Timeout != HAL_MAX_DELAY)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1423,13 +1420,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -1454,13 +1451,13 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { if (hspi->TxXferCount > 1U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -1506,9 +1503,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD } if ((((HAL_GetTick() - tickstart) >= Timeout) && ((Timeout != HAL_MAX_DELAY))) || (Timeout == 0U)) { - errorcode = HAL_TIMEOUT; hspi->State = HAL_SPI_STATE_READY; - goto error; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } } } @@ -1522,8 +1519,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read CRC */ if (hspi->Init.DataSize == SPI_DATASIZE_16BIT) @@ -1548,8 +1546,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); - errorcode = HAL_TIMEOUT; - goto error; + hspi->State = HAL_SPI_STATE_READY; + __HAL_UNLOCK(hspi); + return HAL_TIMEOUT; } /* Read 8bit CRC again in case of 16bit CRC in 8bit Data mode */ tmpreg8 = *ptmpreg8; @@ -1565,43 +1564,44 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxD SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); /* Clear CRC Flag */ __HAL_SPI_CLEAR_CRCERRFLAG(hspi); - - errorcode = HAL_ERROR; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } #endif /* USE_SPI_CRC */ /* Check the end of the transaction */ if (SPI_EndRxTxTransaction(hspi, Timeout, tickstart) != HAL_OK) { - errorcode = HAL_ERROR; hspi->ErrorCode = HAL_SPI_ERROR_FLAG; + __HAL_UNLOCK(hspi); + return HAL_ERROR; } + + hspi->State = HAL_SPI_STATE_READY; + /* Unlock the process */ + __HAL_UNLOCK(hspi); + if (hspi->ErrorCode != HAL_SPI_ERROR_NONE) { - errorcode = HAL_ERROR; + return HAL_ERROR; } else { - hspi->State = HAL_SPI_STATE_READY; + return HAL_OK; } - -error : - __HAL_UNLOCK(hspi); - return errorcode; } /** * @brief Transmit an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); @@ -1609,14 +1609,12 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } /* Process Locked */ @@ -1625,7 +1623,7 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1673,27 +1671,28 @@ HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Enable TXE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -1704,12 +1703,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui } - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Process Locked */ __HAL_LOCK(hspi); @@ -1781,24 +1774,23 @@ HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, ui /* Enable RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer - * @param Size amount of data to be sent and received + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); @@ -1808,16 +1800,15 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || \ - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } /* Process locked */ @@ -1831,7 +1822,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -1892,21 +1883,19 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *p /* Enable TXE, RXNE and ERR interrupt */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR)); -error : - return errorcode; + return HAL_OK; } /** * @brief Transmit an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer - * @param Size amount of data to be sent + * @param pData pointer to data buffer (u8 or u16 data elements) + * @param Size amount of data elements (u8 or u16) to be sent * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; /* Check tx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmatx)); @@ -1914,25 +1903,23 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction)); - /* Process Locked */ - __HAL_LOCK(hspi); - if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process Locked */ + __HAL_LOCK(hspi); + /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_TX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pData; + hspi->pTxBuffPtr = (const uint8_t *)pData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; @@ -1994,9 +1981,9 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2006,16 +1993,16 @@ HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2023,22 +2010,24 @@ error : * @note In case of MASTER mode and SPI_DIRECTION_2LINES direction, hdmatx shall be defined. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pData pointer to data buffer + * @param pData pointer to data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pData Length must be Size + 1. - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be received * @retval HAL status */ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size) { - HAL_StatusTypeDef errorcode = HAL_OK; - /* Check rx dma handle */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); if (hspi->State != HAL_SPI_STATE_READY) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; + } + + if ((pData == NULL) || (Size == 0U)) + { + return HAL_ERROR; } if ((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER)) @@ -2055,12 +2044,6 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u /* Process Locked */ __HAL_LOCK(hspi); - if ((pData == NULL) || (Size == 0U)) - { - errorcode = HAL_ERROR; - goto error; - } - /* Set the transaction information */ hspi->State = HAL_SPI_STATE_BUSY_RX; hspi->ErrorCode = HAL_SPI_ERROR_NONE; @@ -2138,9 +2121,9 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2150,34 +2133,33 @@ HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, u __HAL_SPI_ENABLE(hspi); } + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Rx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN); -error: - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** * @brief Transmit and Receive an amount of data in non-blocking mode with DMA. * @param hspi pointer to a SPI_HandleTypeDef structure that contains * the configuration information for SPI module. - * @param pTxData pointer to transmission data buffer - * @param pRxData pointer to reception data buffer + * @param pTxData pointer to transmission data buffer (u8 or u16 data elements) + * @param pRxData pointer to reception data buffer (u8 or u16 data elements) * @note When the CRC feature is enabled the pRxData Length must be Size + 1 - * @param Size amount of data to be sent + * @param Size amount of data elements (u8 or u16) to be sent and received * @retval HAL status */ -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size) { uint32_t tmp_mode; HAL_SPI_StateTypeDef tmp_state; - HAL_StatusTypeDef errorcode = HAL_OK; /* Check rx & tx dma handles */ assert_param(IS_SPI_DMA_HANDLE(hspi->hdmarx)); @@ -2186,26 +2168,25 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Check Direction parameter */ assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction)); - /* Process locked */ - __HAL_LOCK(hspi); - /* Init temporary variables */ tmp_state = hspi->State; tmp_mode = hspi->Init.Mode; if (!((tmp_state == HAL_SPI_STATE_READY) || - ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (tmp_state == HAL_SPI_STATE_BUSY_RX)))) + ((tmp_mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && + (tmp_state == HAL_SPI_STATE_BUSY_RX)))) { - errorcode = HAL_BUSY; - goto error; + return HAL_BUSY; } if ((pTxData == NULL) || (pRxData == NULL) || (Size == 0U)) { - errorcode = HAL_ERROR; - goto error; + return HAL_ERROR; } + /* Process locked */ + __HAL_LOCK(hspi); + /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */ if (hspi->State != HAL_SPI_STATE_BUSY_RX) { @@ -2214,7 +2195,7 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Set the transaction information */ hspi->ErrorCode = HAL_SPI_ERROR_NONE; - hspi->pTxBuffPtr = (uint8_t *)pTxData; + hspi->pTxBuffPtr = (const uint8_t *)pTxData; hspi->TxXferSize = Size; hspi->TxXferCount = Size; hspi->pRxBuffPtr = (uint8_t *)pRxData; @@ -2305,9 +2286,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Enable Rx DMA Request */ @@ -2326,9 +2307,9 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * { /* Update SPI error code */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA); - errorcode = HAL_ERROR; - - goto error; + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + return HAL_ERROR; } /* Check if the SPI is already enabled */ @@ -2337,16 +2318,17 @@ HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t * /* Enable SPI peripheral */ __HAL_SPI_ENABLE(hspi); } + + /* Process Unlocked */ + __HAL_UNLOCK(hspi); + /* Enable the SPI Error Interrupt Bit */ __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_ERR)); /* Enable Tx DMA Request */ SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN); -error : - /* Process Unlocked */ - __HAL_UNLOCK(hspi); - return errorcode; + return HAL_OK; } /** @@ -2439,7 +2421,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2472,7 +2455,8 @@ HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -2727,9 +2711,11 @@ HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi) { HAL_StatusTypeDef errorcode = HAL_OK; /* The Lock is not implemented on this API to allow the user application - to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback(): + to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback(): when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated - and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback() + and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or + HAL_SPI_TxRxCpltCallback() */ /* Abort the SPI DMA tx Stream/Channel */ @@ -3019,7 +3005,7 @@ __weak void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI state */ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi) { /* Return SPI handle state */ return hspi->State; @@ -3031,7 +3017,7 @@ HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi) * the configuration information for SPI module. * @retval SPI error code in bitmap format */ -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi) { /* Return SPI ErrorCode */ return hspi->ErrorCode; @@ -3058,7 +3044,7 @@ uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi) */ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; /* Init tickstart for timeout management*/ @@ -3115,7 +3101,7 @@ static void SPI_DMATransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3232,7 +3218,7 @@ static void SPI_DMAReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); uint32_t tickstart; #if (USE_SPI_CRC != 0U) __IO uint32_t tmpreg = 0U; @@ -3270,7 +3256,8 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) } else { - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, tickstart) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_HALF_FULL, SPI_DEFAULT_TIMEOUT, + tickstart) != HAL_OK) { /* Error on the CRC reception */ SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC); @@ -3332,7 +3319,7 @@ static void SPI_DMATransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Tx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3350,7 +3337,7 @@ static void SPI_DMAHalfTransmitCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user Rx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3368,7 +3355,7 @@ static void SPI_DMAHalfReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Call user TxRx half complete callback */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) @@ -3386,7 +3373,7 @@ static void SPI_DMAHalfTransmitReceiveCplt(DMA_HandleTypeDef *hdma) */ static void SPI_DMAError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Stop the disable DMA transfer on SPI side */ CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN | SPI_CR2_RXDMAEN); @@ -3409,7 +3396,7 @@ static void SPI_DMAError(DMA_HandleTypeDef *hdma) */ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->RxXferCount = 0U; hspi->TxXferCount = 0U; @@ -3431,7 +3418,7 @@ static void SPI_DMAAbortOnError(DMA_HandleTypeDef *hdma) */ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); hspi->hdmatx->XferAbortCallback = NULL; @@ -3447,7 +3434,8 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3497,7 +3485,7 @@ static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma) */ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) { - SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Derogation MISRAC2012-Rule-11.5 */ + SPI_HandleTypeDef *hspi = (SPI_HandleTypeDef *)(((DMA_HandleTypeDef *)hdma)->Parent); /* Disable SPI Peripheral */ __HAL_SPI_DISABLE(hspi); @@ -3514,7 +3502,8 @@ static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -3650,14 +3639,14 @@ static void SPI_2linesTxISR_8BIT(struct __SPI_HandleTypeDef *hspi) /* Transmit data in packing Bit mode */ if (hspi->TxXferCount >= 2U) { - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount -= 2U; } /* Transmit data in 8 Bit mode */ else { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; } @@ -3751,7 +3740,7 @@ static void SPI_2linesRxISR_16BITCRC(struct __SPI_HandleTypeDef *hspi) static void SPI_2linesTxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -3904,7 +3893,7 @@ static void SPI_RxISR_16BIT(struct __SPI_HandleTypeDef *hspi) */ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) { - *(__IO uint8_t *)&hspi->Instance->DR = (*hspi->pTxBuffPtr); + *(__IO uint8_t *)&hspi->Instance->DR = *((const uint8_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr++; hspi->TxXferCount--; @@ -3930,7 +3919,7 @@ static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi) static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi) { /* Transmit data in 16 Bit mode */ - hspi->Instance->DR = *((uint16_t *)hspi->pTxBuffPtr); + hspi->Instance->DR = *((const uint16_t *)hspi->pTxBuffPtr); hspi->pTxBuffPtr += sizeof(uint16_t); hspi->TxXferCount--; @@ -4009,7 +3998,10 @@ static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4032,7 +4024,7 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, __IO uint32_t count; uint32_t tmp_timeout; uint32_t tmp_tickstart; - __IO uint8_t *ptmpreg8; + __IO const uint8_t *ptmpreg8; __IO uint8_t tmpreg8 = 0; /* Adjust Timeout value in case of end of transfer */ @@ -4091,7 +4083,10 @@ static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, { tmp_timeout = 0U; } - count--; + else + { + count--; + } } } @@ -4387,7 +4382,8 @@ static void SPI_AbortRx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4430,7 +4426,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) __HAL_SPI_DISABLE(hspi); /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } @@ -4459,7 +4456,8 @@ static void SPI_AbortTx_ISR(SPI_HandleTypeDef *hspi) } /* Empty the FRLVL fifo */ - if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, HAL_GetTick()) != HAL_OK) + if (SPI_WaitFifoStateUntilTimeout(hspi, SPI_FLAG_FRLVL, SPI_FRLVL_EMPTY, SPI_DEFAULT_TIMEOUT, + HAL_GetTick()) != HAL_OK) { hspi->ErrorCode = HAL_SPI_ERROR_ABORT; } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c index 77951fb06a..629bbf9925 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_sram.c @@ -1037,6 +1037,7 @@ HAL_SRAM_StateTypeDef HAL_SRAM_GetState(const SRAM_HandleTypeDef *hsram) */ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1059,6 +1060,7 @@ static void SRAM_DMACplt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ @@ -1081,6 +1083,7 @@ static void SRAM_DMACpltProt(DMA_HandleTypeDef *hdma) */ static void SRAM_DMAError(DMA_HandleTypeDef *hdma) { + /* Derogation MISRAC2012-Rule-11.5 */ SRAM_HandleTypeDef *hsram = (SRAM_HandleTypeDef *)(hdma->Parent); /* Disable the DMA channel */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c index 5b35a84848..ed1d6e599c 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim.c @@ -4577,7 +4577,6 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t ((BurstLength) >> 8U) + 1U); - return status; } @@ -6946,8 +6945,6 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure /* Set the auto-reload preload */ MODIFY_REG(tmpcr1, TIM_CR1_ARPE, Structure->AutoReloadPreload); - TIMx->CR1 = tmpcr1; - /* Set the Autoreload value */ TIMx->ARR = (uint32_t)Structure->Period ; @@ -6960,16 +6957,15 @@ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, const TIM_Base_InitTypeDef *Structure TIMx->RCR = Structure->RepetitionCounter; } + /* Disable Update Event (UEV) with Update Generation (UG) + by changing Update Request Source (URS) to avoid Update flag (UIF) */ + SET_BIT(TIMx->CR1, TIM_CR1_URS); + /* Generate an update event to reload the Prescaler and the repetition counter (only for advanced timer) value immediately */ TIMx->EGR = TIM_EGR_UG; - /* Check if the update flag is set after the Update Generation, if so clear the UIF flag */ - if (HAL_IS_BIT_SET(TIMx->SR, TIM_FLAG_UPDATE)) - { - /* Clear the update flag */ - CLEAR_BIT(TIMx->SR, TIM_FLAG_UPDATE); - } + TIMx->CR1 = tmpcr1; } /** @@ -7012,12 +7008,13 @@ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co /* Check parameters */ assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 1N: Reset the CC1NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC1NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC1NP; /* Set the Output N Polarity */ tmpccer |= OC_Config->OCNPolarity; - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC1NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7088,12 +7085,13 @@ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Config) { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 2N: Reset the CC2NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC2NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC2NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 4U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC2NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7163,12 +7161,13 @@ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, const TIM_OC_InitTypeDef *OC_Co { assert_param(IS_TIM_OCN_POLARITY(OC_Config->OCNPolarity)); + /* Disable the Channel 3N: Reset the CC3NE Bit */ + TIMx->CCER &= ~TIM_CCER_CC3NE; + /* Reset the Output N Polarity level */ tmpccer &= ~TIM_CCER_CC3NP; /* Set the Output N Polarity */ tmpccer |= (OC_Config->OCNPolarity << 8U); - /* Reset the Output N State */ - tmpccer &= ~TIM_CCER_CC3NE; } if (IS_TIM_BREAK_INSTANCE(TIMx)) @@ -7515,9 +7514,18 @@ void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7561,9 +7569,18 @@ static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 1: Reset the CC1E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 1: Reset the CC1E Bit */ TIMx->CCER &= ~TIM_CCER_CC1E; + /* Disable the Channel 1N: Reset the CC1NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_1)) + { + TIMx->CCER &= ~TIM_CCER_CC1NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7605,9 +7622,18 @@ static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Select the Input */ @@ -7644,9 +7670,18 @@ static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t tmpccmr1; uint32_t tmpccer; - /* Disable the Channel 2: Reset the CC2E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 2: Reset the CC2E Bit */ TIMx->CCER &= ~TIM_CCER_CC2E; + /* Disable the Channel 2N: Reset the CC2NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_2)) + { + TIMx->CCER &= ~TIM_CCER_CC2NE; + } + + /* Get the TIMx CCMR1 register value */ tmpccmr1 = TIMx->CCMR1; /* Set the filter */ @@ -7688,9 +7723,18 @@ static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 3: Reset the CC3E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 3: Reset the CC3E Bit */ TIMx->CCER &= ~TIM_CCER_CC3E; + /* Disable the Channel 3N: Reset the CC3NE Bit */ + if (IS_TIM_CCXN_INSTANCE(TIMx, TIM_CHANNEL_3)) + { + TIMx->CCER &= ~TIM_CCER_CC3NE; + } + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7736,9 +7780,13 @@ static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32 uint32_t tmpccmr2; uint32_t tmpccer; - /* Disable the Channel 4: Reset the CC4E Bit */ + /* Get the TIMx CCER register value */ tmpccer = TIMx->CCER; + + /* Disable the Channel 4: Reset the CC4E Bit */ TIMx->CCER &= ~TIM_CCER_CC4E; + + /* Get the TIMx CCMR2 register value */ tmpccmr2 = TIMx->CCMR2; /* Select the Input */ @@ -7825,10 +7873,10 @@ void TIM_ETR_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ExtTRGPrescaler, * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 - * @arg TIM_CHANNEL_4: TIM Channel 4 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected + * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @arg TIM_CHANNEL_5: TIM Channel 5 selected * @arg TIM_CHANNEL_6: TIM Channel 6 selected * @param ChannelState specifies the TIM Channel CCxE bit new state. diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c index f65c6888f8..086a0bb91f 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_tim_ex.c @@ -2626,9 +2626,9 @@ HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(const TIM_HandleTypeDef *htim * @param htim TIM handle * @param ChannelN TIM Complementary channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @retval TIM Complementary channel state */ HAL_TIM_ChannelStateTypeDef HAL_TIMEx_GetChannelNState(const TIM_HandleTypeDef *htim, uint32_t ChannelN) @@ -2787,9 +2787,9 @@ static void TIM_DMAErrorCCxN(DMA_HandleTypeDef *hdma) * @param TIMx to select the TIM peripheral * @param Channel specifies the TIM Channel * This parameter can be one of the following values: - * @arg TIM_CHANNEL_1: TIM Channel 1 - * @arg TIM_CHANNEL_2: TIM Channel 2 - * @arg TIM_CHANNEL_3: TIM Channel 3 + * @arg TIM_CHANNEL_1: TIM Channel 1 selected + * @arg TIM_CHANNEL_2: TIM Channel 2 selected + * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_timebase_tim_template.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_timebase_tim_template.c index 882e36af83..9c2192c651 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_timebase_tim_template.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_timebase_tim_template.c @@ -116,6 +116,11 @@ HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) TimHandle.Init.AutoReloadPreload = TIM_AUTORELOAD_PRELOAD_DISABLE; if (HAL_TIM_Base_Init(&TimHandle) == HAL_OK) { +#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1U) + /* Register callback */ + HAL_TIM_RegisterCallback(&TimHandle, HAL_TIM_PERIOD_ELAPSED_CB_ID, TimeBase_TIM_PeriodElapsedCallback); +#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */ + /* Start the TIM time Base generation in interrupt mode */ if (HAL_TIM_Base_Start_IT(&TimHandle) == HAL_OK) { diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c index 7b5907a0ac..063528315e 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart.c @@ -1022,75 +1022,79 @@ HAL_StatusTypeDef HAL_UART_UnRegisterRxEventCallback(UART_HandleTypeDef *huart) =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of functions allowing to manage the UART asynchronous and Half duplex data transfers. - (#) There are two mode of transfer: - (+) Blocking mode: The communication is performed in polling mode. - The HAL status of all data processing is returned by the same function - after finishing transfer. - (+) Non-Blocking mode: The communication is performed using Interrupts - or DMA, These API's return the HAL status. - The end of the data processing will be indicated through the - dedicated UART IRQ when using Interrupt mode or the DMA IRQ when - using DMA mode. - The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks - will be executed respectively at the end of the transmit or Receive process - The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected + (#) There are two modes of transfer: + (++) Blocking mode: The communication is performed in polling mode. + The HAL status of all data processing is returned by the same function + after finishing transfer. + (++) Non-Blocking mode: The communication is performed using Interrupts + or DMA, These API's return the HAL status. + The end of the data processing will be indicated through the + dedicated UART IRQ when using Interrupt mode or the DMA IRQ when + using DMA mode. + The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks + will be executed respectively at the end of the transmit or Receive process + The HAL_UART_ErrorCallback()user callback will be executed when a communication error is detected (#) Blocking mode API's are : - (+) HAL_UART_Transmit() - (+) HAL_UART_Receive() + (++) HAL_UART_Transmit() + (++) HAL_UART_Receive() (#) Non-Blocking mode API's with Interrupt are : - (+) HAL_UART_Transmit_IT() - (+) HAL_UART_Receive_IT() - (+) HAL_UART_IRQHandler() + (++) HAL_UART_Transmit_IT() + (++) HAL_UART_Receive_IT() + (++) HAL_UART_IRQHandler() (#) Non-Blocking mode API's with DMA are : - (+) HAL_UART_Transmit_DMA() - (+) HAL_UART_Receive_DMA() - (+) HAL_UART_DMAPause() - (+) HAL_UART_DMAResume() - (+) HAL_UART_DMAStop() + (++) HAL_UART_Transmit_DMA() + (++) HAL_UART_Receive_DMA() + (++) HAL_UART_DMAPause() + (++) HAL_UART_DMAResume() + (++) HAL_UART_DMAStop() (#) A set of Transfer Complete Callbacks are provided in Non_Blocking mode: - (+) HAL_UART_TxHalfCpltCallback() - (+) HAL_UART_TxCpltCallback() - (+) HAL_UART_RxHalfCpltCallback() - (+) HAL_UART_RxCpltCallback() - (+) HAL_UART_ErrorCallback() + (++) HAL_UART_TxHalfCpltCallback() + (++) HAL_UART_TxCpltCallback() + (++) HAL_UART_RxHalfCpltCallback() + (++) HAL_UART_RxCpltCallback() + (++) HAL_UART_ErrorCallback() (#) Non-Blocking mode transfers could be aborted using Abort API's : - (+) HAL_UART_Abort() - (+) HAL_UART_AbortTransmit() - (+) HAL_UART_AbortReceive() - (+) HAL_UART_Abort_IT() - (+) HAL_UART_AbortTransmit_IT() - (+) HAL_UART_AbortReceive_IT() + (++) HAL_UART_Abort() + (++) HAL_UART_AbortTransmit() + (++) HAL_UART_AbortReceive() + (++) HAL_UART_Abort_IT() + (++) HAL_UART_AbortTransmit_IT() + (++) HAL_UART_AbortReceive_IT() (#) For Abort services based on interrupts (HAL_UART_Abortxxx_IT), a set of Abort Complete Callbacks are provided: - (+) HAL_UART_AbortCpltCallback() - (+) HAL_UART_AbortTransmitCpltCallback() - (+) HAL_UART_AbortReceiveCpltCallback() + (++) HAL_UART_AbortCpltCallback() + (++) HAL_UART_AbortTransmitCpltCallback() + (++) HAL_UART_AbortReceiveCpltCallback() (#) A Rx Event Reception Callback (Rx event notification) is available for Non_Blocking modes of enhanced reception services: - (+) HAL_UARTEx_RxEventCallback() + (++) HAL_UARTEx_RxEventCallback() + + (#) Wakeup from Stop mode Callback: + (++) HAL_UARTEx_WakeupCallback() (#) In Non-Blocking mode transfers, possible errors are split into 2 categories. Errors are handled as follows : - (+) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is - to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error - in Interrupt mode reception . - Received character is then retrieved and stored in Rx buffer, Error code is set to allow user - to identify error type, and HAL_UART_ErrorCallback() user callback is executed. - Transfer is kept ongoing on UART side. - If user wants to abort it, Abort services should be called by user. - (+) Error is considered as Blocking : Transfer could not be completed properly and is aborted. - This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. - Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() - user callback is executed. + (++) Error is considered as Recoverable and non blocking : Transfer could go till end, but error severity is + to be evaluated by user : this concerns Frame Error, Parity Error or Noise Error + in Interrupt mode reception . + Received character is then retrieved and stored in Rx buffer, Error code is set to allow user + to identify error type, and HAL_UART_ErrorCallback() user callback is executed. + Transfer is kept ongoing on UART side. + If user wants to abort it, Abort services should be called by user. + (++) Error is considered as Blocking : Transfer could not be completed properly and is aborted. + This concerns Overrun Error In Interrupt mode reception and all errors in DMA mode. + Error code is set to allow user to identify error type, and HAL_UART_ErrorCallback() + user callback is executed. -@- In the Half duplex communication, it is forbidden to run the transmit and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX can't be useful. @@ -1168,7 +1172,15 @@ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, const uint8_t *pD huart->Instance->TDR = (uint8_t)(*pdata8bits & 0xFFU); pdata8bits++; } - huart->TxXferCount--; + if ((huart->gState & HAL_UART_STATE_BUSY_TX) == HAL_UART_STATE_BUSY_TX) + { + huart->TxXferCount--; + } + else + { + /* Process was aborted during the transmission */ + return HAL_ERROR; + } } if (UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, tickstart, Timeout) != HAL_OK) @@ -1264,7 +1276,15 @@ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, ui *pdata8bits = (uint8_t)(huart->Instance->RDR & (uint8_t)uhMask); pdata8bits++; } - huart->RxXferCount--; + if (huart->RxState == HAL_UART_STATE_BUSY_RX) + { + huart->RxXferCount--; + } + else + { + /* Process was aborted during the reception */ + return HAL_ERROR; + } } /* At end of Rx process, restore huart->RxState to Ready */ @@ -1704,10 +1724,6 @@ HAL_StatusTypeDef HAL_UART_Abort(UART_HandleTypeDef *huart) } } - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1774,9 +1790,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit(UART_HandleTypeDef *huart) } } - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -1839,9 +1852,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive(UART_HandleTypeDef *huart) } } - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -1967,10 +1977,6 @@ HAL_StatusTypeDef HAL_UART_Abort_IT(UART_HandleTypeDef *huart) /* if no DMA abort complete callback execution is required => call user Abort Complete callback */ if (abortcplt == 1U) { - /* Reset Tx and Rx transfer counters */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Clear ISR function pointers */ huart->RxISR = NULL; huart->TxISR = NULL; @@ -2050,8 +2056,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2071,9 +2075,6 @@ HAL_StatusTypeDef HAL_UART_AbortTransmit_IT(UART_HandleTypeDef *huart) } else { - /* Reset Tx transfer counter */ - huart->TxXferCount = 0U; - /* Clear TxISR function pointers */ huart->TxISR = NULL; @@ -2147,9 +2148,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2175,9 +2173,6 @@ HAL_StatusTypeDef HAL_UART_AbortReceive_IT(UART_HandleTypeDef *huart) } else { - /* Reset Rx transfer counter */ - huart->RxXferCount = 0U; - /* Clear RxISR function pointer */ huart->pRxBuffPtr = NULL; @@ -2425,6 +2420,28 @@ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ } + else + { + /* If DMA is in Circular mode, Idle event is to be reported to user + even if occurring after a Transfer Complete event from DMA */ + if (nb_remaining_rx_data == huart->RxXferSize) + { + if (HAL_IS_BIT_SET(huart->hdmarx->Instance->CCR, DMA_CCR_CIRC)) + { + /* Initialize type of RxEvent that correspond to RxEvent callback execution; + In this case, Rx Event type is Idle Event */ + huart->RxEventType = HAL_UART_RXEVENT_IDLE; + +#if (USE_HAL_UART_REGISTER_CALLBACKS == 1) + /*Call registered Rx Event callback*/ + huart->RxEventCallback(huart, huart->RxXferSize); +#else + /*Call legacy weak Rx Event callback*/ + HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); +#endif /* (USE_HAL_UART_REGISTER_CALLBACKS) */ + } + } + } return; } else @@ -3610,8 +3627,6 @@ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->TxXferCount = 0U; - /* Disable the DMA transfer for transmit request by resetting the DMAT bit in the UART CR3 register */ ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_DMAT); @@ -3662,8 +3677,6 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) /* DMA Normal mode */ if (HAL_IS_BIT_CLR(hdma->Instance->CCR, DMA_CCR_CIRC)) { - huart->RxXferCount = 0U; - /* Disable PE and ERR (Frame error, noise error, overrun error) interrupts */ ATOMIC_CLEAR_BIT(huart->Instance->CR1, USART_CR1_PEIE); ATOMIC_CLEAR_BIT(huart->Instance->CR3, USART_CR3_EIE); @@ -3690,12 +3703,22 @@ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + /* Check current nb of data still to be received on DMA side. + DMA Normal mode, remaining nb of data will be 0 + DMA Circular mode, remaining nb of data is reset to RxXferSize */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data < huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3728,12 +3751,22 @@ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) If Reception till IDLE event has been selected : use Rx Event callback */ if (huart->ReceptionType == HAL_UART_RECEPTION_TOIDLE) { + huart->RxXferCount = huart->RxXferSize / 2U; + + /* Check current nb of data still to be received on DMA side. */ + uint16_t nb_remaining_rx_data = (uint16_t) __HAL_DMA_GET_COUNTER(hdma); + if (nb_remaining_rx_data <= huart->RxXferSize) + { + /* Update nb of remaining data */ + huart->RxXferCount = nb_remaining_rx_data; + } + #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered Rx Event callback*/ - huart->RxEventCallback(huart, huart->RxXferSize / 2U); + huart->RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #else /*Call legacy weak Rx Event callback*/ - HAL_UARTEx_RxEventCallback(huart, huart->RxXferSize / 2U); + HAL_UARTEx_RxEventCallback(huart, (huart->RxXferSize - huart->RxXferCount)); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } else @@ -3765,7 +3798,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAT)) && (gstate == HAL_UART_STATE_BUSY_TX)) { - huart->TxXferCount = 0U; UART_EndTxTransfer(huart); } @@ -3773,7 +3805,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) if ((HAL_IS_BIT_SET(huart->Instance->CR3, USART_CR3_DMAR)) && (rxstate == HAL_UART_STATE_BUSY_RX)) { - huart->RxXferCount = 0U; UART_EndRxTransfer(huart); } @@ -3797,8 +3828,6 @@ static void UART_DMAError(DMA_HandleTypeDef *hdma) static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->RxXferCount = 0U; - huart->TxXferCount = 0U; #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) /*Call registered error callback*/ @@ -3832,10 +3861,6 @@ static void UART_DMATxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3887,10 +3912,6 @@ static void UART_DMARxAbortCallback(DMA_HandleTypeDef *hdma) } } - /* No Abort process still ongoing : All DMA channels are aborted, call user Abort Complete callback */ - huart->TxXferCount = 0U; - huart->RxXferCount = 0U; - /* Reset errorCode */ huart->ErrorCode = HAL_UART_ERROR_NONE; @@ -3928,8 +3949,6 @@ static void UART_DMATxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)(hdma->Parent); - huart->TxXferCount = 0U; - /* Flush the whole TX FIFO (if needed) */ if (huart->FifoMode == UART_FIFOMODE_ENABLE) { @@ -3961,8 +3980,6 @@ static void UART_DMARxOnlyAbortCallback(DMA_HandleTypeDef *hdma) { UART_HandleTypeDef *huart = (UART_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent; - huart->RxXferCount = 0U; - /* Clear the Error flags in the ICR register */ __HAL_UART_CLEAR_FLAG(huart, UART_CLEAR_OREF | UART_CLEAR_NEF | UART_CLEAR_PEF | UART_CLEAR_FEF); @@ -4469,6 +4486,7 @@ static void UART_RxISR_8BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } @@ -4633,6 +4651,7 @@ static void UART_RxISR_16BIT_FIFOEN(UART_HandleTypeDef *huart) HAL_UART_RxCpltCallback(huart); #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ } + break; } } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c index d1b96667c6..525d2e037b 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_uart_ex.c @@ -24,7 +24,7 @@ ============================================================================== ##### UART peripheral extended features ##### ============================================================================== - + [..] (#) Declare a UART_HandleTypeDef handle structure. (#) For the UART RS485 Driver Enable mode, initialize the UART registers @@ -253,15 +253,13 @@ HAL_StatusTypeDef HAL_RS485Ex_Init(UART_HandleTypeDef *huart, uint32_t Polarity, =============================================================================== ##### IO operation functions ##### =============================================================================== + [..] This subsection provides a set of Wakeup and FIFO mode related callback functions. - (#) Wakeup from Stop mode Callback: - (+) HAL_UARTEx_WakeupCallback() - + (++) HAL_UARTEx_WakeupCallback() (#) TX/RX Fifos Callbacks: - (+) HAL_UARTEx_RxFifoFullCallback() - (+) HAL_UARTEx_TxFifoEmptyCallback() - + (++) HAL_UARTEx_RxFifoFullCallback() + (++) HAL_UARTEx_TxFifoEmptyCallback() @endverbatim * @{ */ @@ -341,19 +339,19 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) (#) Compared to standard reception services which only consider number of received data elements as reception completion criteria, these functions also consider additional events as triggers for updating reception status to caller : - (+) Detection of inactivity period (RX line has not been active for a given period). - (++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) + (++) Detection of inactivity period (RX line has not been active for a given period). + (+++) RX inactivity detected by IDLE event, i.e. RX line has been in idle state (normally high state) for 1 frame time, after last received byte. - (++) RX inactivity detected by RTO, i.e. line has been in idle state + (+++) RX inactivity detected by RTO, i.e. line has been in idle state for a programmable time, after last received byte. - (+) Detection that a specific character has been received. + (++) Detection that a specific character has been received. - (#) There are two mode of transfer: - (+) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, + (#) There are two modes of transfer: + (++) Blocking mode: The reception is performed in polling mode, until either expected number of data is received, or till IDLE event occurs. Reception is handled only during function execution. When function exits, no data reception could occur. HAL status and number of actually received data elements, are returned by function after finishing transfer. - (+) Non-Blocking mode: The reception is performed using Interrupts or DMA. + (++) Non-Blocking mode: The reception is performed using Interrupts or DMA. These API's return the HAL status. The end of the data processing will be indicated through the dedicated UART IRQ when using Interrupt mode or the DMA IRQ when using DMA mode. @@ -361,13 +359,13 @@ __weak void HAL_UARTEx_TxFifoEmptyCallback(UART_HandleTypeDef *huart) The HAL_UART_ErrorCallback()user callback will be executed when a reception error is detected. (#) Blocking mode API: - (+) HAL_UARTEx_ReceiveToIdle() + (++) HAL_UARTEx_ReceiveToIdle() (#) Non-Blocking mode API with Interrupt: - (+) HAL_UARTEx_ReceiveToIdle_IT() + (++) HAL_UARTEx_ReceiveToIdle_IT() (#) Non-Blocking mode API with DMA: - (+) HAL_UARTEx_ReceiveToIdle_DMA() + (++) HAL_UARTEx_ReceiveToIdle_DMA() @endverbatim * @{ @@ -576,7 +574,7 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart) /* Disable UART */ __HAL_UART_DISABLE(huart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); huart->FifoMode = UART_FIFOMODE_DISABLE; @@ -942,17 +940,15 @@ HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_ * Half Transfer, or Transfer Complete), this function allows to retrieve the Rx Event type that has lead * to Rx Event callback execution. * @note This function is expected to be called within the user implementation of Rx Event Callback, - * in order to provide the accurate value : - * In Interrupt Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one) - * In DMA Mode : - * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received) - * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received - * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed (nb of - * received data is lower than expected one). - * In DMA mode, RxEvent callback could be called several times; + * in order to provide the accurate value. + * @note In Interrupt Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA Mode: + * - HAL_UART_RXEVENT_TC : when Reception has been completed (expected nb of data has been received). + * - HAL_UART_RXEVENT_HT : when half of expected nb of data has been received. + * - HAL_UART_RXEVENT_IDLE : when Idle event occurred prior reception has been completed. + * @note In DMA mode, RxEvent callback could be called several times; * When DMA is configured in Normal Mode, HT event does not stop Reception process; * When DMA is configured in Circular Mode, HT, TC or IDLE events don't stop Reception process; * @param huart UART handle. diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart_ex.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart_ex.c index 7f22731974..6eabe264bb 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart_ex.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_usart_ex.c @@ -364,7 +364,7 @@ HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart) /* Disable USART */ __HAL_USART_DISABLE(husart); - /* Enable FIFO mode */ + /* Disable FIFO mode */ CLEAR_BIT(tmpcr1, USART_CR1_FIFOEN); husart->FifoMode = USART_FIFOMODE_DISABLE; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c index dffa0c3fe4..4b7f351cf4 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_hal_wwdg.c @@ -95,7 +95,7 @@ and a pointer to the user callback function. (+) Use function HAL_WWDG_UnRegisterCallback() to reset a callback to - the default weak (surcharged) function. HAL_WWDG_UnRegisterCallback() + the default weak function. HAL_WWDG_UnRegisterCallback() takes as parameters the HAL peripheral handle and the Callback ID. This function allows to reset following callbacks: (++) EwiCallback : callback for Early WakeUp Interrupt. @@ -103,14 +103,14 @@ [..] When calling HAL_WWDG_Init function, callbacks are reset to the - corresponding legacy weak (surcharged) functions: + corresponding legacy weak functions: HAL_WWDG_EarlyWakeupCallback() and HAL_WWDG_MspInit() only if they have not been registered before. [..] When compilation define USE_HAL_WWDG_REGISTER_CALLBACKS is set to 0 or not defined, the callback registering feature is not available - and weak (surcharged) callbacks are used. + and weak (overridden) callbacks are used. *** WWDG HAL driver macros list *** =================================== @@ -240,7 +240,7 @@ __weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg) #if (USE_HAL_WWDG_REGISTER_CALLBACKS == 1) /** * @brief Register a User WWDG Callback - * To be used instead of the weak (surcharged) predefined callback + * To be used instead of the weak (overridden) predefined callback * @param hwwdg WWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: @@ -282,7 +282,7 @@ HAL_StatusTypeDef HAL_WWDG_RegisterCallback(WWDG_HandleTypeDef *hwwdg, HAL_WWDG_ /** * @brief Unregister a WWDG Callback - * WWDG Callback is redirected to the weak (surcharged) predefined callback + * WWDG Callback is redirected to the weak (overridden) predefined callback * @param hwwdg WWDG handle * @param CallbackID ID of the callback to be registered * This parameter can be one of the following values: diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crs.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crs.c index c7477149fd..abde34e0a2 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crs.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_crs.c @@ -1,6 +1,6 @@ /** ****************************************************************************** - * @file stm32l5xx_ll_crs.h + * @file stm32l5xx_ll_crs.c * @author MCD Application Team * @brief CRS LL module driver. ****************************************************************************** @@ -15,6 +15,7 @@ * ****************************************************************************** */ + #if defined(USE_FULL_LL_DRIVER) /* Includes ------------------------------------------------------------------*/ @@ -61,7 +62,6 @@ ErrorStatus LL_CRS_DeInit(void) } - /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c index 37ccb8a184..94b9324332 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_fmc.c @@ -59,7 +59,7 @@ * @{ */ #if defined(HAL_NOR_MODULE_ENABLED) || defined(HAL_NAND_MODULE_ENABLED) \ - || defined(HAL_SRAM_MODULE_ENABLED) + || defined(HAL_SRAM_MODULE_ENABLED) /** @defgroup FMC_LL FMC Low Layer * @brief FMC driver modules @@ -171,7 +171,7 @@ * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_InitTypeDef *Init) + const FMC_NORSRAM_InitTypeDef *Init) { uint32_t flashaccess; uint32_t btcr_reg; @@ -359,7 +359,7 @@ HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank) { uint32_t tmpr; @@ -389,7 +389,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, /* Configure Clock division value (in NORSRAM bank 1) when continuous clock is enabled */ if (HAL_IS_BIT_SET(Device->BTCR[FMC_NORSRAM_BANK1], FMC_BCR1_CCLKEN)) { - tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FU) << FMC_BTRx_CLKDIV_Pos)); + tmpr = (uint32_t)(Device->BTCR[FMC_NORSRAM_BANK1 + 1U] & ~((0x0FUL) << FMC_BTRx_CLKDIV_Pos)); tmpr |= (uint32_t)(((Timing->CLKDivision) - 1U) << FMC_BTRx_CLKDIV_Pos); MODIFY_REG(Device->BTCR[FMC_NORSRAM_BANK1 + 1U], FMC_BTRx_CLKDIV, tmpr); } @@ -410,7 +410,7 @@ HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, - FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, + const FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode) { /* Check the parameters */ @@ -507,7 +507,6 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @} */ - /** @defgroup FMC_LL_Exported_Functions_NAND FMC Low Layer NAND Exported Functions * @brief NAND Controller functions * @@ -557,7 +556,7 @@ HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device * @param Init Pointer to NAND Initialization structure * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init) +HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, const FMC_NAND_InitTypeDef *Init) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -590,7 +589,7 @@ HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef * * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -604,10 +603,10 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - Device->PMEM =(Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | - ((Timing->HoldSetupTime )<< FMC_PMEM_MEMHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); + Device->PMEM = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PMEM_MEMWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PMEM_MEMHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PMEM_MEMHIZ_Pos)); return HAL_OK; } @@ -621,7 +620,7 @@ HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, * @retval HAL status */ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, - FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) + const FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank) { /* Check the parameters */ assert_param(IS_FMC_NAND_DEVICE(Device)); @@ -635,10 +634,10 @@ HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, UNUSED(Bank); /* NAND bank 3 registers configuration */ - Device->PATT =(Timing->SetupTime | - ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | - ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | - ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); + Device->PATT = (Timing->SetupTime | + ((Timing->WaitSetupTime) << FMC_PATT_ATTWAIT_Pos) | + ((Timing->HoldSetupTime) << FMC_PATT_ATTHOLD_Pos) | + ((Timing->HiZSetupTime) << FMC_PATT_ATTHIZ_Pos)); return HAL_OK; } @@ -742,7 +741,7 @@ HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank) * @param Timeout Timeout wait value * @retval HAL status */ -HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, +HAL_StatusTypeDef FMC_NAND_GetECC(const FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout) { uint32_t tickstart; @@ -780,8 +779,6 @@ HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, ui * @} */ - - /** * @} */ diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_gpio.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_gpio.c index 80e486e84c..25a4f3bf0f 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_gpio.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_gpio.c @@ -100,7 +100,7 @@ * - SUCCESS: GPIO registers are de-initialized * - ERROR: Wrong GPIO Port */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx) { ErrorStatus status = SUCCESS; diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_opamp.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_opamp.c index f1a7e8c954..c053dbbc82 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_opamp.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_opamp.c @@ -129,7 +129,7 @@ ErrorStatus LL_OPAMP_DeInit(OPAMP_TypeDef* OPAMPx) * - SUCCESS: OPAMP registers are initialized * - ERROR: OPAMP registers are not initialized */ -ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, LL_OPAMP_InitTypeDef *OPAMP_InitStruct) +ErrorStatus LL_OPAMP_Init(OPAMP_TypeDef *OPAMPx, const LL_OPAMP_InitTypeDef *OPAMP_InitStruct) { /* Check the parameters */ assert_param(IS_OPAMP_ALL_INSTANCE(OPAMPx)); diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c index b7d27dd076..6a28ff0ccc 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_sdmmc.c @@ -163,7 +163,7 @@ */ #if defined (SDMMC1) || defined (SDMMC2) -#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) +#if defined (HAL_SD_MODULE_ENABLED) || defined (HAL_MMC_MODULE_ENABLED) || defined (HAL_SDIO_MODULE_ENABLED) /* Private typedef -----------------------------------------------------------*/ /* Private define ------------------------------------------------------------*/ @@ -349,7 +349,7 @@ uint32_t SDMMC_GetPowerState(const SDMMC_TypeDef *SDMMCx) * the configuration information for the SDMMC command * @retval HAL status */ -HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command) +HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, const SDMMC_CmdInitTypeDef *Command) { uint32_t tmpreg = 0; @@ -417,7 +417,7 @@ uint32_t SDMMC_GetResponse(const SDMMC_TypeDef *SDMMCx, uint32_t Response) * that contains the configuration information for the SDMMC data. * @retval HAL status */ -HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef *Data) +HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, const SDMMC_DataInitTypeDef *Data) { uint32_t tmpreg = 0; @@ -1256,6 +1256,78 @@ uint32_t SDMMC_CmdSendEXTCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument) return errorstate; } +/** + * @brief Execute a cmd52 to write single byte data and read single byte data if needed + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @param pData: pointer to read response if needed + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteDirect(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint8_t *pResponse) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_DIRECT; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_DIRECT, pResponse); + + return errorstate; +} + +/** + * @brief Execute a cmd53 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_SDIO_CmdReadWriteExtended(SDMMC_TypeDef *SDMMCx, uint32_t Argument) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_RW_EXTENDED; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp5(SDMMCx, SDMMC_CMD_SDMMC_RW_EXTENDED, NULL); + + return errorstate; +} + +/** + * @brief Execute a cmd5 to write or read multiple data with a single command + * @param SDMMCx: Pointer to SDMMC register base + * @param Argument: SDMMC command argument which is sent to a card as part of a command message + * @retval SD Card error state + */ +uint32_t SDMMC_CmdSendOperationcondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument, uint32_t *pResp) +{ + SDMMC_CmdInitTypeDef sdmmc_cmdinit; + uint32_t errorstate; + + sdmmc_cmdinit.Argument = Argument; + sdmmc_cmdinit.CmdIndex = SDMMC_CMD_SDMMC_SEN_OP_COND; + sdmmc_cmdinit.Response = SDMMC_RESPONSE_SHORT; + sdmmc_cmdinit.WaitForInterrupt = SDMMC_WAIT_NO; + sdmmc_cmdinit.CPSM = SDMMC_CPSM_ENABLE; + (void)SDMMC_SendCommand(SDMMCx, &sdmmc_cmdinit); + + /* Check for error conditions */ + errorstate = SDMMC_GetCmdResp4(SDMMCx, pResp); + + return errorstate; +} /** * @} */ @@ -1491,6 +1563,138 @@ uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx) return SDMMC_ERROR_NONE; } +/** + * @brief Checks for error conditions for R4 response. + * @param SDMMCx: Pointer to SDMMC register base + * @param pResp: pointer to response + * @retval error state + */ +uint32_t SDMMC_GetCmdResp4(SDMMC_TypeDef *SDMMCx, uint32_t *pResp) +{ + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else + { + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + *pResp = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + return SDMMC_ERROR_NONE; +} + +/** + * @brief Checks for error conditions for R5 (cmd52/cmd53) response. + * @param SDMMCx: Pointer to SDMMC register base + * @param SDIO_CMD: The sent command index + * @param pData: pointer to the read/write buffer needed for cmd52 + * @retval SDIO Card error state + */ +uint32_t SDMMC_GetCmdResp5(SDMMC_TypeDef *SDMMCx, uint8_t SDIO_CMD, uint8_t *pData) +{ + uint32_t response_r5; + uint32_t sta_reg; + + /* 8 is the number of required instructions cycles for the below loop statement. + The SDMMC_CMDTIMEOUT is expressed in ms */ + uint32_t count = SDMMC_CMDTIMEOUT * (SystemCoreClock / 8U / 1000U); + + do + { + if (count-- == 0U) + { + return SDMMC_ERROR_TIMEOUT; + } + sta_reg = SDMMCx->STA; + } while (((sta_reg & (SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_CMDREND | SDMMC_FLAG_CTIMEOUT)) == 0U) || + ((sta_reg & SDMMC_FLAG_CMDACT) != 0U)); + + if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CTIMEOUT); + + return SDMMC_ERROR_CMD_RSP_TIMEOUT; + } + else if (__SDMMC_GET_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL)) + { + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_FLAG_CCRCFAIL); + + return SDMMC_ERROR_CMD_CRC_FAIL; + } + else + { + /* Nothing to do */ + } + + /* Check response received is of desired command */ + if (SDMMC_GetCommandResponse(SDMMCx) != SDIO_CMD) + { + return SDMMC_ERROR_CMD_CRC_FAIL; + } + + /* Clear all the static flags */ + __SDMMC_CLEAR_FLAG(SDMMCx, SDMMC_STATIC_CMD_FLAGS); + + /* We have received response, retrieve it. */ + response_r5 = SDMMC_GetResponse(SDMMCx, SDMMC_RESP1); + + if ((response_r5 & SDMMC_SDIO_R5_ERRORBITS) == SDMMC_ALLZERO) + { + /* we only want 8 bit read or write data and the 8 bit response flags are masked in the data pointer */ + if (pData != NULL) + { + *pData = (uint8_t)(response_r5 & 0xFFU); + } + + return SDMMC_ERROR_NONE; + } + else if ((response_r5 & SDMMC_SDIO_R5_OUT_OF_RANGE) == SDMMC_SDIO_R5_OUT_OF_RANGE) + { + return SDMMC_ERROR_ADDR_OUT_OF_RANGE; + } + else if ((response_r5 & SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) == SDMMC_SDIO_R5_INVALID_FUNCTION_NUMBER) + { + return SDMMC_ERROR_INVALID_PARAMETER; + } + else if ((response_r5 & SDMMC_SDIO_R5_ILLEGAL_CMD) == SDMMC_SDIO_R5_ILLEGAL_CMD) + { + return SDMMC_ERROR_ILLEGAL_CMD; + } + else if ((response_r5 & SDMMC_SDIO_R5_COM_CRC_FAILED) == SDMMC_SDIO_R5_COM_CRC_FAILED) + { + return SDMMC_ERROR_COM_CRC_FAILED; + } + else + { + return SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } +} + /** * @brief Checks for error conditions for R6 (RCA) response. * @param hsd: SD handle diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_spi.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_spi.c index 64380e9d2e..e4a4776641 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_spi.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_spi.c @@ -129,7 +129,7 @@ * - SUCCESS: SPI registers are de-initialized * - ERROR: SPI registers are not de-initialized */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx) { ErrorStatus status = ERROR; @@ -178,8 +178,9 @@ ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) /** * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note As some bits in SPI configuration registers can only be written when the + * SPI is disabled (SPI_CR1_SPE bit = 0), SPI peripheral should be in disabled state prior + * calling this function. Otherwise, ERROR result will be returned. * @param SPIx SPI Instance * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure * @retval An ErrorStatus enumeration value. (Return always SUCCESS) diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c index 8b0d397f63..4b4ea160bc 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_tim.c @@ -594,8 +594,6 @@ void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorI * @note Channel 2 is configured in output PWM 2 mode. * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. * @note OC2REF is selected as trigger output on TRGO. - * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used - * when TIMx operates in Hall sensor interface mode. * @param TIMx Timer Instance * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor * interface configuration data structure) diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c index a9eef24dc3..ea88aeebc7 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_usb.c @@ -33,6 +33,9 @@ (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes. + (#)NOTE: For applications not using double buffer mode, define the symbol + 'USE_USB_DOUBLE_BUFFER' as 0 to reduce the driver's memory footprint. + @endverbatim ****************************************************************************** @@ -61,7 +64,7 @@ * the configuration information for the specified USBx peripheral. * @retval HAL status */ -HAL_StatusTypeDef USB_CoreInit(USB_TypeDef *USBx, USB_CfgTypeDef cfg) +HAL_StatusTypeDef USB_CoreInit(USB_TypeDef const *USBx, USB_CfgTypeDef cfg) { /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); @@ -130,7 +133,7 @@ HAL_StatusTypeDef USB_DisableGlobalInt(USB_TypeDef *USBx) * @arg USB_DEVICE_MODE Peripheral mode * @retval HAL status */ -HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef *USBx, USB_ModeTypeDef mode) +HAL_StatusTypeDef USB_SetCurrentMode(USB_TypeDef const *USBx, USB_ModeTypeDef mode) { /* Prevent unused argument(s) compilation warning */ UNUSED(USBx); @@ -319,6 +322,10 @@ HAL_StatusTypeDef USB_ActivateEndpoint(USB_TypeDef *USBx, USB_EPTypeDef *ep) PCD_CLEAR_RX_DTOG(USBx, ep->num); PCD_CLEAR_TX_DTOG(USBx, ep->num); + /* Set endpoint RX count */ + PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); + + /* Set endpoint RX to valid state */ PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_DIS); } @@ -423,7 +430,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* IN endpoint */ if (ep->is_in == 1U) { - /*Multi packet transfer*/ + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { len = ep->maxpacket; @@ -525,9 +532,9 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) USB_WritePMA(USBx, ep->xfer_buff, pmabuffer, (uint16_t)len); } } - else /* manage isochronous double buffer IN mode */ + else /* Manage isochronous double buffer IN mode */ { - /* each Time to write in PMA xfer_len_db will */ + /* Each Time to write in PMA xfer_len_db will */ ep->xfer_len_db -= len; /* Fill the data buffer */ @@ -559,19 +566,25 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) { if (ep->doublebuffer == 0U) { + if ((ep->xfer_len == 0U) && (ep->type == EP_TYPE_CTRL)) + { + /* This is a status out stage set the OUT_STATUS */ + PCD_SET_OUT_STATUS(USBx, ep->num); + } + else + { + PCD_CLEAR_OUT_STATUS(USBx, ep->num); + } + /* Multi packet transfer */ if (ep->xfer_len > ep->maxpacket) { - len = ep->maxpacket; - ep->xfer_len -= len; + ep->xfer_len -= ep->maxpacket; } else { - len = ep->xfer_len; ep->xfer_len = 0U; } - /* configure and validate Rx endpoint */ - PCD_SET_EP_RX_CNT(USBx, ep->num, len); } #if (USE_USB_DOUBLE_BUFFER == 1U) else @@ -580,15 +593,13 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* Set the Double buffer counter */ if (ep->type == EP_TYPE_BULK) { - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, ep->maxpacket); - /* Coming from ISR */ if (ep->xfer_count != 0U) { - /* update last value to check if there is blocking state */ + /* Update last value to check if there is blocking state */ wEPVal = PCD_GET_ENDPOINT(USBx, ep->num); - /*Blocking State */ + /* Blocking State */ if ((((wEPVal & USB_EP_DTOG_RX) != 0U) && ((wEPVal & USB_EP_DTOG_TX) != 0U)) || (((wEPVal & USB_EP_DTOG_RX) == 0U) && ((wEPVal & USB_EP_DTOG_TX) == 0U))) { @@ -599,18 +610,8 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_TypeDef *USBx, USB_EPTypeDef *ep) /* iso out double */ else if (ep->type == EP_TYPE_ISOC) { - /* Multi packet transfer */ - if (ep->xfer_len > ep->maxpacket) - { - len = ep->maxpacket; - ep->xfer_len -= len; - } - else - { - len = ep->xfer_len; - ep->xfer_len = 0U; - } - PCD_SET_EP_DBUF_CNT(USBx, ep->num, ep->is_in, len); + /* Only single packet transfer supported in FS */ + ep->xfer_len = 0U; } else { @@ -654,26 +655,23 @@ HAL_StatusTypeDef USB_EPSetStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) */ HAL_StatusTypeDef USB_EPClearStall(USB_TypeDef *USBx, USB_EPTypeDef *ep) { - if (ep->doublebuffer == 0U) + if (ep->is_in != 0U) { - if (ep->is_in != 0U) - { - PCD_CLEAR_TX_DTOG(USBx, ep->num); + PCD_CLEAR_TX_DTOG(USBx, ep->num); - if (ep->type != EP_TYPE_ISOC) - { - /* Configure NAK status for the Endpoint */ - PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); - } - } - else + if (ep->type != EP_TYPE_ISOC) { - PCD_CLEAR_RX_DTOG(USBx, ep->num); - - /* Configure VALID status for the Endpoint */ - PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + /* Configure NAK status for the Endpoint */ + PCD_SET_EP_TX_STATUS(USBx, ep->num, USB_EP_TX_NAK); } } + else + { + PCD_CLEAR_RX_DTOG(USBx, ep->num); + + /* Configure VALID status for the Endpoint */ + PCD_SET_EP_RX_STATUS(USBx, ep->num, USB_EP_RX_VALID); + } return HAL_OK; } diff --git a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_utils.c b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_utils.c index 3f31396df0..4c4521ec78 100644 --- a/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_utils.c +++ b/system/Drivers/STM32L5xx_HAL_Driver/Src/stm32l5xx_ll_utils.c @@ -121,7 +121,7 @@ * @{ */ static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, - LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); + const LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct); static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); static ErrorStatus UTILS_PLL_IsBusy(void); /** @@ -668,7 +668,7 @@ ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypa * the configuration information for the PLL. * @retval PLL output frequency (in Hz) */ -static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) +static uint32_t UTILS_GetPLLOutputFrequency(uint32_t PLL_InputFrequency, const LL_UTILS_PLLInitTypeDef *UTILS_PLLInitStruct) { uint32_t pllfreq; diff --git a/system/Drivers/STM32YYxx_HAL_Driver_version.md b/system/Drivers/STM32YYxx_HAL_Driver_version.md index 7324c2b198..c0f557a670 100644 --- a/system/Drivers/STM32YYxx_HAL_Driver_version.md +++ b/system/Drivers/STM32YYxx_HAL_Driver_version.md @@ -14,7 +14,7 @@ * STM32L0: 1.10.7 * STM32L1: 1.4.6 * STM32L4: 1.13.5 - * STM32L5: 1.0.6 + * STM32L5: 1.0.7 * STM32MP1: 1.7.0 * STM32U0: 1.3.0 * STM32U3: 1.1.0 From 3da9a1be701e3dbc829755177ec9f2a397c6159f Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 20 Nov 2025 11:08:44 +0100 Subject: [PATCH 2/4] system(l5): update STM32L5xx CMSIS Drivers to v1.0.7 Included in STM32CubeL5 FW v1.6.0 Signed-off-by: Frederic Pillon --- .../Device/ST/STM32L5xx/Include/stm32l552xx.h | 4 +- .../Device/ST/STM32L5xx/Include/stm32l562xx.h | 4 +- .../Device/ST/STM32L5xx/Include/stm32l5xx.h | 2 +- .../ST/STM32L5xx/{License.md => LICENSE.md} | 0 .../CMSIS/Device/ST/STM32L5xx/README.md | 30 ++++---- .../Device/ST/STM32L5xx/Release_Notes.html | 70 +++++++++++++------ .../Source/Templates/system_stm32l5xx.c | 8 +-- .../Source/Templates/system_stm32l5xx_ns.c | 6 ++ .../Source/Templates/system_stm32l5xx_s.c | 8 +-- .../Device/ST/STM32YYxx_CMSIS_version.md | 2 +- 10 files changed, 83 insertions(+), 51 deletions(-) rename system/Drivers/CMSIS/Device/ST/STM32L5xx/{License.md => LICENSE.md} (100%) diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h index 0f7b82a572..23326fe545 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Include/stm32l552xx.h @@ -214,7 +214,7 @@ typedef enum #define __FPU_PRESENT 1U /* FPU present */ #define __DSP_PRESENT 1U /* DSP extension present */ -#include /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32l5xx.h" /*!< STM32L5xx System */ @@ -14729,7 +14729,7 @@ typedef struct /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*! /*!< ARM Cortex-M33 processor and core peripherals */ +#include "core_cm33.h" /*!< ARM Cortex-M33 processor and core peripherals */ #include "system_stm32l5xx.h" /*!< STM32L5xx System */ @@ -15468,7 +15468,7 @@ typedef struct /******************* Bit definition for TIM_CCR5 register *******************/ #define TIM_CCR5_CCR5_Pos (0U) -#define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */ +#define TIM_CCR5_CCR5_Msk (0xFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFF */ #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!Purpose

Update History

- +

Main Changes

Maintenance release

Contents

    -
  • Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
    • -
  • Add the READONLY tag to sections containing lookup tables to avoid GCC12 linker warnings if a segment is marked RWX.
    • +
  • Fix Capture Compare register TIMx_CCR5 definition.
    • +
  • Allow redefinition of the macro ‘VECT_TAB_OFFSET’ externally from the IDE, makefile, or command line.
    • +
  • Update core_cm33 header file inclusion to use double quotes instead of angle brackets.

Notes

Reminder:

@@ -72,12 +73,41 @@

Notes

- +

Main Changes

Maintenance release

Contents

    +
  • Fix the location of .size directive in STM32CubeIDE’s startup code to allow proper size information of vector table.
    • +
  • Add the READONLY tag to sections containing lookup tables to avoid GCC12 linker warnings if a segment is marked RWX.
    • +
+

Notes

+

Reminder:

+
    +
  • When TrustZone is enabled in the system (Flash option bit TZEN=1) +
      +
    • template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core).
      • +
    • default Security Attribute Unit (SAU) configuration in the partition_stm32l552xx.h and partition_stm32l562xx.h: +
        +
      • SAU region 0: 0x0C03E000-0x0C03FFFF (Secure, Non-Secure Callable)
        • +
      • SAU region 1: 0x08040000-0x0807FFFF (Non-Secure FLASH Bank2 (256 Kbytes))
        • +
      • SAU region 2: 0x20018000-0x2003FFFF (Non-Secure RAM (2nd half SRAM1 + SRAM2 (160 Kbytes)))
        • +
      • SAU region 3: 0x40000000-0x4FFFFFFF (Non-Secure Peripheral mapped memory)
        • +
      • SAU region 4: 0x60000000-0x9FFFFFFF (Non-Secure external memories)
        • +
      • SAU region 5: 0x0BF90000-0x0BFA8FFF (Non-Secure System memory)
        • +
      • +
    • +
+
+
+
+ +
+

Main Changes

+

Maintenance release

+

Contents

+
  • General updates to fix known defects and implementation enhancements.
  • All source files: update disclaimer to add reference to the new license agreement.
  • Add new atomic register access macros in stm32l5xx.h file.
    • @@ -85,7 +115,7 @@

    Contents

  • Add missing parameter after @param in order to fix warning in generated documentation
  • Change addresses of ROM symbols in sram.icf template files to code region alias in order to increase performance while running code from SRAM
-

Notes

+

Notes

Reminder:

  • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -107,9 +137,9 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    Maintenance release

    -

    Contents

    +

    Contents

    Maintenance release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

    • stm32l552xx.h and stm32l562xx.h updates @@ -118,7 +148,7 @@

      Contents

    • Fix I2C4_EV_IRQn and I2C4_ER_IRQn order in IRQn_Type
-

Notes

+

Notes

Reminder:

  • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -140,9 +170,9 @@

    Notes

    -

    Main Changes

    +

    Main Changes

    Fourth release

    -

    Contents

    +

    Contents

    Fourth release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

    • stm32l552xx.h and stm32l562xx.h updates @@ -158,7 +188,7 @@

      Contents

    • Add README.md and License.md files for GitHub publication
    • Misspelled words corrections in driver descriptions
    -

    Notes

    +

    Notes

    Reminder:

    • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -180,9 +210,9 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      Third release

      -

      Contents

      +

      Contents

      Third official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

      • stm32l552xx.h and stm32l562xx.h updates @@ -192,7 +222,7 @@

        Contents

      • Align DBGMCU_APB2FZR register and bits definitions with RM0438
    -

    Notes

    +

    Notes

    Reminder:

    • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -214,9 +244,9 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      Second release

      -

      Contents

      +

      Contents

      Second official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

      • Templates system_stm32l5xx.c, system_stm32l5xx_s.c and system_stm32l5xx_ns.c @@ -224,7 +254,7 @@

        Contents

      • Add vector table relocation capability with conditional USER_VECT_TAB_ADDRESS
    -

    Notes

    +

    Notes

    Reminder:

    • When TrustZone is enabled in the system (Flash option bit TZEN=1) @@ -246,9 +276,9 @@

      Notes

      -

      Main Changes

      +

      Main Changes

      First release

      -

      Contents

      +

      Contents

      First official release of STM32L5xx CMSIS Device drivers to support STM32L552xx and STM32L562xx devices

      • Templates @@ -266,7 +296,7 @@

        Contents

      • Linker files for 256 and 512 Kbytes Flash device configurations
    -

    Notes

    +

    Notes

    When TrustZone is enabled in the system (Flash option bit TZEN=1), template device partition_stm32l552xx.h or partition_stm32l562xx.h file must be copied and optionally updated in user application secure project to configure the system (SAU, interrupts, core)

    diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c index 93e1ad7d1e..71f333cee3 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx.c @@ -143,14 +143,14 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c index 53e22fff50..4b11eb8359 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_ns.c @@ -97,13 +97,19 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE_NS /*!< Vector Table base address field. This value must be a multiple of 0x200. */ +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x00018000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE_NS /*!< Vector Table base address field. This value must be a multiple of 0x200. */ +#if !defined(VECT_TAB_OFFSET) #define VECT_TAB_OFFSET 0x00040000U /*!< Vector Table base offset field. This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ + #endif /* VECT_TAB_SRAM */ #endif /* USER_VECT_TAB_ADDRESS */ diff --git a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c index afe8e1ec68..b573073a11 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c +++ b/system/Drivers/CMSIS/Device/ST/STM32L5xx/Source/Templates/system_stm32l5xx_s.c @@ -159,14 +159,14 @@ #if defined(VECT_TAB_SRAM) #define VECT_TAB_BASE_ADDRESS SRAM1_BASE_S /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #else #define VECT_TAB_BASE_ADDRESS FLASH_BASE_S /*!< Vector Table base address field. This value must be a multiple of 0x200. */ -#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table base offset field. - This value must be a multiple of 0x200. */ #endif /* VECT_TAB_SRAM */ +#if !defined(VECT_TAB_OFFSET) +#define VECT_TAB_OFFSET 0x00000000U /*!< Vector Table offset field. + This value must be a multiple of 0x200. */ +#endif /* VECT_TAB_OFFSET */ #endif /* USER_VECT_TAB_ADDRESS */ /******************************************************************************/ diff --git a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md index c7b748d11d..047d73187c 100644 --- a/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md +++ b/system/Drivers/CMSIS/Device/ST/STM32YYxx_CMSIS_version.md @@ -14,7 +14,7 @@ * STM32L0: 1.9.4 * STM32L1: 2.3.4 * STM32L4: 1.7.4 - * STM32L5: 1.0.6 + * STM32L5: 1.0.7 * STM32MP1: 1.7.0 * STM32U0: 1.3.0 * STM32U3: 1.1.0 From 1b3ad2214236760457b8e180be9b342f7f616c91 Mon Sep 17 00:00:00 2001 From: Frederic Pillon Date: Thu, 20 Nov 2025 11:08:53 +0100 Subject: [PATCH 3/4] system(wl) update STM32WLxx HAL Drivers to v1.4.0 Included in STM32CubeWL FW v1.4.0 Signed-off-by: Frederic Pillon --- .../Inc/Legacy/stm32_hal_legacy.h | 546 +++++++++-- .../Inc/stm32_assert_template.h | 8 +- .../STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h | 22 +- .../Inc/stm32wlxx_hal_adc.h | 327 ++++--- .../Inc/stm32wlxx_hal_adc_ex.h | 5 +- .../Inc/stm32wlxx_hal_comp.h | 64 +- .../Inc/stm32wlxx_hal_conf_template.h | 70 +- .../Inc/stm32wlxx_hal_cortex.h | 14 +- .../Inc/stm32wlxx_hal_crc.h | 2 +- .../Inc/stm32wlxx_hal_cryp.h | 29 +- .../Inc/stm32wlxx_hal_cryp_ex.h | 8 +- .../Inc/stm32wlxx_hal_dac.h | 14 - .../Inc/stm32wlxx_hal_def.h | 118 +-- .../Inc/stm32wlxx_hal_dma.h | 16 +- .../Inc/stm32wlxx_hal_dma_ex.h | 4 +- .../Inc/stm32wlxx_hal_exti.h | 10 +- .../Inc/stm32wlxx_hal_flash.h | 78 +- .../Inc/stm32wlxx_hal_flash_ex.h | 8 +- .../Inc/stm32wlxx_hal_gpio.h | 4 +- .../Inc/stm32wlxx_hal_gtzc.h | 28 +- .../Inc/stm32wlxx_hal_hsem.h | 12 +- .../Inc/stm32wlxx_hal_i2c.h | 2 - .../Inc/stm32wlxx_hal_i2s.h | 4 +- .../Inc/stm32wlxx_hal_irda.h | 56 +- .../Inc/stm32wlxx_hal_lptim.h | 10 +- .../Inc/stm32wlxx_hal_pka.h | 4 +- .../Inc/stm32wlxx_hal_pwr.h | 52 +- .../Inc/stm32wlxx_hal_pwr_ex.h | 30 +- .../Inc/stm32wlxx_hal_rcc.h | 58 +- .../Inc/stm32wlxx_hal_rng.h | 7 +- .../Inc/stm32wlxx_hal_rng_ex.h | 36 +- .../Inc/stm32wlxx_hal_rtc.h | 130 +-- .../Inc/stm32wlxx_hal_rtc_ex.h | 135 +-- .../Inc/stm32wlxx_hal_smartcard.h | 140 ++- .../Inc/stm32wlxx_hal_smbus.h | 2 - .../Inc/stm32wlxx_hal_spi.h | 46 +- .../Inc/stm32wlxx_hal_spi_ex.h | 2 +- .../Inc/stm32wlxx_hal_subghz.h | 5 +- .../Inc/stm32wlxx_hal_tim.h | 97 +- .../Inc/stm32wlxx_hal_tim_ex.h | 2 +- .../Inc/stm32wlxx_hal_uart.h | 137 +-- .../Inc/stm32wlxx_hal_uart_ex.h | 29 +- .../Inc/stm32wlxx_hal_usart.h | 95 +- .../Inc/stm32wlxx_hal_usart_ex.h | 10 +- .../Inc/stm32wlxx_ll_adc.h | 869 ++++++++++++------ .../Inc/stm32wlxx_ll_comp.h | 36 +- .../Inc/stm32wlxx_ll_cortex.h | 7 +- .../Inc/stm32wlxx_ll_crc.h | 22 +- .../Inc/stm32wlxx_ll_dac.h | 26 +- .../Inc/stm32wlxx_ll_dma.h | 228 ++--- .../Inc/stm32wlxx_ll_dmamux.h | 164 ++-- .../Inc/stm32wlxx_ll_gpio.h | 26 +- .../Inc/stm32wlxx_ll_hsem.h | 236 +---- .../Inc/stm32wlxx_ll_i2c.h | 4 +- .../Inc/stm32wlxx_ll_iwdg.h | 14 +- .../Inc/stm32wlxx_ll_lptim.h | 2 +- .../Inc/stm32wlxx_ll_lpuart.h | 43 +- .../Inc/stm32wlxx_ll_pka.h | 33 +- .../Inc/stm32wlxx_ll_pwr.h | 14 +- .../Inc/stm32wlxx_ll_rng.h | 75 +- .../Inc/stm32wlxx_ll_rtc.h | 334 +++---- .../Inc/stm32wlxx_ll_spi.h | 167 ++-- .../Inc/stm32wlxx_ll_system.h | 11 +- .../Inc/stm32wlxx_ll_tim.h | 101 +- .../Inc/stm32wlxx_ll_usart.h | 375 ++++---- .../Inc/stm32wlxx_ll_utils.h | 4 +- .../Inc/stm32wlxx_ll_wwdg.h | 12 +- .../STM32WLxx_HAL_Driver/Release_Notes.html | 737 +++++++-------- .../STM32WLxx_HAL_Driver/Src/stm32wlxx_hal.c | 8 +- .../Src/stm32wlxx_hal_adc.c | 107 +-- .../Src/stm32wlxx_hal_adc_ex.c | 32 +- .../Src/stm32wlxx_hal_comp.c | 78 +- .../Src/stm32wlxx_hal_cortex.c | 6 + .../Src/stm32wlxx_hal_crc.c | 4 +- .../Src/stm32wlxx_hal_cryp.c | 735 ++++++++------- .../Src/stm32wlxx_hal_cryp_ex.c | 12 +- .../Src/stm32wlxx_hal_dac.c | 81 +- .../Src/stm32wlxx_hal_dac_ex.c | 29 +- .../Src/stm32wlxx_hal_dma.c | 98 +- .../Src/stm32wlxx_hal_dma_ex.c | 30 +- .../Src/stm32wlxx_hal_exti.c | 14 +- .../Src/stm32wlxx_hal_flash.c | 23 +- .../Src/stm32wlxx_hal_flash_ex.c | 57 +- .../Src/stm32wlxx_hal_gpio.c | 12 +- .../Src/stm32wlxx_hal_gtzc.c | 30 +- .../Src/stm32wlxx_hal_i2c.c | 154 ++-- .../Src/stm32wlxx_hal_i2s.c | 82 +- .../Src/stm32wlxx_hal_ipcc.c | 12 +- .../Src/stm32wlxx_hal_irda.c | 41 +- .../Src/stm32wlxx_hal_lptim.c | 10 +- .../Src/stm32wlxx_hal_pka.c | 56 +- .../Src/stm32wlxx_hal_pwr.c | 21 +- .../Src/stm32wlxx_hal_pwr_ex.c | 45 +- .../Src/stm32wlxx_hal_rcc.c | 6 +- .../Src/stm32wlxx_hal_rng.c | 56 +- .../Src/stm32wlxx_hal_rng_ex.c | 27 +- .../Src/stm32wlxx_hal_rtc.c | 235 +++-- .../Src/stm32wlxx_hal_rtc_ex.c | 41 +- .../Src/stm32wlxx_hal_smartcard.c | 12 +- .../Src/stm32wlxx_hal_smartcard_ex.c | 6 +- .../Src/stm32wlxx_hal_smbus.c | 42 +- .../Src/stm32wlxx_hal_smbus_ex.c | 2 + .../Src/stm32wlxx_hal_spi.c | 460 +++++---- .../Src/stm32wlxx_hal_spi_ex.c | 2 +- .../Src/stm32wlxx_hal_subghz.c | 15 +- .../Src/stm32wlxx_hal_tim.c | 151 ++- .../Src/stm32wlxx_hal_tim_ex.c | 78 +- ...tm32wlxx_hal_timebase_rtc_alarm_template.c | 13 +- ...m32wlxx_hal_timebase_rtc_wakeup_template.c | 19 +- .../Src/stm32wlxx_hal_timebase_tim_template.c | 13 +- .../Src/stm32wlxx_hal_uart.c | 302 +++--- .../Src/stm32wlxx_hal_uart_ex.c | 180 ++-- .../Src/stm32wlxx_hal_usart.c | 71 +- .../Src/stm32wlxx_hal_usart_ex.c | 15 +- .../Src/stm32wlxx_ll_adc.c | 31 +- .../Src/stm32wlxx_ll_comp.c | 25 +- .../Src/stm32wlxx_ll_crc.c | 2 +- .../Src/stm32wlxx_ll_dac.c | 74 +- .../Src/stm32wlxx_ll_dma.c | 28 +- .../Src/stm32wlxx_ll_gpio.c | 2 +- .../Src/stm32wlxx_ll_i2c.c | 4 +- .../Src/stm32wlxx_ll_lptim.c | 4 +- .../Src/stm32wlxx_ll_lpuart.c | 5 +- .../Src/stm32wlxx_ll_pka.c | 2 +- .../Src/stm32wlxx_ll_pwr.c | 10 +- .../Src/stm32wlxx_ll_rng.c | 26 +- .../Src/stm32wlxx_ll_rtc.c | 68 +- .../Src/stm32wlxx_ll_spi.c | 9 +- .../Src/stm32wlxx_ll_tim.c | 33 +- .../Src/stm32wlxx_ll_usart.c | 40 +- .../Src/stm32wlxx_ll_utils.c | 4 +- .../Drivers/STM32YYxx_HAL_Driver_version.md | 2 +- 132 files changed, 5446 insertions(+), 4462 deletions(-) diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h index c3fa678347..aac1d4c645 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/Legacy/stm32_hal_legacy.h @@ -37,16 +37,12 @@ extern "C" { #define AES_CLEARFLAG_CCF CRYP_CLEARFLAG_CCF #define AES_CLEARFLAG_RDERR CRYP_CLEARFLAG_RDERR #define AES_CLEARFLAG_WRERR CRYP_CLEARFLAG_WRERR -#if defined(STM32U5) || defined(STM32H7) || defined(STM32MP1) +#if defined(STM32H7) || defined(STM32MP1) #define CRYP_DATATYPE_32B CRYP_NO_SWAP #define CRYP_DATATYPE_16B CRYP_HALFWORD_SWAP #define CRYP_DATATYPE_8B CRYP_BYTE_SWAP #define CRYP_DATATYPE_1B CRYP_BIT_SWAP -#if defined(STM32U5) -#define CRYP_CCF_CLEAR CRYP_CLEAR_CCF -#define CRYP_ERR_CLEAR CRYP_CLEAR_RWEIF -#endif /* STM32U5 */ -#endif /* STM32U5 || STM32H7 || STM32MP1 */ +#endif /* STM32H7 || STM32MP1 */ /** * @} */ @@ -113,6 +109,9 @@ extern "C" { #define ADC4_SAMPLETIME_160CYCLES_5 ADC4_SAMPLETIME_814CYCLES_5 #endif /* STM32U5 */ +#if defined(STM32H5) +#define ADC_CHANNEL_VCORE ADC_CHANNEL_VDDCORE +#endif /* STM32H5 */ /** * @} */ @@ -140,7 +139,8 @@ extern "C" { #define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6 #define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7 #if defined(STM32L0) -#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */ +#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM + input 1 for COMP1, LPTIM input 2 for COMP2 */ #endif #define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR #if defined(STM32F373xC) || defined(STM32F378xx) @@ -239,10 +239,12 @@ extern "C" { /** @defgroup CRC_Aliases CRC API aliases * @{ */ -#if defined(STM32C0) +#if defined(STM32H5) || defined(STM32C0) #else -#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for inter STM32 series compatibility */ -#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for inter STM32 series compatibility */ +#define HAL_CRC_Input_Data_Reverse HAL_CRCEx_Input_Data_Reverse /*!< Aliased to HAL_CRCEx_Input_Data_Reverse for + inter STM32 series compatibility */ +#define HAL_CRC_Output_Data_Reverse HAL_CRCEx_Output_Data_Reverse /*!< Aliased to HAL_CRCEx_Output_Data_Reverse for + inter STM32 series compatibility */ #endif /** * @} @@ -273,7 +275,7 @@ extern "C" { #define DAC_WAVEGENERATION_NOISE DAC_WAVE_NOISE #define DAC_WAVEGENERATION_TRIANGLE DAC_WAVE_TRIANGLE -#if defined(STM32G4) || defined(STM32L5) || defined(STM32H7) || defined (STM32U5) +#if defined(STM32G4) || defined(STM32H7) || defined (STM32U5) #define DAC_CHIPCONNECT_DISABLE DAC_CHIPCONNECT_EXTERNAL #define DAC_CHIPCONNECT_ENABLE DAC_CHIPCONNECT_INTERNAL #endif @@ -285,7 +287,13 @@ extern "C" { #define DAC_TRIGGER_LPTIM3_OUT DAC_TRIGGER_LPTIM3_CH1 #endif -#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || defined(STM32F4) || defined(STM32G4) +#if defined(STM32H5) +#define DAC_TRIGGER_LPTIM1_OUT DAC_TRIGGER_LPTIM1_CH1 +#define DAC_TRIGGER_LPTIM2_OUT DAC_TRIGGER_LPTIM2_CH1 +#endif + +#if defined(STM32L1) || defined(STM32L4) || defined(STM32G0) || defined(STM32L5) || defined(STM32H7) || \ + defined(STM32F4) || defined(STM32G4) #define HAL_DAC_MSP_INIT_CB_ID HAL_DAC_MSPINIT_CB_ID #define HAL_DAC_MSP_DEINIT_CB_ID HAL_DAC_MSPDEINIT_CB_ID #endif @@ -350,9 +358,13 @@ extern "C" { #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING -#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || defined(STM32L4S7xx) || defined(STM32L4S9xx) +#if defined(STM32L4R5xx) || defined(STM32L4R9xx) || defined(STM32L4R9xx) || defined(STM32L4S5xx) || \ + defined(STM32L4S7xx) || defined(STM32L4S9xx) #define DMA_REQUEST_DCMI_PSSI DMA_REQUEST_DCMI -#endif +#elif defined(STM32L4P5xx) || defined(STM32L4Q5xx) +#define DMA_REQUEST_PSSI DMA_REQUEST_DCMI_PSSI +#define LL_DMAMUX_REQ_PSSI LL_DMAMUX_REQ_DCMI_PSSI +#endif /* STM32L4R5xx || STM32L4R9xx || STM32L4R9xx || STM32L4S5xx || STM32L4S7xx || STM32L4S9xx */ #endif /* STM32L4 */ @@ -463,7 +475,9 @@ extern "C" { #define TYPEPROGRAMDATA_FASTBYTE FLASH_TYPEPROGRAMDATA_FASTBYTE #define TYPEPROGRAMDATA_FASTHALFWORD FLASH_TYPEPROGRAMDATA_FASTHALFWORD #define TYPEPROGRAMDATA_FASTWORD FLASH_TYPEPROGRAMDATA_FASTWORD +#if !defined(STM32F2) && !defined(STM32F4) && !defined(STM32F7) && !defined(STM32H7) && !defined(STM32H5) #define PAGESIZE FLASH_PAGE_SIZE +#endif /* STM32F2 && STM32F4 && STM32F7 && STM32H7 && STM32H5 */ #define TYPEPROGRAM_FASTBYTE FLASH_TYPEPROGRAM_BYTE #define TYPEPROGRAM_FASTHALFWORD FLASH_TYPEPROGRAM_HALFWORD #define TYPEPROGRAM_FASTWORD FLASH_TYPEPROGRAM_WORD @@ -527,6 +541,10 @@ extern "C" { #define FLASH_FLAG_WDW FLASH_FLAG_WBNE #define OB_WRP_SECTOR_All OB_WRP_SECTOR_ALL #endif /* STM32H7 */ +#if defined(STM32H7RS) +#define FLASH_OPTKEY1 FLASH_OPT_KEY1 +#define FLASH_OPTKEY2 FLASH_OPT_KEY2 +#endif /* STM32H7RS */ #if defined(STM32U5) #define OB_USER_nRST_STOP OB_USER_NRST_STOP #define OB_USER_nRST_STDBY OB_USER_NRST_STDBY @@ -539,6 +557,19 @@ extern "C" { #define OB_SRAM134_RST_ERASE OB_SRAM_RST_ERASE #define OB_SRAM134_RST_NOT_ERASE OB_SRAM_RST_NOT_ERASE #endif /* STM32U5 */ +#if defined(STM32U0) +#define OB_USER_nRST_STOP OB_USER_NRST_STOP +#define OB_USER_nRST_STDBY OB_USER_NRST_STDBY +#define OB_USER_nRST_SHDW OB_USER_NRST_SHDW +#define OB_USER_nBOOT_SEL OB_USER_NBOOT_SEL +#define OB_USER_nBOOT0 OB_USER_NBOOT0 +#define OB_USER_nBOOT1 OB_USER_NBOOT1 +#define OB_nBOOT0_RESET OB_NBOOT0_RESET +#define OB_nBOOT0_SET OB_NBOOT0_SET +#endif /* STM32U0 */ +#if defined(STM32H5) +#define FLASH_ECC_AREA_EDATA FLASH_ECC_AREA_EDATA_BANK1 +#endif /* STM32H5 */ /** * @} @@ -582,6 +613,115 @@ extern "C" { #define HAL_SYSCFG_DisableIOAnalogSwitchVDD HAL_SYSCFG_DisableIOSwitchVDD #endif /* STM32G4 */ +#if defined(STM32U5) + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SYSCFG_EnableIOAnalogBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SYSCFG_DisableIOAnalogBooster +#define HAL_SYSCFG_EnableIOAnalogSwitchVoltageSelection HAL_SYSCFG_EnableIOAnalogVoltageSelection +#define HAL_SYSCFG_DisableIOAnalogSwitchVoltageSelection HAL_SYSCFG_DisableIOAnalogVoltageSelection + +#endif /* STM32U5 */ + +#if defined(STM32H5) +#define SYSCFG_IT_FPU_IOC SBS_IT_FPU_IOC +#define SYSCFG_IT_FPU_DZC SBS_IT_FPU_DZC +#define SYSCFG_IT_FPU_UFC SBS_IT_FPU_UFC +#define SYSCFG_IT_FPU_OFC SBS_IT_FPU_OFC +#define SYSCFG_IT_FPU_IDC SBS_IT_FPU_IDC +#define SYSCFG_IT_FPU_IXC SBS_IT_FPU_IXC + +#define SYSCFG_BREAK_FLASH_ECC SBS_BREAK_FLASH_ECC +#define SYSCFG_BREAK_PVD SBS_BREAK_PVD +#define SYSCFG_BREAK_SRAM_ECC SBS_BREAK_SRAM_ECC +#define SYSCFG_BREAK_LOCKUP SBS_BREAK_LOCKUP + +#define SYSCFG_VREFBUF_VOLTAGE_SCALE0 VREFBUF_VOLTAGE_SCALE0 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE1 VREFBUF_VOLTAGE_SCALE1 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE2 VREFBUF_VOLTAGE_SCALE2 +#define SYSCFG_VREFBUF_VOLTAGE_SCALE3 VREFBUF_VOLTAGE_SCALE3 + +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_DISABLE VREFBUF_HIGH_IMPEDANCE_DISABLE +#define SYSCFG_VREFBUF_HIGH_IMPEDANCE_ENABLE VREFBUF_HIGH_IMPEDANCE_ENABLE + +#define SYSCFG_FASTMODEPLUS_PB6 SBS_FASTMODEPLUS_PB6 +#define SYSCFG_FASTMODEPLUS_PB7 SBS_FASTMODEPLUS_PB7 +#define SYSCFG_FASTMODEPLUS_PB8 SBS_FASTMODEPLUS_PB8 +#define SYSCFG_FASTMODEPLUS_PB9 SBS_FASTMODEPLUS_PB9 + +#define SYSCFG_ETH_MII SBS_ETH_MII +#define SYSCFG_ETH_RMII SBS_ETH_RMII +#define IS_SYSCFG_ETHERNET_CONFIG IS_SBS_ETHERNET_CONFIG + +#define SYSCFG_MEMORIES_ERASE_FLAG_IPMEE SBS_MEMORIES_ERASE_FLAG_IPMEE +#define SYSCFG_MEMORIES_ERASE_FLAG_MCLR SBS_MEMORIES_ERASE_FLAG_MCLR +#define IS_SYSCFG_MEMORIES_ERASE_FLAG IS_SBS_MEMORIES_ERASE_FLAG + +#define IS_SYSCFG_CODE_CONFIG IS_SBS_CODE_CONFIG + +#define SYSCFG_MPU_NSEC SBS_MPU_NSEC +#define SYSCFG_VTOR_NSEC SBS_VTOR_NSEC +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define SYSCFG_SAU SBS_SAU +#define SYSCFG_MPU_SEC SBS_MPU_SEC +#define SYSCFG_VTOR_AIRCR_SEC SBS_VTOR_AIRCR_SEC +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#else +#define SYSCFG_LOCK_ALL SBS_LOCK_ALL +#endif /* __ARM_FEATURE_CMSE */ + +#define SYSCFG_CLK SBS_CLK +#define SYSCFG_CLASSB SBS_CLASSB +#define SYSCFG_FPU SBS_FPU +#define SYSCFG_ALL SBS_ALL + +#define SYSCFG_SEC SBS_SEC +#define SYSCFG_NSEC SBS_NSEC + +#define __HAL_SYSCFG_FPU_INTERRUPT_ENABLE __HAL_SBS_FPU_INTERRUPT_ENABLE +#define __HAL_SYSCFG_FPU_INTERRUPT_DISABLE __HAL_SBS_FPU_INTERRUPT_DISABLE + +#define __HAL_SYSCFG_BREAK_ECC_LOCK __HAL_SBS_BREAK_ECC_LOCK +#define __HAL_SYSCFG_BREAK_LOCKUP_LOCK __HAL_SBS_BREAK_LOCKUP_LOCK +#define __HAL_SYSCFG_BREAK_PVD_LOCK __HAL_SBS_BREAK_PVD_LOCK +#define __HAL_SYSCFG_BREAK_SRAM_ECC_LOCK __HAL_SBS_BREAK_SRAM_ECC_LOCK + +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE __HAL_SBS_FASTMODEPLUS_ENABLE +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE __HAL_SBS_FASTMODEPLUS_DISABLE + +#define __HAL_SYSCFG_GET_MEMORIES_ERASE_STATUS __HAL_SBS_GET_MEMORIES_ERASE_STATUS +#define __HAL_SYSCFG_CLEAR_MEMORIES_ERASE_STATUS __HAL_SBS_CLEAR_MEMORIES_ERASE_STATUS + +#define IS_SYSCFG_FPU_INTERRUPT IS_SBS_FPU_INTERRUPT +#define IS_SYSCFG_BREAK_CONFIG IS_SBS_BREAK_CONFIG +#define IS_SYSCFG_VREFBUF_VOLTAGE_SCALE IS_VREFBUF_VOLTAGE_SCALE +#define IS_SYSCFG_VREFBUF_HIGH_IMPEDANCE IS_VREFBUF_HIGH_IMPEDANCE +#define IS_SYSCFG_VREFBUF_TRIMMING IS_VREFBUF_TRIMMING +#define IS_SYSCFG_FASTMODEPLUS IS_SBS_FASTMODEPLUS +#define IS_SYSCFG_ITEMS_ATTRIBUTES IS_SBS_ITEMS_ATTRIBUTES +#define IS_SYSCFG_ATTRIBUTES IS_SBS_ATTRIBUTES +#define IS_SYSCFG_LOCK_ITEMS IS_SBS_LOCK_ITEMS + +#define HAL_SYSCFG_VREFBUF_VoltageScalingConfig HAL_VREFBUF_VoltageScalingConfig +#define HAL_SYSCFG_VREFBUF_HighImpedanceConfig HAL_VREFBUF_HighImpedanceConfig +#define HAL_SYSCFG_VREFBUF_TrimmingConfig HAL_VREFBUF_TrimmingConfig +#define HAL_SYSCFG_EnableVREFBUF HAL_EnableVREFBUF +#define HAL_SYSCFG_DisableVREFBUF HAL_DisableVREFBUF + +#define HAL_SYSCFG_EnableIOAnalogSwitchBooster HAL_SBS_EnableIOAnalogSwitchBooster +#define HAL_SYSCFG_DisableIOAnalogSwitchBooster HAL_SBS_DisableIOAnalogSwitchBooster +#define HAL_SYSCFG_ETHInterfaceSelect HAL_SBS_ETHInterfaceSelect + +#define HAL_SYSCFG_Lock HAL_SBS_Lock +#define HAL_SYSCFG_GetLock HAL_SBS_GetLock + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +#define HAL_SYSCFG_ConfigAttributes HAL_SBS_ConfigAttributes +#define HAL_SYSCFG_GetConfigAttributes HAL_SBS_GetConfigAttributes +#endif /* __ARM_FEATURE_CMSE */ + +#endif /* STM32H5 */ + + /** * @} */ @@ -649,14 +789,16 @@ extern "C" { #define GPIO_AF10_OTG2_HS GPIO_AF10_OTG2_FS #define GPIO_AF10_OTG1_FS GPIO_AF10_OTG1_HS #define GPIO_AF12_OTG2_FS GPIO_AF12_OTG1_FS -#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || STM32H757xx */ +#endif /*STM32H743xx || STM32H753xx || STM32H750xx || STM32H742xx || STM32H745xx || STM32H755xx || STM32H747xx || \ + STM32H757xx */ #endif /* STM32H7 */ #define GPIO_AF0_LPTIM GPIO_AF0_LPTIM1 #define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1 #define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1 -#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) +#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || \ + defined(STM32G4) || defined(STM32H7) || defined(STM32WB) || defined(STM32U5) #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM #define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH @@ -678,11 +820,28 @@ extern "C" { #define GPIO_AF6_DFSDM GPIO_AF6_DFSDM1 -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32H5) #define GPIO_AF0_RTC_50Hz GPIO_AF0_RTC_50HZ +#endif /* STM32U5 || STM32H5 */ +#if defined(STM32U5) #define GPIO_AF0_S2DSTOP GPIO_AF0_SRDSTOP #define GPIO_AF11_LPGPIO GPIO_AF11_LPGPIO1 #endif /* STM32U5 */ + +#if defined(STM32WBA) +#define GPIO_AF11_RF_ANTSW0 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW1 GPIO_AF11_RF +#define GPIO_AF11_RF_ANTSW2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO1 GPIO_AF11_RF +#define GPIO_AF11_RF_IO2 GPIO_AF11_RF +#define GPIO_AF11_RF_IO3 GPIO_AF11_RF +#define GPIO_AF11_RF_IO4 GPIO_AF11_RF +#define GPIO_AF11_RF_IO5 GPIO_AF11_RF +#define GPIO_AF11_RF_IO6 GPIO_AF11_RF +#define GPIO_AF11_RF_IO7 GPIO_AF11_RF +#define GPIO_AF11_RF_IO8 GPIO_AF11_RF +#define GPIO_AF11_RF_IO9 GPIO_AF11_RF +#endif /* STM32WBA */ /** * @} */ @@ -694,7 +853,23 @@ extern "C" { #define GTZC_PERIPH_DCMI GTZC_PERIPH_DCMI_PSSI #define GTZC_PERIPH_LTDC GTZC_PERIPH_LTDCUSB #endif /* STM32U5 */ - +#if defined(STM32H5) +#define GTZC_PERIPH_DAC12 GTZC_PERIPH_DAC1 +#define GTZC_PERIPH_ADC12 GTZC_PERIPH_ADC +#define GTZC_PERIPH_USBFS GTZC_PERIPH_USB +#endif /* STM32H5 */ +#if defined(STM32H5) || defined(STM32U5) +#define GTZC_MCPBB_NB_VCTR_REG_MAX GTZC_MPCBB_NB_VCTR_REG_MAX +#define GTZC_MCPBB_NB_LCK_VCTR_REG_MAX GTZC_MPCBB_NB_LCK_VCTR_REG_MAX +#define GTZC_MCPBB_SUPERBLOCK_UNLOCKED GTZC_MPCBB_SUPERBLOCK_UNLOCKED +#define GTZC_MCPBB_SUPERBLOCK_LOCKED GTZC_MPCBB_SUPERBLOCK_LOCKED +#define GTZC_MCPBB_BLOCK_NSEC GTZC_MPCBB_BLOCK_NSEC +#define GTZC_MCPBB_BLOCK_SEC GTZC_MPCBB_BLOCK_SEC +#define GTZC_MCPBB_BLOCK_NPRIV GTZC_MPCBB_BLOCK_NPRIV +#define GTZC_MCPBB_BLOCK_PRIV GTZC_MPCBB_BLOCK_PRIV +#define GTZC_MCPBB_LOCK_OFF GTZC_MPCBB_LOCK_OFF +#define GTZC_MCPBB_LOCK_ON GTZC_MPCBB_LOCK_ON +#endif /* STM32H5 || STM32U5 */ /** * @} */ @@ -721,6 +896,10 @@ extern "C" { #define __HAL_HRTIM_SetCompare __HAL_HRTIM_SETCOMPARE #define __HAL_HRTIM_GetCompare __HAL_HRTIM_GETCOMPARE +#if defined(STM32F3) || defined(STM32G4) || defined(STM32H7) +#define HRTIMInterruptResquests HRTIMInterruptRequests +#endif /* STM32F3 || STM32G4 || STM32H7 */ + #if defined(STM32G4) #define HAL_HRTIM_ExternalEventCounterConfig HAL_HRTIM_ExtEventCounterConfig #define HAL_HRTIM_ExternalEventCounterEnable HAL_HRTIM_ExtEventCounterEnable @@ -858,8 +1037,8 @@ extern "C" { #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) - #endif /* STM32F3 */ + /** * @} */ @@ -875,7 +1054,8 @@ extern "C" { #define I2C_NOSTRETCH_ENABLED I2C_NOSTRETCH_ENABLE #define I2C_ANALOGFILTER_ENABLED I2C_ANALOGFILTER_ENABLE #define I2C_ANALOGFILTER_DISABLED I2C_ANALOGFILTER_DISABLE -#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || defined(STM32L1) || defined(STM32F7) +#if defined(STM32F0) || defined(STM32F1) || defined(STM32F3) || defined(STM32G0) || defined(STM32L4) || \ + defined(STM32L1) || defined(STM32F7) #define HAL_I2C_STATE_MEM_BUSY_TX HAL_I2C_STATE_BUSY_TX #define HAL_I2C_STATE_MEM_BUSY_RX HAL_I2C_STATE_BUSY_RX #define HAL_I2C_STATE_MASTER_BUSY_TX HAL_I2C_STATE_BUSY_TX @@ -1109,22 +1289,42 @@ extern "C" { #define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1 #define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1 -#if defined(STM32F7) +#if defined(STM32H5) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_BKP_SRAM TAMP_DEVICESECRETS_ERASE_BKPSRAM +#endif /* STM32H5 || STM32H7RS || STM32N6 */ + +#if defined(STM32WBA) +#define TAMP_SECRETDEVICE_ERASE_NONE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_SRAM2 TAMP_DEVICESECRETS_ERASE_SRAM2 +#define TAMP_SECRETDEVICE_ERASE_RHUK TAMP_DEVICESECRETS_ERASE_RHUK +#define TAMP_SECRETDEVICE_ERASE_ICACHE TAMP_DEVICESECRETS_ERASE_ICACHE +#define TAMP_SECRETDEVICE_ERASE_SAES_AES_HASH TAMP_DEVICESECRETS_ERASE_SAES_AES_HASH +#define TAMP_SECRETDEVICE_ERASE_PKA_SRAM TAMP_DEVICESECRETS_ERASE_PKA_SRAM +#define TAMP_SECRETDEVICE_ERASE_ALL TAMP_DEVICESECRETS_ERASE_ALL +#endif /* STM32WBA */ + +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define TAMP_SECRETDEVICE_ERASE_DISABLE TAMP_DEVICESECRETS_ERASE_NONE +#define TAMP_SECRETDEVICE_ERASE_ENABLE TAMP_SECRETDEVICE_ERASE_ALL +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +#if defined(STM32F7) || defined(STM32WB) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_ENABLE_BITS_MASK #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_IT_ENABLE_BITS_MASK -#endif /* STM32F7 */ +#endif /* STM32F7 || STM32WB */ #if defined(STM32H7) #define RTC_TAMPCR_TAMPXE RTC_TAMPER_X #define RTC_TAMPCR_TAMPXIE RTC_TAMPER_X_INTERRUPT #endif /* STM32H7 */ -#if defined(STM32F7) || defined(STM32H7) +#if defined(STM32F7) || defined(STM32H7) || defined(STM32L0) || defined(STM32WB) #define RTC_TAMPER1_INTERRUPT RTC_IT_TAMP1 #define RTC_TAMPER2_INTERRUPT RTC_IT_TAMP2 #define RTC_TAMPER3_INTERRUPT RTC_IT_TAMP3 #define RTC_ALL_TAMPER_INTERRUPT RTC_IT_TAMP -#endif /* STM32F7 || STM32H7 */ +#endif /* STM32F7 || STM32H7 || STM32L0 || STM32WB */ /** * @} @@ -1291,7 +1491,7 @@ extern "C" { #define TIM_TIM3_TI1_COMP1COMP2_OUT TIM_TIM3_TI1_COMP1_COMP2 #endif -#if defined(STM32U5) +#if defined(STM32U5) || defined(STM32MP2) #define OCREF_CLEAR_SELECT_Pos OCREF_CLEAR_SELECT_POS #define OCREF_CLEAR_SELECT_Msk OCREF_CLEAR_SELECT_MSK #endif @@ -1404,30 +1604,40 @@ extern "C" { #define ETH_MMCRFAECR 0x00000198U #define ETH_MMCRGUFCR 0x000001C4U -#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ -#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ -#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ -#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ -#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */ -#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */ -#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */ -#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */ -#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input frame for transmission */ +#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */ +#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */ +#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */ +#define ETH_MAC_TXFIFO_IDLE 0x00000000U /* Tx FIFO read status: Idle */ +#define ETH_MAC_TXFIFO_READ 0x00100000U /* Tx FIFO read status: Read (transferring data to + the MAC transmitter) */ +#define ETH_MAC_TXFIFO_WAITING 0x00200000U /* Tx FIFO read status: Waiting for TxStatus from + MAC transmitter */ +#define ETH_MAC_TXFIFO_WRITING 0x00300000U /* Tx FIFO read status: Writing the received TxStatus + or flushing the TxFIFO */ +#define ETH_MAC_TRANSMISSION_PAUSE 0x00080000U /* MAC transmitter in pause */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE 0x00000000U /* MAC transmit frame controller: Idle */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING 0x00020000U /* MAC transmit frame controller: Waiting for Status + of previous frame or IFG/backoff period to be over */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF 0x00040000U /* MAC transmit frame controller: Generating and + transmitting a Pause control frame (in full duplex mode) */ +#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING 0x00060000U /* MAC transmit frame controller: Transferring input + frame for transmission */ #define ETH_MAC_MII_TRANSMIT_ACTIVE 0x00010000U /* MAC MII transmit engine active */ #define ETH_MAC_RXFIFO_EMPTY 0x00000000U /* Rx FIFO fill level: empty */ -#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */ -#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */ +#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control + de-activate threshold */ +#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control + activate threshold */ #define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */ #if defined(STM32F1) #else #define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */ #define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */ -#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */ +#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status + (or time-stamp) */ #endif -#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */ +#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and + status */ #define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */ #define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */ #define ETH_MAC_SMALL_FIFO_READ_ACTIVE 0x00000002U /* MAC small FIFO read controller active */ @@ -1435,6 +1645,8 @@ extern "C" { #define ETH_MAC_SMALL_FIFO_RW_ACTIVE 0x00000006U /* MAC small FIFO read / write controllers active */ #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE 0x00000001U /* MAC MII receive protocol engine active */ +#define ETH_TxPacketConfig ETH_TxPacketConfigTypeDef /* Transmit Packet Configuration structure definition */ + /** * @} */ @@ -1598,7 +1810,8 @@ extern "C" { #define HAL_EnableDBGStandbyMode HAL_DBGMCU_EnableDBGStandbyMode #define HAL_DisableDBGStandbyMode HAL_DBGMCU_DisableDBGStandbyMode #define HAL_DBG_LowPowerConfig(Periph, cmd) (((cmd\ - )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) + )==ENABLE)? HAL_DBGMCU_DBG_EnableLowPowerConfig(Periph) : \ + HAL_DBGMCU_DBG_DisableLowPowerConfig(Periph)) #define HAL_VREFINT_OutputSelect HAL_SYSCFG_VREFINT_OutputSelect #define HAL_Lock_Cmd(cmd) (((cmd)==ENABLE) ? HAL_SYSCFG_Enable_Lock_VREFINT() : HAL_SYSCFG_Disable_Lock_VREFINT()) #if defined(STM32L0) @@ -1607,8 +1820,10 @@ extern "C" { #endif #define HAL_ADC_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_ADCEx_EnableVREFINT() : HAL_ADCEx_DisableVREFINT()) #define HAL_ADC_EnableBufferSensor_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : HAL_ADCEx_DisableVREFINTTempSensor()) -#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) + )==ENABLE) ? HAL_ADCEx_EnableVREFINTTempSensor() : \ + HAL_ADCEx_DisableVREFINTTempSensor()) +#if defined(STM32H7A3xx) || defined(STM32H7B3xx) || defined(STM32H7B0xx) || defined(STM32H7A3xxQ) || \ + defined(STM32H7B3xxQ) || defined(STM32H7B0xxQ) #define HAL_EnableSRDomainDBGStopMode HAL_EnableDomain3DBGStopMode #define HAL_DisableSRDomainDBGStopMode HAL_DisableDomain3DBGStopMode #define HAL_EnableSRDomainDBGStandbyMode HAL_EnableDomain3DBGStandbyMode @@ -1642,16 +1857,21 @@ extern "C" { #define HAL_FMPI2CEx_AnalogFilter_Config HAL_FMPI2CEx_ConfigAnalogFilter #define HAL_FMPI2CEx_DigitalFilter_Config HAL_FMPI2CEx_ConfigDigitalFilter -#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd\ - )==ENABLE)? HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) +#define HAL_I2CFastModePlusConfig(SYSCFG_I2CFastModePlus, cmd) (((cmd) == ENABLE)? \ + HAL_I2CEx_EnableFastModePlus(SYSCFG_I2CFastModePlus): \ + HAL_I2CEx_DisableFastModePlus(SYSCFG_I2CFastModePlus)) -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || \ + defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || \ + defined(STM32L4) || defined(STM32L5) || defined(STM32G4) || defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_IT HAL_I2C_Master_Seq_Transmit_IT #define HAL_I2C_Master_Sequential_Receive_IT HAL_I2C_Master_Seq_Receive_IT #define HAL_I2C_Slave_Sequential_Transmit_IT HAL_I2C_Slave_Seq_Transmit_IT #define HAL_I2C_Slave_Sequential_Receive_IT HAL_I2C_Slave_Seq_Receive_IT -#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || STM32L4 || STM32L5 || STM32G4 || STM32L1 */ -#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) +#endif /* STM32H7 || STM32WB || STM32G0 || STM32F0 || STM32F1 || STM32F2 || STM32F3 || STM32F4 || STM32F7 || STM32L0 || + STM32L4 || STM32L5 || STM32G4 || STM32L1 */ +#if defined(STM32H7) || defined(STM32WB) || defined(STM32G0) || defined(STM32F4) || defined(STM32F7) || \ + defined(STM32L0) || defined(STM32L4) || defined(STM32L5) || defined(STM32G4)|| defined(STM32L1) #define HAL_I2C_Master_Sequential_Transmit_DMA HAL_I2C_Master_Seq_Transmit_DMA #define HAL_I2C_Master_Sequential_Receive_DMA HAL_I2C_Master_Seq_Receive_DMA #define HAL_I2C_Slave_Sequential_Transmit_DMA HAL_I2C_Slave_Seq_Transmit_DMA @@ -1776,6 +1996,17 @@ extern "C" { #define PWR_SRAM5_PAGE13_STOP_RETENTION PWR_SRAM5_PAGE13_STOP #define PWR_SRAM5_FULL_STOP_RETENTION PWR_SRAM5_FULL_STOP +#define PWR_SRAM6_PAGE1_STOP_RETENTION PWR_SRAM6_PAGE1_STOP +#define PWR_SRAM6_PAGE2_STOP_RETENTION PWR_SRAM6_PAGE2_STOP +#define PWR_SRAM6_PAGE3_STOP_RETENTION PWR_SRAM6_PAGE3_STOP +#define PWR_SRAM6_PAGE4_STOP_RETENTION PWR_SRAM6_PAGE4_STOP +#define PWR_SRAM6_PAGE5_STOP_RETENTION PWR_SRAM6_PAGE5_STOP +#define PWR_SRAM6_PAGE6_STOP_RETENTION PWR_SRAM6_PAGE6_STOP +#define PWR_SRAM6_PAGE7_STOP_RETENTION PWR_SRAM6_PAGE7_STOP +#define PWR_SRAM6_PAGE8_STOP_RETENTION PWR_SRAM6_PAGE8_STOP +#define PWR_SRAM6_FULL_STOP_RETENTION PWR_SRAM6_FULL_STOP + + #define PWR_ICACHE_FULL_STOP_RETENTION PWR_ICACHE_FULL_STOP #define PWR_DCACHE1_FULL_STOP_RETENTION PWR_DCACHE1_FULL_STOP #define PWR_DCACHE2_FULL_STOP_RETENTION PWR_DCACHE2_FULL_STOP @@ -1784,6 +2015,8 @@ extern "C" { #define PWR_PKA32RAM_FULL_STOP_RETENTION PWR_PKA32RAM_FULL_STOP #define PWR_GRAPHICPRAM_FULL_STOP_RETENTION PWR_GRAPHICPRAM_FULL_STOP #define PWR_DSIRAM_FULL_STOP_RETENTION PWR_DSIRAM_FULL_STOP +#define PWR_JPEGRAM_FULL_STOP_RETENTION PWR_JPEGRAM_FULL_STOP + #define PWR_SRAM2_PAGE1_STANDBY_RETENTION PWR_SRAM2_PAGE1_STANDBY #define PWR_SRAM2_PAGE2_STANDBY_RETENTION PWR_SRAM2_PAGE2_STANDBY @@ -1794,6 +2027,7 @@ extern "C" { #define PWR_SRAM3_FULL_RUN_RETENTION PWR_SRAM3_FULL_RUN #define PWR_SRAM4_FULL_RUN_RETENTION PWR_SRAM4_FULL_RUN #define PWR_SRAM5_FULL_RUN_RETENTION PWR_SRAM5_FULL_RUN +#define PWR_SRAM6_FULL_RUN_RETENTION PWR_SRAM6_FULL_RUN #define PWR_ALL_RAM_RUN_RETENTION_MASK PWR_ALL_RAM_RUN_MASK #endif @@ -1802,6 +2036,20 @@ extern "C" { * @} */ +/** @defgroup HAL_RTC_Aliased_Functions HAL RTC Aliased Functions maintained for legacy purpose + * @{ + */ +#if defined(STM32H5) || defined(STM32WBA) || defined(STM32H7RS) || defined(STM32N6) +#define HAL_RTCEx_SetBoothardwareKey HAL_RTCEx_LockBootHardwareKey +#define HAL_RTCEx_BKUPBlock_Enable HAL_RTCEx_BKUPBlock +#define HAL_RTCEx_BKUPBlock_Disable HAL_RTCEx_BKUPUnblock +#define HAL_RTCEx_Erase_SecretDev_Conf HAL_RTCEx_ConfigEraseDeviceSecrets +#endif /* STM32H5 || STM32WBA || STM32H7RS || STM32N6 */ + +/** + * @} + */ + /** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose * @{ */ @@ -1827,7 +2075,8 @@ extern "C" { #define HAL_TIM_DMAError TIM_DMAError #define HAL_TIM_DMACaptureCplt TIM_DMACaptureCplt #define HAL_TIMEx_DMACommutationCplt TIMEx_DMACommutationCplt -#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) +#if defined(STM32H7) || defined(STM32G0) || defined(STM32F0) || defined(STM32F1) || defined(STM32F2) || \ + defined(STM32F3) || defined(STM32F4) || defined(STM32F7) || defined(STM32L0) || defined(STM32L4) #define HAL_TIM_SlaveConfigSynchronization HAL_TIM_SlaveConfigSynchro #define HAL_TIM_SlaveConfigSynchronization_IT HAL_TIM_SlaveConfigSynchro_IT #define HAL_TIMEx_CommutationCallback HAL_TIMEx_CommutCallback @@ -1903,6 +2152,13 @@ extern "C" { #define UFB_MODE_BitNumber UFB_MODE_BIT_NUMBER #define CMP_PD_BitNumber CMP_PD_BIT_NUMBER +#if defined(STM32H7RS) || defined(STM32N6) +#define FMC_SWAPBMAP_DISABLE FMC_SWAPBANK_MODE0 +#define FMC_SWAPBMAP_SDRAM_SRAM FMC_SWAPBANK_MODE1 +#define HAL_SetFMCMemorySwappingConfig HAL_FMC_SetBankSwapConfig +#define HAL_GetFMCMemorySwappingConfig HAL_FMC_GetBankSwapConfig +#endif /* STM32H7RS || STM32N6 */ + /** * @} */ @@ -2084,7 +2340,8 @@ extern "C" { #define COMP_STOP __HAL_COMP_DISABLE #define COMP_LOCK __HAL_COMP_LOCK -#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) +#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || \ + defined(STM32F334x8) || defined(STM32F328xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP6_EXTI_ENABLE_RISING_EDGE()) @@ -2109,8 +2366,8 @@ extern "C" { #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F302xE) || defined(STM32F302xC) +#endif +#if defined(STM32F302xE) || defined(STM32F302xC) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \ @@ -2143,8 +2400,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP6_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) +#endif +#if defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F303xC) || defined(STM32F358xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \ ((__EXTILINE__) == COMP_EXTI_LINE_COMP3) ? __HAL_COMP_COMP3_EXTI_ENABLE_RISING_EDGE() : \ @@ -2201,8 +2458,8 @@ extern "C" { ((__FLAG__) == COMP_EXTI_LINE_COMP5) ? __HAL_COMP_COMP5_EXTI_CLEAR_FLAG() : \ ((__FLAG__) == COMP_EXTI_LINE_COMP6) ? __HAL_COMP_COMP6_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP7_EXTI_CLEAR_FLAG()) -# endif -# if defined(STM32F373xC) ||defined(STM32F378xx) +#endif +#if defined(STM32F373xC) ||defined(STM32F378xx) #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) #define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_DISABLE_RISING_EDGE() : \ @@ -2219,7 +2476,7 @@ extern "C" { __HAL_COMP_COMP2_EXTI_GET_FLAG()) #define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__) (((__FLAG__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_CLEAR_FLAG() : \ __HAL_COMP_COMP2_EXTI_CLEAR_FLAG()) -# endif +#endif #else #define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP1) ? __HAL_COMP_COMP1_EXTI_ENABLE_RISING_EDGE() : \ __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE()) @@ -2256,8 +2513,10 @@ extern "C" { /** @defgroup HAL_COMP_Aliased_Functions HAL COMP Aliased Functions maintained for legacy purpose * @{ */ -#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ -#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is done into HAL_COMP_Init() */ +#define HAL_COMP_Start_IT HAL_COMP_Start /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ +#define HAL_COMP_Stop_IT HAL_COMP_Stop /* Function considered as legacy as EXTI event or IT configuration is + done into HAL_COMP_Init() */ /** * @} */ @@ -2416,7 +2675,9 @@ extern "C" { #define __HAL_PWR_INTERNALWAKEUP_ENABLE HAL_PWREx_EnableInternalWakeUpLine #define __HAL_PWR_PULL_UP_DOWN_CONFIG_DISABLE HAL_PWREx_DisablePullUpPullDownConfig #define __HAL_PWR_PULL_UP_DOWN_CONFIG_ENABLE HAL_PWREx_EnablePullUpPullDownConfig -#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); } while(0) +#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() do { __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(); \ + __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE(); \ + } while(0) #define __HAL_PWR_PVD_EXTI_EVENT_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_EVENT #define __HAL_PWR_PVD_EXTI_EVENT_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_EVENT #define __HAL_PWR_PVD_EXTI_FALLINGTRIGGER_DISABLE __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE @@ -2425,8 +2686,12 @@ extern "C" { #define __HAL_PWR_PVD_EXTI_RISINGTRIGGER_ENABLE __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE -#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2();HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); } while(0) -#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2();HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); } while(0) +#define __HAL_PWR_PVM_DISABLE() do { HAL_PWREx_DisablePVM1();HAL_PWREx_DisablePVM2(); \ + HAL_PWREx_DisablePVM3();HAL_PWREx_DisablePVM4(); \ + } while(0) +#define __HAL_PWR_PVM_ENABLE() do { HAL_PWREx_EnablePVM1();HAL_PWREx_EnablePVM2(); \ + HAL_PWREx_EnablePVM3();HAL_PWREx_EnablePVM4(); \ + } while(0) #define __HAL_PWR_SRAM2CONTENT_PRESERVE_DISABLE HAL_PWREx_DisableSRAM2ContentRetention #define __HAL_PWR_SRAM2CONTENT_PRESERVE_ENABLE HAL_PWREx_EnableSRAM2ContentRetention #define __HAL_PWR_VDDIO2_DISABLE HAL_PWREx_DisableVddIO2 @@ -2462,8 +2727,8 @@ extern "C" { #define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI #define HAL_RCC_CCSCallback HAL_RCC_CSSCallback -#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd\ - )==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) +#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? \ + HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT()) #define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE #define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE @@ -2513,6 +2778,12 @@ extern "C" { #define __APB1_RELEASE_RESET __HAL_RCC_APB1_RELEASE_RESET #define __APB2_FORCE_RESET __HAL_RCC_APB2_FORCE_RESET #define __APB2_RELEASE_RESET __HAL_RCC_APB2_RELEASE_RESET +#if defined(STM32C0) +#define __HAL_RCC_APB1_FORCE_RESET __HAL_RCC_APB1_GRP1_FORCE_RESET +#define __HAL_RCC_APB1_RELEASE_RESET __HAL_RCC_APB1_GRP1_RELEASE_RESET +#define __HAL_RCC_APB2_FORCE_RESET __HAL_RCC_APB1_GRP2_FORCE_RESET +#define __HAL_RCC_APB2_RELEASE_RESET __HAL_RCC_APB1_GRP2_RELEASE_RESET +#endif /* STM32C0 */ #define __BKP_CLK_DISABLE __HAL_RCC_BKP_CLK_DISABLE #define __BKP_CLK_ENABLE __HAL_RCC_BKP_CLK_ENABLE #define __BKP_FORCE_RESET __HAL_RCC_BKP_FORCE_RESET @@ -3436,7 +3707,14 @@ extern "C" { #define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2 -#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || defined(STM32WL) || defined(STM32C0) +#if defined(STM32U0) +#define RCC_SYSCLKSOURCE_STATUS_PLLR RCC_SYSCLKSOURCE_STATUS_PLLCLK +#endif + + +#if defined(STM32L4) || defined(STM32WB) || defined(STM32G0) || defined(STM32G4) || defined(STM32L5) || \ + defined(STM32WL) || defined(STM32C0) || defined(STM32N6) || defined(STM32H7RS) || \ + defined(STM32U0) #define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE #else #define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK @@ -3538,8 +3816,10 @@ extern "C" { #define __HAL_RCC_GET_DFSDM_SOURCE __HAL_RCC_GET_DFSDM1_SOURCE #define RCC_DFSDM1CLKSOURCE_PCLK RCC_DFSDM1CLKSOURCE_PCLK2 #define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1 +#if !defined(STM32U0) #define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1 #define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1 +#endif #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1 #define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2 @@ -3581,6 +3861,92 @@ extern "C" { #define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE #endif /* STM32U5 */ +#if defined(STM32H5) +#define __HAL_RCC_PLLFRACN_ENABLE __HAL_RCC_PLL_FRACN_ENABLE +#define __HAL_RCC_PLLFRACN_DISABLE __HAL_RCC_PLL_FRACN_DISABLE +#define __HAL_RCC_PLLFRACN_CONFIG __HAL_RCC_PLL_FRACN_CONFIG +#define IS_RCC_PLLFRACN_VALUE IS_RCC_PLL_FRACN_VALUE + +#define RCC_PLLSOURCE_NONE RCC_PLL1_SOURCE_NONE +#define RCC_PLLSOURCE_HSI RCC_PLL1_SOURCE_HSI +#define RCC_PLLSOURCE_CSI RCC_PLL1_SOURCE_CSI +#define RCC_PLLSOURCE_HSE RCC_PLL1_SOURCE_HSE +#define RCC_PLLVCIRANGE_0 RCC_PLL1_VCIRANGE_0 +#define RCC_PLLVCIRANGE_1 RCC_PLL1_VCIRANGE_1 +#define RCC_PLLVCIRANGE_2 RCC_PLL1_VCIRANGE_2 +#define RCC_PLLVCIRANGE_3 RCC_PLL1_VCIRANGE_3 +#define RCC_PLL1VCOWIDE RCC_PLL1_VCORANGE_WIDE +#define RCC_PLL1VCOMEDIUM RCC_PLL1_VCORANGE_MEDIUM + +#define IS_RCC_PLLSOURCE IS_RCC_PLL1_SOURCE +#define IS_RCC_PLLRGE_VALUE IS_RCC_PLL1_VCIRGE_VALUE +#define IS_RCC_PLLVCORGE_VALUE IS_RCC_PLL1_VCORGE_VALUE +#define IS_RCC_PLLCLOCKOUT_VALUE IS_RCC_PLL1_CLOCKOUT_VALUE +#define IS_RCC_PLL_FRACN_VALUE IS_RCC_PLL1_FRACN_VALUE +#define IS_RCC_PLLM_VALUE IS_RCC_PLL1_DIVM_VALUE +#define IS_RCC_PLLN_VALUE IS_RCC_PLL1_MULN_VALUE +#define IS_RCC_PLLP_VALUE IS_RCC_PLL1_DIVP_VALUE +#define IS_RCC_PLLQ_VALUE IS_RCC_PLL1_DIVQ_VALUE +#define IS_RCC_PLLR_VALUE IS_RCC_PLL1_DIVR_VALUE + +#define __HAL_RCC_PLL_ENABLE __HAL_RCC_PLL1_ENABLE +#define __HAL_RCC_PLL_DISABLE __HAL_RCC_PLL1_DISABLE +#define __HAL_RCC_PLL_FRACN_ENABLE __HAL_RCC_PLL1_FRACN_ENABLE +#define __HAL_RCC_PLL_FRACN_DISABLE __HAL_RCC_PLL1_FRACN_DISABLE +#define __HAL_RCC_PLL_CONFIG __HAL_RCC_PLL1_CONFIG +#define __HAL_RCC_PLL_PLLSOURCE_CONFIG __HAL_RCC_PLL1_PLLSOURCE_CONFIG +#define __HAL_RCC_PLL_DIVM_CONFIG __HAL_RCC_PLL1_DIVM_CONFIG +#define __HAL_RCC_PLL_FRACN_CONFIG __HAL_RCC_PLL1_FRACN_CONFIG +#define __HAL_RCC_PLL_VCIRANGE __HAL_RCC_PLL1_VCIRANGE +#define __HAL_RCC_PLL_VCORANGE __HAL_RCC_PLL1_VCORANGE +#define __HAL_RCC_GET_PLL_OSCSOURCE __HAL_RCC_GET_PLL1_OSCSOURCE +#define __HAL_RCC_PLLCLKOUT_ENABLE __HAL_RCC_PLL1_CLKOUT_ENABLE +#define __HAL_RCC_PLLCLKOUT_DISABLE __HAL_RCC_PLL1_CLKOUT_DISABLE +#define __HAL_RCC_GET_PLLCLKOUT_CONFIG __HAL_RCC_GET_PLL1_CLKOUT_CONFIG + +#define __HAL_RCC_PLL2FRACN_ENABLE __HAL_RCC_PLL2_FRACN_ENABLE +#define __HAL_RCC_PLL2FRACN_DISABLE __HAL_RCC_PLL2_FRACN_DISABLE +#define __HAL_RCC_PLL2CLKOUT_ENABLE __HAL_RCC_PLL2_CLKOUT_ENABLE +#define __HAL_RCC_PLL2CLKOUT_DISABLE __HAL_RCC_PLL2_CLKOUT_DISABLE +#define __HAL_RCC_PLL2FRACN_CONFIG __HAL_RCC_PLL2_FRACN_CONFIG +#define __HAL_RCC_GET_PLL2CLKOUT_CONFIG __HAL_RCC_GET_PLL2_CLKOUT_CONFIG + +#define __HAL_RCC_PLL3FRACN_ENABLE __HAL_RCC_PLL3_FRACN_ENABLE +#define __HAL_RCC_PLL3FRACN_DISABLE __HAL_RCC_PLL3_FRACN_DISABLE +#define __HAL_RCC_PLL3CLKOUT_ENABLE __HAL_RCC_PLL3_CLKOUT_ENABLE +#define __HAL_RCC_PLL3CLKOUT_DISABLE __HAL_RCC_PLL3_CLKOUT_DISABLE +#define __HAL_RCC_PLL3FRACN_CONFIG __HAL_RCC_PLL3_FRACN_CONFIG +#define __HAL_RCC_GET_PLL3CLKOUT_CONFIG __HAL_RCC_GET_PLL3_CLKOUT_CONFIG + +#define RCC_PLL2VCIRANGE_0 RCC_PLL2_VCIRANGE_0 +#define RCC_PLL2VCIRANGE_1 RCC_PLL2_VCIRANGE_1 +#define RCC_PLL2VCIRANGE_2 RCC_PLL2_VCIRANGE_2 +#define RCC_PLL2VCIRANGE_3 RCC_PLL2_VCIRANGE_3 + +#define RCC_PLL2VCOWIDE RCC_PLL2_VCORANGE_WIDE +#define RCC_PLL2VCOMEDIUM RCC_PLL2_VCORANGE_MEDIUM + +#define RCC_PLL2SOURCE_NONE RCC_PLL2_SOURCE_NONE +#define RCC_PLL2SOURCE_HSI RCC_PLL2_SOURCE_HSI +#define RCC_PLL2SOURCE_CSI RCC_PLL2_SOURCE_CSI +#define RCC_PLL2SOURCE_HSE RCC_PLL2_SOURCE_HSE + +#define RCC_PLL3VCIRANGE_0 RCC_PLL3_VCIRANGE_0 +#define RCC_PLL3VCIRANGE_1 RCC_PLL3_VCIRANGE_1 +#define RCC_PLL3VCIRANGE_2 RCC_PLL3_VCIRANGE_2 +#define RCC_PLL3VCIRANGE_3 RCC_PLL3_VCIRANGE_3 + +#define RCC_PLL3VCOWIDE RCC_PLL3_VCORANGE_WIDE +#define RCC_PLL3VCOMEDIUM RCC_PLL3_VCORANGE_MEDIUM + +#define RCC_PLL3SOURCE_NONE RCC_PLL3_SOURCE_NONE +#define RCC_PLL3SOURCE_HSI RCC_PLL3_SOURCE_HSI +#define RCC_PLL3SOURCE_CSI RCC_PLL3_SOURCE_CSI +#define RCC_PLL3SOURCE_HSE RCC_PLL3_SOURCE_HSE + + +#endif /* STM32H5 */ + /** * @} */ @@ -3597,8 +3963,10 @@ extern "C" { /** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose * @{ */ -#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || defined (STM32L4P5xx) || \ - defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || defined (STM32C0) +#if defined (STM32G0) || defined (STM32L5) || defined (STM32L412xx) || defined (STM32L422xx) || \ + defined (STM32L4P5xx)|| defined (STM32L4Q5xx) || defined (STM32G4) || defined (STM32WL) || defined (STM32U5) || \ + defined (STM32WBA) || defined (STM32H5) || defined (STM32C0) || defined (STM32N6) || \ + defined (STM32H7RS) || defined (STM32U0) || defined (STM32U3) #else #define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG #endif @@ -3633,6 +4001,13 @@ extern "C" { __HAL_RTC_TAMPER_TIMESTAMP_EXTI_GENERATE_SWIT())) #endif /* STM32F1 */ +#if defined (STM32F0) || defined (STM32F2) || defined (STM32F3) || defined (STM32F4) || defined (STM32F7) || \ + defined (STM32H7) || \ + defined (STM32L0) || defined (STM32L1) || \ + defined (STM32WB) +#define __HAL_RTC_TAMPER_GET_IT __HAL_RTC_TAMPER_GET_FLAG +#endif + #define IS_ALARM IS_RTC_ALARM #define IS_ALARM_MASK IS_RTC_ALARM_MASK #define IS_TAMPER IS_RTC_TAMPER @@ -3651,6 +4026,11 @@ extern "C" { #define __RTC_WRITEPROTECTION_ENABLE __HAL_RTC_WRITEPROTECTION_ENABLE #define __RTC_WRITEPROTECTION_DISABLE __HAL_RTC_WRITEPROTECTION_DISABLE +#if defined (STM32H5) +#define __HAL_RCC_RTCAPB_CLK_ENABLE __HAL_RCC_RTC_CLK_ENABLE +#define __HAL_RCC_RTCAPB_CLK_DISABLE __HAL_RCC_RTC_CLK_DISABLE +#endif /* STM32H5 */ + /** * @} */ @@ -3880,6 +4260,33 @@ extern "C" { #define HAL_PCD_SetTxFiFo HAL_PCDEx_SetTxFiFo #define HAL_PCD_SetRxFiFo HAL_PCDEx_SetRxFiFo +#if defined(STM32U5) +#define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSVLD +#define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINTMSK +#define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPC +#define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_PSRST +#define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_GONAKEFF +#define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUPINT +#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_IPXFRM_IISOOXFRM +#define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_CHNUM +#define USB_OTG_GLPMCFG_L1ResumeOK USB_OTG_GLPMCFG_L1RSMOK +#define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFSIZ +#define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MCNT +#define USB_OTG_HCCHAR_MC_0 USB_OTG_HCCHAR_MCNT_0 +#define USB_OTG_HCCHAR_MC_1 USB_OTG_HCCHAR_MCNT_1 +#define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERRM +#define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPNG +#define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OUTPKTERRM +#define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SD1PID_SODDFRM +#define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MCNT +#define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SD1PID_SODDFRM +#define USB_OTG_DOEPCTL_DPID USB_OTG_DOEPCTL_DPID_EONUM +#define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_RXDPID +#define USB_OTG_DOEPTSIZ_STUPCNT_0 USB_OTG_DOEPTSIZ_RXDPID_0 +#define USB_OTG_DOEPTSIZ_STUPCNT_1 USB_OTG_DOEPTSIZ_RXDPID_1 +#define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STPPCLK +#define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATEHCLK +#endif /** * @} */ @@ -3909,6 +4316,9 @@ extern "C" { #define __HAL_TIM_GetCompare __HAL_TIM_GET_COMPARE #define TIM_BREAKINPUTSOURCE_DFSDM TIM_BREAKINPUTSOURCE_DFSDM1 + +#define TIM_OCMODE_ASSYMETRIC_PWM1 TIM_OCMODE_ASYMMETRIC_PWM1 +#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_OCMODE_ASYMMETRIC_PWM2 /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32_assert_template.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32_assert_template.h index 91e5e6dce5..467ab8580d 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32_assert_template.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32_assert_template.h @@ -23,7 +23,7 @@ #define __STM32_ASSERT_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -39,11 +39,11 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h index a823722b78..d6e20284fd 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal.h @@ -537,9 +537,9 @@ typedef enum */ /* Legacy define */ #define __HAL_SYSCFG_SRAM2_WRP_1_31_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE -#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do {assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ - LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__);\ - }while(0) +#define __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE(__SRAM2WRP__) do { assert_param(IS_SYSCFG_SRAM2WRP_PAGE((__SRAM2WRP__)));\ + LL_SYSCFG_EnableSRAM2PageWRP_0_31(__SRAM2WRP__); \ + } while(0) /** @brief SRAM2 page write protection unlock prior to erase * @note Writing a wrong key reactivates the write protection @@ -593,13 +593,13 @@ typedef enum /** @brief Fast mode Plus driving capability enable/disable macros * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO */ -#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ - LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \ - }while(0) +#define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do { assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ + LL_SYSCFG_EnableFastModePlus(__FASTMODEPLUS__); \ + } while(0) -#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ - LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \ - }while(0) +#define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do { assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__))); \ + LL_SYSCFG_DisableFastModePlus(__FASTMODEPLUS__); \ + } while(0) /** * @} @@ -816,8 +816,8 @@ void HAL_SYSCFG_EnableIOAnalogSwitchBooster(void); void HAL_SYSCFG_DisableIOAnalogSwitchBooster(void); #if defined(DUAL_CORE) -void HAL_SYSCFG_EnableIT(SYSCFG_InterruptTypeDef *Interrupt); -void HAL_SYSCFG_DisableIT(SYSCFG_InterruptTypeDef *Interrupt); +void HAL_SYSCFG_EnableIT(const SYSCFG_InterruptTypeDef *Interrupt); +void HAL_SYSCFG_DisableIT(const SYSCFG_InterruptTypeDef *Interrupt); #endif /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h index f7614d4efa..cae04d5136 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc.h @@ -63,7 +63,7 @@ typedef struct * @brief Structure definition of ADC instance and ADC group regular. * @note Parameters of this structure are shared within 2 scopes: * - Scope entire ADC (differentiation done for compatibility with some other STM32 series featuring ADC - * groups regular and injected): ClockPrescaler, Resolution, DataAlign, + * groups regular and injected): ClockPrescaler, Resolution, DataAlign, * ScanConvMode, EOCSelection, LowPowerAutoWait. * - Scope ADC group regular: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, * ExternalTrigConv, ExternalTrigConvEdge, DMAContinuousRequests, Overrun, OversamplingMode, Oversampling. @@ -74,7 +74,7 @@ typedef struct * group regular. * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed * without error reporting (as it can be the expected behavior in case of intended action to update another - * parameter (which fulfills the ADC state condition) on the fly). + * parameter (which fulfills the ADC state condition) on the fly). */ typedef struct { @@ -373,8 +373,8 @@ typedef struct respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 - LSB are ignored. */ - /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits). */ @@ -385,8 +385,8 @@ typedef struct respectively. Note: Analog watchdog 2 and 3 are limited to a resolution of 8 bits: if ADC resolution is 12 bits the 4 LSB are ignored, if ADC resolution is 10 bits the 2 - LSB are ignored.*/ - /*!< Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are + LSB are ignored. + Note: If ADC oversampling is enabled, ADC analog watchdog thresholds are impacted: the comparison of analog watchdog thresholds is done on oversampling final computation (after ratio and shift application): ADC data register bitfield [15:4] (12 most significant bits).*/ @@ -407,7 +407,7 @@ typedef struct /* States of ADC global scope */ #define HAL_ADC_STATE_RESET (0x00000000UL) /*!< ADC not yet initialized or disabled */ #define HAL_ADC_STATE_READY (0x00000001UL) /*!< ADC peripheral ready for use */ -#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy due to internal process (ex : calibration) */ +#define HAL_ADC_STATE_BUSY_INTERNAL (0x00000002UL) /*!< ADC is busy from internal process (ex : calibration, ...) */ #define HAL_ADC_STATE_TIMEOUT (0x00000004UL) /*!< TimeOut occurrence */ /* States of ADC errors */ @@ -538,37 +538,38 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_CLOCK_SYNC_PCLK_DIV1 (LL_ADC_CLOCK_SYNC_PCLK_DIV1) /*!< ADC synchronous clock from AHB clock - without prescaler. This configuration must be enabled only if PCLK has a 50% duty clock cycle (APB prescaler - configured inside the RCC must be bypassed and the system clock must by 50% duty cycle) */ + without prescaler. This configuration must be enabled only if PCLK has + a 50% duty clock cycle (APB prescaler configured inside the RCC must + be bypassed and the system clock must by 50% duty cycle) */ #define ADC_CLOCK_SYNC_PCLK_DIV2 (LL_ADC_CLOCK_SYNC_PCLK_DIV2) /*!< ADC synchronous clock from AHB clock - with prescaler division by 2 */ + with prescaler division by 2 */ #define ADC_CLOCK_SYNC_PCLK_DIV4 (LL_ADC_CLOCK_SYNC_PCLK_DIV4) /*!< ADC synchronous clock from AHB clock - with prescaler division by 4 */ + with prescaler division by 4 */ #define ADC_CLOCK_ASYNC_DIV1 (LL_ADC_CLOCK_ASYNC_DIV1) /*!< ADC asynchronous clock without - prescaler */ + prescaler */ #define ADC_CLOCK_ASYNC_DIV2 (LL_ADC_CLOCK_ASYNC_DIV2) /*!< ADC asynchronous clock with prescaler - division by 2 */ + division by 2 */ #define ADC_CLOCK_ASYNC_DIV4 (LL_ADC_CLOCK_ASYNC_DIV4) /*!< ADC asynchronous clock with prescaler - division by 4 */ + division by 4 */ #define ADC_CLOCK_ASYNC_DIV6 (LL_ADC_CLOCK_ASYNC_DIV6) /*!< ADC asynchronous clock with prescaler - division by 6 */ + division by 6 */ #define ADC_CLOCK_ASYNC_DIV8 (LL_ADC_CLOCK_ASYNC_DIV8) /*!< ADC asynchronous clock with prescaler - division by 8 */ + division by 8 */ #define ADC_CLOCK_ASYNC_DIV10 (LL_ADC_CLOCK_ASYNC_DIV10) /*!< ADC asynchronous clock with prescaler - division by 10 */ + division by 10 */ #define ADC_CLOCK_ASYNC_DIV12 (LL_ADC_CLOCK_ASYNC_DIV12) /*!< ADC asynchronous clock with prescaler - division by 12 */ + division by 12 */ #define ADC_CLOCK_ASYNC_DIV16 (LL_ADC_CLOCK_ASYNC_DIV16) /*!< ADC asynchronous clock with prescaler - division by 16 */ + division by 16 */ #define ADC_CLOCK_ASYNC_DIV32 (LL_ADC_CLOCK_ASYNC_DIV32) /*!< ADC asynchronous clock with prescaler - division by 32 */ + division by 32 */ #define ADC_CLOCK_ASYNC_DIV64 (LL_ADC_CLOCK_ASYNC_DIV64) /*!< ADC asynchronous clock with prescaler - division by 64 */ + division by 64 */ #define ADC_CLOCK_ASYNC_DIV128 (LL_ADC_CLOCK_ASYNC_DIV128) /*!< ADC asynchronous clock with prescaler - division by 128 */ + division by 128 */ #define ADC_CLOCK_ASYNC_DIV256 (LL_ADC_CLOCK_ASYNC_DIV256) /*!< ADC asynchronous clock with prescaler - division by 256 */ + division by 256 */ /** * @} */ @@ -588,9 +589,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_DATAALIGN_RIGHT (LL_ADC_DATA_ALIGN_RIGHT) /*!< ADC conversion data alignment: right aligned - (alignment on data register LSB bit 0)*/ + (alignment on data register LSB bit 0)*/ #define ADC_DATAALIGN_LEFT (LL_ADC_DATA_ALIGN_LEFT) /*!< ADC conversion data alignment: left aligned - (alignment on data register MSB bit 15)*/ + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -613,18 +614,20 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /* warned of change of setting choices with assert check. */ /* Sequencer set to fully configurable */ #define ADC_SCAN_DISABLE (0x00000000UL) /*!< Sequencer set to fully configurable: - only the rank 1 is enabled (no scan sequence on several ranks) */ + only the rank 1 is enabled (no scan sequence on several ranks) */ #define ADC_SCAN_ENABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer set to fully configurable: - sequencer length and each rank affectation to a channel are configurable. */ + sequencer length and each rank affectation to a channel are configurable. */ /* Sequencer set to not fully configurable */ #define ADC_SCAN_SEQ_FIXED (ADC_SCAN_SEQ_FIXED_INT) /*!< Sequencer set to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, - channel 1 fixed on rank1, ...). Scan direction forward: from channel 0 to channel 18 */ + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction forward: from channel 0 to channel 18 */ #define ADC_SCAN_SEQ_FIXED_BACKWARD (ADC_SCAN_SEQ_FIXED_INT \ | ADC_CFGR1_SCANDIR) /*!< Sequencer set to not fully configurable: - sequencer length and each rank affectation to a channel are fixed by channel HW number (channel 0 fixed on rank 0, - channel 1 fixed on rank1, ...). Scan direction backward: from channel 18 to channel 0 */ + sequencer length and each rank affectation to a channel are fixed by + channel HW number (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + Scan direction backward: from channel 18 to channel 0 */ #define ADC_SCAN_DIRECTION_FORWARD (ADC_SCAN_SEQ_FIXED) /* For compatibility with other STM32 series */ #define ADC_SCAN_DIRECTION_BACKWARD (ADC_SCAN_SEQ_FIXED_BACKWARD) /* For compatibility with other STM32 series */ @@ -636,27 +639,20 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ /* ADC group regular trigger sources for all ADC instances */ -#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< Software start. */ -/** ADC group regular conversion trigger from external peripheral */ -#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< TIM1 TRGO. Trigger edge set to - rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< TIM1 channel 4 event (capture - compare: input capture or output - capture). Trigger edge set to - rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< TIM2 TRGO. Trigger edge set to - rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< TIM2 channel 4 event (capture - compare: input capture or output - capture). Trigger edge set to - rising edge (default setting). */ -#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< TIM2 channel 3 event (capture - compare: input capture or output - capture). Trigger edge set to - rising edge (default setting). */ -#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< External interrupt line 11. Trigger - edge set to rising edge (default - setting). */ +#define ADC_SOFTWARE_START (LL_ADC_REG_TRIG_SOFTWARE) /*!< ADC group regular conversion + trigger software start */ +#define ADC_EXTERNALTRIG_T1_TRGO2 (LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 TRGO. */ +#define ADC_EXTERNALTRIG_T1_CC4 (LL_ADC_REG_TRIG_EXT_TIM1_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM1 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_T2_TRGO (LL_ADC_REG_TRIG_EXT_TIM2_TRGO) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 TRGO. */ +#define ADC_EXTERNALTRIG_T2_CC4 (LL_ADC_REG_TRIG_EXT_TIM2_CH4) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 channel 4 event (capture compare). */ +#define ADC_EXTERNALTRIG_T2_CC3 (LL_ADC_REG_TRIG_EXT_TIM2_CH3) /*!< ADC group regular conversion + trigger from external peripheral: TIM2 channel 3 event (capture compare). */ +#define ADC_EXTERNALTRIG_EXT_IT11 (LL_ADC_REG_TRIG_EXT_EXTI_LINE11) /*!< ADC group regular conversion + trigger from external peripheral: external interrupt line 11. */ /** * @} */ @@ -665,14 +661,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_EXTERNALTRIGCONVEDGE_NONE (0x00000000UL) /*!< ADC group regular trigger - detection disabled (SW start)*/ -#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular trigger - polarity set to rising edge */ -#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular trigger - polarity set to falling edge */ -#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular trigger - polarity set to both rising and - falling edges */ + disabled (SW start)*/ +#define ADC_EXTERNALTRIGCONVEDGE_RISING (LL_ADC_REG_TRIG_EXT_RISING) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define ADC_EXTERNALTRIGCONVEDGE_FALLING (LL_ADC_REG_TRIG_EXT_FALLING) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING (LL_ADC_REG_TRIG_EXT_RISINGFALLING) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -689,13 +684,10 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -/** - * @brief ADC group regular behavior in case of overrun - */ -#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case of - overrun: data preserved */ -#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case of - overrun: data overwritten */ +#define ADC_OVR_DATA_PRESERVED (LL_ADC_REG_OVR_DATA_PRESERVED) /*!< ADC group regular behavior in case + of overrun: data preserved */ +#define ADC_OVR_DATA_OVERWRITTEN (LL_ADC_REG_OVR_DATA_OVERWRITTEN) /*!< ADC group regular behavior in case + of overrun: data overwritten */ /** * @} */ @@ -703,24 +695,25 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of ranks in - the sequence is defined by number of channels enabled, rank - of each channel is defined by channel number (channel 0 fixed - on rank 0, channel 1 fixed on rank1, ...). - Setting relevant if parameter "ScanConvMode" is set to - sequencer not fully configurable. */ -#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from sequencer. - Setting relevant if parameter "ScanConvMode" is set to - sequencer not fully configurable. */ - -#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ -#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ -#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ -#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ -#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ -#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ -#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ -#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ +#define ADC_RANK_CHANNEL_NUMBER (0x00000001U) /*!< Enable the rank of the selected channels. Number of + ranks in the sequence is defined by number of channels enabled, rank of + each channel is defined by channel number (channel 0 fixed on rank 0, + channel 1 fixed on rank1, ...). + Setting relevant if parameter "ScanConvMode" is set to sequencer not fully + configurable. */ +#define ADC_RANK_NONE (0x00000002U) /*!< Disable the selected rank (selected channel) from + sequencer. + Setting relevant if parameter "ScanConvMode" is set to sequencer not fully + configurable. */ + +#define ADC_REGULAR_RANK_1 (LL_ADC_REG_RANK_1) /*!< ADC group regular sequencer rank 1 */ +#define ADC_REGULAR_RANK_2 (LL_ADC_REG_RANK_2) /*!< ADC group regular sequencer rank 2 */ +#define ADC_REGULAR_RANK_3 (LL_ADC_REG_RANK_3) /*!< ADC group regular sequencer rank 3 */ +#define ADC_REGULAR_RANK_4 (LL_ADC_REG_RANK_4) /*!< ADC group regular sequencer rank 4 */ +#define ADC_REGULAR_RANK_5 (LL_ADC_REG_RANK_5) /*!< ADC group regular sequencer rank 5 */ +#define ADC_REGULAR_RANK_6 (LL_ADC_REG_RANK_6) /*!< ADC group regular sequencer rank 6 */ +#define ADC_REGULAR_RANK_7 (LL_ADC_REG_RANK_7) /*!< ADC group regular sequencer rank 7 */ +#define ADC_REGULAR_RANK_8 (LL_ADC_REG_RANK_8) /*!< ADC group regular sequencer rank 8 */ /** * @} */ @@ -739,13 +732,13 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ -#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ -#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ -#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ -#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ -#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ -#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ +#define ADC_SAMPLETIME_1CYCLE_5 (LL_ADC_SAMPLINGTIME_1CYCLE_5) /*!< Sampling time 1.5 ADC clock cycle */ +#define ADC_SAMPLETIME_3CYCLES_5 (LL_ADC_SAMPLINGTIME_3CYCLES_5) /*!< Sampling time 3.5 ADC clock cycles */ +#define ADC_SAMPLETIME_7CYCLES_5 (LL_ADC_SAMPLINGTIME_7CYCLES_5) /*!< Sampling time 7.5 ADC clock cycles */ +#define ADC_SAMPLETIME_12CYCLES_5 (LL_ADC_SAMPLINGTIME_12CYCLES_5) /*!< Sampling time 12.5 ADC clock cycles */ +#define ADC_SAMPLETIME_19CYCLES_5 (LL_ADC_SAMPLINGTIME_19CYCLES_5) /*!< Sampling time 19.5 ADC clock cycles */ +#define ADC_SAMPLETIME_39CYCLES_5 (LL_ADC_SAMPLINGTIME_39CYCLES_5) /*!< Sampling time 39.5 ADC clock cycles */ +#define ADC_SAMPLETIME_79CYCLES_5 (LL_ADC_SAMPLINGTIME_79CYCLES_5) /*!< Sampling time 79.5 ADC clock cycles */ #define ADC_SAMPLETIME_160CYCLES_5 (LL_ADC_SAMPLINGTIME_160CYCLES_5) /*!< Sampling time 160.5 ADC clock cycles */ /** * @} @@ -754,35 +747,36 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to /** @defgroup ADC_HAL_EC_CHANNEL ADC instance - Channel number * @{ */ -#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ -#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ -#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ -#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ -#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ -#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ -#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ -#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ -#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ -#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ -#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ -#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ -#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ -#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ -#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ -#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ -#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ -#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ -#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel Internal voltage reference*/ -#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor */ -#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: - Vbat voltage through a divider ladder of - factor 1/3 to have Vbat always below Vdda. */ -#define ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_DACCH1) /*!< Internal channel DAC channel 1. */ +#define ADC_CHANNEL_0 (LL_ADC_CHANNEL_0) /*!< External channel (GPIO pin) ADCx_IN0 */ +#define ADC_CHANNEL_1 (LL_ADC_CHANNEL_1) /*!< External channel (GPIO pin) ADCx_IN1 */ +#define ADC_CHANNEL_2 (LL_ADC_CHANNEL_2) /*!< External channel (GPIO pin) ADCx_IN2 */ +#define ADC_CHANNEL_3 (LL_ADC_CHANNEL_3) /*!< External channel (GPIO pin) ADCx_IN3 */ +#define ADC_CHANNEL_4 (LL_ADC_CHANNEL_4) /*!< External channel (GPIO pin) ADCx_IN4 */ +#define ADC_CHANNEL_5 (LL_ADC_CHANNEL_5) /*!< External channel (GPIO pin) ADCx_IN5 */ +#define ADC_CHANNEL_6 (LL_ADC_CHANNEL_6) /*!< External channel (GPIO pin) ADCx_IN6 */ +#define ADC_CHANNEL_7 (LL_ADC_CHANNEL_7) /*!< External channel (GPIO pin) ADCx_IN7 */ +#define ADC_CHANNEL_8 (LL_ADC_CHANNEL_8) /*!< External channel (GPIO pin) ADCx_IN8 */ +#define ADC_CHANNEL_9 (LL_ADC_CHANNEL_9) /*!< External channel (GPIO pin) ADCx_IN9 */ +#define ADC_CHANNEL_10 (LL_ADC_CHANNEL_10) /*!< External channel (GPIO pin) ADCx_IN10 */ +#define ADC_CHANNEL_11 (LL_ADC_CHANNEL_11) /*!< External channel (GPIO pin) ADCx_IN11 */ +#define ADC_CHANNEL_12 (LL_ADC_CHANNEL_12) /*!< External channel (GPIO pin) ADCx_IN12 */ +#define ADC_CHANNEL_13 (LL_ADC_CHANNEL_13) /*!< External channel (GPIO pin) ADCx_IN13 */ +#define ADC_CHANNEL_14 (LL_ADC_CHANNEL_14) /*!< External channel (GPIO pin) ADCx_IN14 */ +#define ADC_CHANNEL_15 (LL_ADC_CHANNEL_15) /*!< External channel (GPIO pin) ADCx_IN15 */ +#define ADC_CHANNEL_16 (LL_ADC_CHANNEL_16) /*!< External channel (GPIO pin) ADCx_IN16 */ +#define ADC_CHANNEL_17 (LL_ADC_CHANNEL_17) /*!< External channel (GPIO pin) ADCx_IN17 */ +#define ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_VREFINT) /*!< Internal channel VrefInt: Internal + voltage reference. */ +#define ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_TEMPSENSOR) /*!< Internal channel Temperature sensor. */ +#define ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_VBAT) /*!< Internal channel Vbat/3: Vbat voltage + through a divider ladder of factor 1/3 to have channel voltage always below + Vdda. */ +#define ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_DACCH1) /*!< Internal channel DAC channel 1. */ /** * @} */ -/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number +/** @defgroup ADC_HAL_EC_AWD_NUMBER Analog watchdog - ADC analog watchdog (AWD) number * @{ */ #define ADC_ANALOGWATCHDOG_1 (LL_ADC_AWD1) /*!< ADC analog watchdog number 1 */ @@ -792,24 +786,22 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @} */ -/** @defgroup ADC_analog_watchdog_mode ADC Analog Watchdog Mode +/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog (AWD) mode * @{ */ -#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< No analog watchdog selected */ -#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to a - regular group, single channel */ -#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< Analog watchdog applied to - regular group, all channels */ +#define ADC_ANALOGWATCHDOG_NONE (0x00000000UL) /*!< ADC AWD not selected */ +#define ADC_ANALOGWATCHDOG_SINGLE_REG (ADC_CFGR1_AWD1SGL | ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to a regular + group single channel */ +#define ADC_ANALOGWATCHDOG_ALL_REG (ADC_CFGR1_AWD1EN) /*!< ADC AWD applied to regular + group all channels */ /** * @} */ /** @defgroup ADC_HAL_EC_OVS_RATIO Oversampling - Ratio - * @{ - */ -/** * @note The oversampling ratio is the number of ADC conversions performed, sum of these conversions data is computed * to result as the ADC oversampling conversion data (before potential shift) + * @{ */ #define ADC_OVERSAMPLING_RATIO_2 (LL_ADC_OVS_RATIO_2) /*!< ADC oversampling ratio 2 */ #define ADC_OVERSAMPLING_RATIO_4 (LL_ADC_OVS_RATIO_4) /*!< ADC oversampling ratio 4 */ @@ -824,21 +816,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /** @defgroup ADC_HAL_EC_OVS_SHIFT Oversampling - Data shift - * @{ - */ -/** * @note The sum of the ADC conversions data is divided by "Rightbitshift" number to result as the ADC oversampling - * conversion data) + * conversion data + * @{ */ #define ADC_RIGHTBITSHIFT_NONE (LL_ADC_OVS_SHIFT_NONE) /*!< ADC oversampling no shift */ -#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 ranks */ -#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 ranks */ -#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 ranks */ -#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 ranks */ -#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 ranks */ -#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 ranks */ -#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 ranks */ -#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 ranks */ +#define ADC_RIGHTBITSHIFT_1 (LL_ADC_OVS_SHIFT_RIGHT_1) /*!< ADC oversampling right shift of 1 rank */ +#define ADC_RIGHTBITSHIFT_2 (LL_ADC_OVS_SHIFT_RIGHT_2) /*!< ADC oversampling right shift of 2 rank */ +#define ADC_RIGHTBITSHIFT_3 (LL_ADC_OVS_SHIFT_RIGHT_3) /*!< ADC oversampling right shift of 3 rank */ +#define ADC_RIGHTBITSHIFT_4 (LL_ADC_OVS_SHIFT_RIGHT_4) /*!< ADC oversampling right shift of 4 rank */ +#define ADC_RIGHTBITSHIFT_5 (LL_ADC_OVS_SHIFT_RIGHT_5) /*!< ADC oversampling right shift of 5 rank */ +#define ADC_RIGHTBITSHIFT_6 (LL_ADC_OVS_SHIFT_RIGHT_6) /*!< ADC oversampling right shift of 6 rank */ +#define ADC_RIGHTBITSHIFT_7 (LL_ADC_OVS_SHIFT_RIGHT_7) /*!< ADC oversampling right shift of 7 rank */ +#define ADC_RIGHTBITSHIFT_8 (LL_ADC_OVS_SHIFT_RIGHT_8) /*!< ADC oversampling right shift of 8 rank */ /** * @} */ @@ -847,24 +837,19 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to * @{ */ #define ADC_TRIGGEREDMODE_SINGLE_TRIGGER (LL_ADC_OVS_REG_CONT) /*!< ADC oversampling discontinuous mode: - continuous mode (all conversions of - OVS ratio are done from 1 trigger) */ + continuous mode (all conversions of OVS ratio are done from 1 trigger) */ #define ADC_TRIGGEREDMODE_MULTI_TRIGGER (LL_ADC_OVS_REG_DISCONT) /*!< ADC oversampling discontinuous mode: - discontinuous mode (each conversion of - OVS ratio needs a trigger) */ + discontinuous mode (each conversion of OVS ratio needs a trigger) */ /** * @} */ /** @defgroup ADC_HAL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode - * @{ - */ - -/** * @note ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion * start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion * start trigger event). * Duration value: Refer to device datasheet, parameter "tIdle". + * @{ */ #define ADC_TRIGGER_FREQ_HIGH (LL_ADC_TRIGGER_FREQ_HIGH) /*!< Trigger frequency mode set to high frequency. */ #define ADC_TRIGGER_FREQ_LOW (LL_ADC_TRIGGER_FREQ_LOW) /*!< Trigger frequency mode set to low frequency. */ @@ -873,11 +858,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ /** @defgroup ADC_Event_type ADC Event type - * @{ - */ -/** * @note Analog watchdog 1 is available on all stm32 series * Analog watchdog 2 and 3 are not available on all series + * @{ */ #define ADC_EOSMP_EVENT (ADC_FLAG_EOSMP) /*!< ADC End of Sampling event */ #define ADC_AWD1_EVENT (ADC_FLAG_AWD1) /*!< ADC Analog watchdog 1 event (main analog watchdog) */ @@ -895,13 +878,15 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to */ #define ADC_IT_RDY ADC_IER_ADRDYIE /*!< ADC Ready interrupt source */ #define ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC channel configuration ready interrupt source */ -#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< End of sampling interrupt source */ -#define ADC_IT_EOC ADC_IER_EOCIE /*!< End of regular conversion interrupt source */ -#define ADC_IT_EOS ADC_IER_EOSIE /*!< End of regular sequence of conversions interrupt source */ -#define ADC_IT_OVR ADC_IER_OVRIE /*!< overrun interrupt source */ -#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< Analog watchdog 1 interrupt source (main analog watchdog) */ -#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< Analog watchdog 2 interrupt source (additional analog watchdog) */ -#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< Analog watchdog 3 interrupt source (additional analog watchdog) */ +#define ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC End of sampling interrupt source */ +#define ADC_IT_EOC ADC_IER_EOCIE /*!< ADC End of regular conversion interrupt source */ +#define ADC_IT_EOS ADC_IER_EOSIE /*!< ADC End of regular sequence of conversions interrupt source */ +#define ADC_IT_OVR ADC_IER_OVRIE /*!< ADC overrun interrupt source */ +#define ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC Analog watchdog 1 interrupt source (main analog watchdog) */ +#define ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC Analog watchdog 2 interrupt source (additional analog + watchdog) */ +#define ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC Analog watchdog 3 interrupt source (additional analog + watchdog) */ /** * @} */ @@ -915,9 +900,9 @@ typedef void (*pADC_CallbackTypeDef)(ADC_HandleTypeDef *hadc); /*!< pointer to #define ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC End of Regular Conversion flag */ #define ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC End of Regular sequence of Conversions flag */ #define ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC overrun flag */ -#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag */ -#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag */ -#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag */ +#define ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC Analog watchdog 1 flag (main analog watchdog) */ +#define ADC_FLAG_AWD2 ADC_ISR_AWD2 /*!< ADC Analog watchdog 2 flag (additional analog watchdog) */ +#define ADC_FLAG_AWD3 ADC_ISR_AWD3 /*!< ADC Analog watchdog 3 flag (additional analog watchdog) */ /** * @} */ @@ -1754,12 +1739,13 @@ __LL_ADC_CALC_TEMPERATURE((__VREFANALOG_VOLTAGE__),\ * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value - (unit: uV/DegCelsius). - * On STM32WL, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at - temperature and Vref+ defined in parameters below) (unit: mV). - * On STM32WL, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value + (unit: uV/DegCelsius). + * On STM32WL, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at + temperature and Vref+ defined in parameters below) (unit: mV). + * On STM32WL, refer to device datasheet parameter "V30" + (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) @@ -1842,7 +1828,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef *hadc, uint32_t *pDa HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef *hadc); /* ADC retrieve conversion value intended to be used with polling or interruption */ -uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetValue(const ADC_HandleTypeDef *hadc); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */ void HAL_ADC_IRQHandler(ADC_HandleTypeDef *hadc); @@ -1859,8 +1845,9 @@ void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, ADC_ChannelConfTypeDef *pConfig); -HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); +HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef *hadc, const ADC_ChannelConfTypeDef *pConfig); +HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, + const ADC_AnalogWDGConfTypeDef *pAnalogWDGConfig); /** * @} @@ -1870,8 +1857,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef *hadc, ADC_Ana /** @addtogroup ADC_Exported_Functions_Group4 * @{ */ -uint32_t HAL_ADC_GetState(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetState(const ADC_HandleTypeDef *hadc); +uint32_t HAL_ADC_GetError(const ADC_HandleTypeDef *hadc); /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h index 26cc974f60..b9a5e9acc1 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_adc_ex.h @@ -53,7 +53,8 @@ extern "C" { /** @defgroup ADC_HAL_EC_GROUPS ADC instance - Groups * @{ */ -#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on all STM32 devices) */ +#define ADC_REGULAR_GROUP (LL_ADC_GROUP_REGULAR) /*!< ADC group regular (available on + all STM32 devices) */ /** * @} */ @@ -143,7 +144,7 @@ extern "C" { /* ADC calibration */ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef *hadc); -uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef *hadc); +uint32_t HAL_ADCEx_Calibration_GetValue(const ADC_HandleTypeDef *hadc); HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef *hadc, uint32_t CalibrationFactor); /* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_comp.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_comp.h index d6dda4571c..6c629cd364 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_comp.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_comp.h @@ -50,7 +50,8 @@ typedef struct uint32_t WindowMode; /*!< Set window mode of a pair of comparators instances (2 consecutive instances odd and even COMP and COMP). - Note: HAL COMP driver allows to set window mode from any COMP instance of the pair of COMP instances composing window mode. + Note: HAL COMP driver allows to set window mode from any COMP + instance of the pair of COMP instances composing window mode. This parameter can be a value of @ref COMP_WindowMode */ uint32_t Mode; /*!< Set comparator operating mode to adjust power and speed. @@ -151,15 +152,25 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @} */ + /** @defgroup COMP_WindowMode COMP Window Mode * @{ */ -#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators instances pair COMP1 and COMP2 are independent */ -#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances pair COMP1 and COMP2 have their input plus connected together. The common input is COMP1 input plus (COMP2 input plus is no more accessible). */ +#define COMP_WINDOWMODE_DISABLE (0x00000000UL) /*!< Window mode disable: Comparators + instances pair COMP1 and COMP2 are + independent */ +#define COMP_WINDOWMODE_COMP1_INPUT_PLUS_COMMON (COMP_CSR_WINMODE) /*!< Window mode enable: Comparators instances + pair COMP1 and COMP2 have their input + plus connected together. + The common input is COMP1 input plus + (COMP2 input plus is no more accessible). + */ /** * @} */ + + /** @defgroup COMP_PowerMode COMP power mode * @{ */ @@ -300,14 +311,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Disable the specified comparator. * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) +#define __HAL_COMP_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_EN) /** * @brief Lock the specified comparator configuration. @@ -318,14 +329,14 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @param __HANDLE__ COMP handle * @retval None */ -#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) +#define __HAL_COMP_LOCK(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) /** * @brief Check whether the specified comparator is locked. * @param __HANDLE__ COMP handle * @retval Value 0 if COMP instance is not locked, value 1 if COMP instance is locked */ -#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) +#define __HAL_COMP_IS_LOCKED(__HANDLE__) (READ_BIT((__HANDLE__)->Instance->CSR, COMP_CSR_LOCK) == COMP_CSR_LOCK) /** * @} @@ -334,7 +345,6 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /** @defgroup COMP_Exti_Management COMP external interrupt line management * @{ */ - /** * @brief Enable the COMP1 EXTI line rising edge trigger. * @retval None @@ -363,19 +373,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + } while(0) /** * @brief Disable the COMP1 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1); \ - } while(0) +#define __HAL_COMP_COMP1_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP1); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP1);\ + } while(0) /** * @brief Enable the COMP1 EXTI line in interrupt mode. @@ -463,19 +473,19 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer * @brief Enable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_ENABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_EnableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_EnableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + } while(0) /** * @brief Disable the COMP2 EXTI line rising & falling edge trigger. * @retval None */ -#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ - LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2); \ - } while(0) +#define __HAL_COMP_COMP2_EXTI_DISABLE_RISING_FALLING_EDGE() do { \ + LL_EXTI_DisableRisingTrig_0_31(COMP_EXTI_LINE_COMP2); \ + LL_EXTI_DisableFallingTrig_0_31(COMP_EXTI_LINE_COMP2);\ + } while(0) /** * @brief Enable the COMP2 EXTI line in interrupt mode. @@ -599,7 +609,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Note: On this STM32 series, comparator input minus parameters are */ /* the same on all COMP instances. */ /* However, comparator instance kept as macro parameter for */ -/* compatibility with other STM32 families. */ +/* compatibility with other STM32 series. */ #define IS_COMP_INPUT_MINUS(__COMP_INSTANCE__, __INPUT_MINUS__) (((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_4VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_1_2VREFINT) || \ ((__INPUT_MINUS__) == COMP_INPUT_MINUS_3_4VREFINT) || \ @@ -619,7 +629,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer ((__POL__) == COMP_OUTPUTPOL_INVERTED)) #define IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__) \ - ( ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ + (((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_NONE) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM1_OC5) \ || ((__OUTPUT_BLANKING_SOURCE__) == COMP_BLANKINGSRC_TIM2_OC3) \ ) @@ -627,7 +637,7 @@ typedef void (*pCOMP_CallbackTypeDef)(COMP_HandleTypeDef *hcomp); /*!< pointer /* Note: Output blanking source common to all COMP instances */ /* Macro kept for compatibility with other STM32 series */ #define IS_COMP_BLANKINGSRC_INSTANCE(__INSTANCE__, __OUTPUT_BLANKING_SOURCE__) \ - (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) + (IS_COMP_BLANKINGSRCE(__OUTPUT_BLANKING_SOURCE__)) #define IS_COMP_TRIGGERMODE(__MODE__) (((__MODE__) == COMP_TRIGGERMODE_NONE) || \ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_conf_template.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_conf_template.h index 0f620a0514..60b45e72c5 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_conf_template.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_conf_template.h @@ -21,7 +21,7 @@ #define STM32WLxx_HAL_CONF_H #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Exported types ------------------------------------------------------------*/ @@ -190,127 +190,127 @@ * @brief Include module's header file */ #ifdef HAL_DMA_MODULE_ENABLED - #include "stm32wlxx_hal_dma.h" +#include "stm32wlxx_hal_dma.h" #endif /* HAL_DMA_MODULE_ENABLED */ #ifdef HAL_ADC_MODULE_ENABLED - #include "stm32wlxx_hal_adc.h" +#include "stm32wlxx_hal_adc.h" #endif /* HAL_ADC_MODULE_ENABLED */ #ifdef HAL_COMP_MODULE_ENABLED - #include "stm32wlxx_hal_comp.h" +#include "stm32wlxx_hal_comp.h" #endif /* HAL_COMP_MODULE_ENABLED */ #ifdef HAL_CORTEX_MODULE_ENABLED - #include "stm32wlxx_hal_cortex.h" +#include "stm32wlxx_hal_cortex.h" #endif /* HAL_CORTEX_MODULE_ENABLED */ #ifdef HAL_CRC_MODULE_ENABLED - #include "stm32wlxx_hal_crc.h" +#include "stm32wlxx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */ #ifdef HAL_CRYP_MODULE_ENABLED - #include "stm32wlxx_hal_cryp.h" +#include "stm32wlxx_hal_cryp.h" #endif /* HAL_CRYP_MODULE_ENABLED */ #ifdef HAL_DAC_MODULE_ENABLED - #include "stm32wlxx_hal_dac.h" +#include "stm32wlxx_hal_dac.h" #endif /* HAL_DAC_MODULE_ENABLED */ #ifdef HAL_EXTI_MODULE_ENABLED - #include "stm32wlxx_hal_exti.h" +#include "stm32wlxx_hal_exti.h" #endif /* HAL_EXTI_MODULE_ENABLED */ #ifdef HAL_FLASH_MODULE_ENABLED - #include "stm32wlxx_hal_flash.h" +#include "stm32wlxx_hal_flash.h" #endif /* HAL_FLASH_MODULE_ENABLED */ #ifdef HAL_GPIO_MODULE_ENABLED - #include "stm32wlxx_hal_gpio.h" +#include "stm32wlxx_hal_gpio.h" #endif /* HAL_GPIO_MODULE_ENABLED */ #ifdef HAL_GTZC_MODULE_ENABLED - #include "stm32wlxx_hal_gtzc.h" +#include "stm32wlxx_hal_gtzc.h" #endif /* HAL_GTZC_MODULE_ENABLED */ #ifdef HAL_HSEM_MODULE_ENABLED - #include "stm32wlxx_hal_hsem.h" +#include "stm32wlxx_hal_hsem.h" #endif /* HAL_HSEM_MODULE_ENABLED */ #ifdef HAL_I2C_MODULE_ENABLED - #include "stm32wlxx_hal_i2c.h" +#include "stm32wlxx_hal_i2c.h" #endif /* HAL_I2C_MODULE_ENABLED */ #ifdef HAL_I2S_MODULE_ENABLED - #include "stm32wlxx_hal_i2s.h" +#include "stm32wlxx_hal_i2s.h" #endif /* HAL_I2S_MODULE_ENABLED */ #ifdef HAL_IPCC_MODULE_ENABLED - #include "stm32wlxx_hal_ipcc.h" +#include "stm32wlxx_hal_ipcc.h" #endif /* HAL_IPCC_MODULE_ENABLED */ #ifdef HAL_IRDA_MODULE_ENABLED - #include "stm32wlxx_hal_irda.h" +#include "stm32wlxx_hal_irda.h" #endif /* HAL_IRDA_MODULE_ENABLED */ #ifdef HAL_IWDG_MODULE_ENABLED - #include "stm32wlxx_hal_iwdg.h" +#include "stm32wlxx_hal_iwdg.h" #endif /* HAL_IWDG_MODULE_ENABLED */ #ifdef HAL_LPTIM_MODULE_ENABLED - #include "stm32wlxx_hal_lptim.h" +#include "stm32wlxx_hal_lptim.h" #endif /* HAL_LPTIM_MODULE_ENABLED */ #ifdef HAL_PKA_MODULE_ENABLED - #include "stm32wlxx_hal_pka.h" +#include "stm32wlxx_hal_pka.h" #endif /* HAL_PKA_MODULE_ENABLED */ #ifdef HAL_PWR_MODULE_ENABLED - #include "stm32wlxx_hal_pwr.h" +#include "stm32wlxx_hal_pwr.h" #endif /* HAL_PWR_MODULE_ENABLED */ #ifdef HAL_RCC_MODULE_ENABLED - #include "stm32wlxx_hal_rcc.h" +#include "stm32wlxx_hal_rcc.h" #endif /* HAL_RCC_MODULE_ENABLED */ #ifdef HAL_RNG_MODULE_ENABLED - #include "stm32wlxx_hal_rng.h" +#include "stm32wlxx_hal_rng.h" #endif /* HAL_RNG_MODULE_ENABLED */ #ifdef HAL_RTC_MODULE_ENABLED - #include "stm32wlxx_hal_rtc.h" +#include "stm32wlxx_hal_rtc.h" #endif /* HAL_RTC_MODULE_ENABLED */ #ifdef HAL_SMARTCARD_MODULE_ENABLED - #include "stm32wlxx_hal_smartcard.h" +#include "stm32wlxx_hal_smartcard.h" #endif /* HAL_SMARTCARD_MODULE_ENABLED */ #ifdef HAL_SMBUS_MODULE_ENABLED - #include "stm32wlxx_hal_smbus.h" +#include "stm32wlxx_hal_smbus.h" #endif /* HAL_SMBUS_MODULE_ENABLED */ #ifdef HAL_SPI_MODULE_ENABLED - #include "stm32wlxx_hal_spi.h" +#include "stm32wlxx_hal_spi.h" #endif /* HAL_SPI_MODULE_ENABLED */ #ifdef HAL_SUBGHZ_MODULE_ENABLED - #include "stm32wlxx_hal_subghz.h" +#include "stm32wlxx_hal_subghz.h" #endif /* HAL_SUBGHZ_MODULE_ENABLED */ #ifdef HAL_TIM_MODULE_ENABLED - #include "stm32wlxx_hal_tim.h" +#include "stm32wlxx_hal_tim.h" #endif /* HAL_TIM_MODULE_ENABLED */ #ifdef HAL_UART_MODULE_ENABLED - #include "stm32wlxx_hal_uart.h" +#include "stm32wlxx_hal_uart.h" #endif /* HAL_UART_MODULE_ENABLED */ #ifdef HAL_USART_MODULE_ENABLED - #include "stm32wlxx_hal_usart.h" +#include "stm32wlxx_hal_usart.h" #endif /* HAL_USART_MODULE_ENABLED */ #ifdef HAL_WWDG_MODULE_ENABLED - #include "stm32wlxx_hal_wwdg.h" +#include "stm32wlxx_hal_wwdg.h" #endif /* HAL_WWDG_MODULE_ENABLED */ /* Exported macro ------------------------------------------------------------*/ @@ -323,11 +323,11 @@ * If expr is true, it returns no value. * @retval None */ - #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +#define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) /* Exported functions ------------------------------------------------------- */ - void assert_failed(uint8_t* file, uint32_t line); +void assert_failed(uint8_t *file, uint32_t line); #else - #define assert_param(expr) ((void)0U) +#define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */ #ifdef __cplusplus diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h index 0402add0e3..8dacda67e9 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cortex.h @@ -58,8 +58,12 @@ typedef struct This parameter can be a value of @ref CORTEX_MPU_Region_Size */ uint8_t SubRegionDisable; /*!< Specifies the number of the subregion protection to disable. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */ +#ifdef CORE_CM0PLUS +#else uint8_t TypeExtField; /*!< Specifies the TEX field level. This parameter can be a value of @ref CORTEX_MPU_TEX_Levels */ +#endif /* CORE_CM0PLUS */ + uint8_t AccessPermission; /*!< Specifies the region access permission type. This parameter can be a value of @ref CORTEX_MPU_Region_Permission_Attributes */ uint8_t DisableExec; /*!< Specifies the instruction access status. @@ -175,9 +179,12 @@ typedef struct /** @defgroup CORTEX_MPU_TEX_Levels CORTEX MPU TEX Levels * @{ */ +#if defined(CORE_CM0PLUS) +#else #define MPU_TEX_LEVEL0 ((uint8_t)0x00) #define MPU_TEX_LEVEL1 ((uint8_t)0x01) #define MPU_TEX_LEVEL2 ((uint8_t)0x02) +#endif /* CORE_CM0PLUS */ /** * @} @@ -191,7 +198,7 @@ typedef struct #define MPU_REGION_SIZE_32B ((uint8_t)0x04) #define MPU_REGION_SIZE_64B ((uint8_t)0x05) #define MPU_REGION_SIZE_128B ((uint8_t)0x06) -#endif +#endif /* CORE_CM0PLUS */ #define MPU_REGION_SIZE_256B ((uint8_t)0x07) #define MPU_REGION_SIZE_512B ((uint8_t)0x08) #define MPU_REGION_SIZE_1KB ((uint8_t)0x09) @@ -362,9 +369,12 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); #define IS_MPU_ACCESS_BUFFERABLE(STATE) (((STATE) == MPU_ACCESS_BUFFERABLE) || \ ((STATE) == MPU_ACCESS_NOT_BUFFERABLE)) +#if defined(CORE_CM0PLUS) +#else #define IS_MPU_TEX_LEVEL(TYPE) (((TYPE) == MPU_TEX_LEVEL0) || \ ((TYPE) == MPU_TEX_LEVEL1) || \ ((TYPE) == MPU_TEX_LEVEL2)) +#endif /* CORE_CM0PLUS */ #define IS_MPU_REGION_PERMISSION_ATTRIBUTE(TYPE) (((TYPE) == MPU_REGION_NO_ACCESS) || \ ((TYPE) == MPU_REGION_PRIV_RW) || \ @@ -437,7 +447,7 @@ void HAL_MPU_ConfigRegion(MPU_Region_InitTypeDef *MPU_Init); ((SIZE) == MPU_REGION_SIZE_1GB) || \ ((SIZE) == MPU_REGION_SIZE_2GB) || \ ((SIZE) == MPU_REGION_SIZE_4GB)) -#endif +#endif /* CORE_CM0PLUS */ #define IS_MPU_SUB_REGION_DISABLE(SUBREGION) ((SUBREGION) < (uint16_t)0x00FFU) #endif /* __MPU_PRESENT */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_crc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_crc.h index 7c78592619..2cced5d561 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_crc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_crc.h @@ -318,7 +318,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t /** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc); +HAL_CRC_StateTypeDef HAL_CRC_GetState(const CRC_HandleTypeDef *hcrc); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp.h index b1ee0369d6..f7b4f6c440 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp.h @@ -53,7 +53,8 @@ typedef struct uint32_t DataType; /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string. This parameter can be a value of @ref CRYP_Data_Type */ uint32_t KeySize; /*!< Used only in AES mode : 128, 192 or 256 bit key length in CRYP1. - 128 or 256 bit key length in TinyAES This parameter can be a value of @ref CRYP_Key_Size */ + 128 or 256 bit key length in TinyAES + This parameter can be a value of @ref CRYP_Key_Size */ uint32_t *pKey; /*!< The key used for encryption/decryption */ uint32_t *pInitVect; /*!< The initialization vector used also as initialization counter in CTR mode */ @@ -96,7 +97,7 @@ typedef enum { HAL_CRYP_SUSPEND_NONE = 0x00U, /*!< CRYP processing suspension not requested */ HAL_CRYP_SUSPEND = 0x01U /*!< CRYP processing suspension requested */ -}HAL_SuspendTypeDef; +} HAL_SuspendTypeDef; #endif /* USE_HAL_CRYP_SUSPEND_RESUME */ /** @@ -431,7 +432,7 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @arg CRYP_FLAG_OFNE: Output FIFO is not empty * @arg CRYP_FLAG_OFFU: Output FIFO is full * @arg CRYP_FLAG_OUTRIS: Input FIFO service raw interrupt is pending - * @retval The state of __FLAG__ (TRUE or FALSE). + * @retval The state of __FLAG__ (TRUE or FALSE). */ #define CRYP_FLAG_MASK 0x0000001FU @@ -458,7 +459,8 @@ typedef void (*pCRYP_CallbackTypeDef)(CRYP_HandleTypeDef *hcryp); /*!< point * @retval State of interruption (TRUE or FALSE). */ -#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__)) +#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR &\ + (__INTERRUPT__)) == (__INTERRUPT__)) /** @brief Check whether the specified CRYP interrupt is set or not. * @param __HANDLE__ specifies the CRYP handle. @@ -527,7 +529,8 @@ void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp); HAL_StatusTypeDef HAL_CRYP_SetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_CRYP_GetConfig(CRYP_HandleTypeDef *hcryp, CRYP_ConfigTypeDef *pConf); #if (USE_HAL_CRYP_REGISTER_CALLBACKS == 1U) -HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, pCRYP_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_CRYP_RegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID, + pCRYP_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_CRYP_UnRegisterCallback(CRYP_HandleTypeDef *hcryp, HAL_CRYP_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_CRYP_REGISTER_CALLBACKS */ #if (USE_HAL_CRYP_SUSPEND_RESUME == 1U) @@ -547,8 +550,10 @@ HAL_StatusTypeDef HAL_CRYP_RestoreContext(CRYP_HandleTypeDef *hcryp, CRYP_Contex */ /* encryption/decryption ***********************************/ -HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Encrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYP_Decrypt(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output, + uint32_t Timeout); HAL_StatusTypeDef HAL_CRYP_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); HAL_StatusTypeDef HAL_CRYP_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint32_t *Input, uint16_t Size, uint32_t *Output); @@ -607,11 +612,11 @@ uint32_t HAL_CRYP_GetError(CRYP_HandleTypeDef *hcryp); ((CONFIG) == CRYP_IVCONFIG_ONCE)) #define IS_CRYP_BUFFERSIZE(ALGO, DATAWIDTH, SIZE) \ - (((((ALGO) == CRYP_AES_CTR)) && \ - ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ - (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ - (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ - ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) + (((((ALGO) == CRYP_AES_CTR)) && \ + ((((DATAWIDTH) == CRYP_DATAWIDTHUNIT_WORD) && (((SIZE) % 4U) == 0U)) || \ + (((DATAWIDTH) == CRYP_DATAWIDTHUNIT_BYTE) && (((SIZE) % 16U) == 0U)))) || \ + (((ALGO) == CRYP_AES_ECB) || ((ALGO) == CRYP_AES_CBC) || \ + ((ALGO)== CRYP_AES_GCM_GMAC) || ((ALGO) == CRYP_AES_CCM))) /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp_ex.h index 3e8e779d87..202b3aa53f 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_cryp_ex.h @@ -73,8 +73,8 @@ extern "C" { */ /** - * @} - */ + * @} + */ /* Private functions ---------------------------------------------------------*/ /** @defgroup CRYPEx_Private_Functions CRYPEx Private Functions @@ -93,8 +93,8 @@ extern "C" { /** @addtogroup CRYPEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); -HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESGCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); +HAL_StatusTypeDef HAL_CRYPEx_AESCCM_GenerateAuthTAG(CRYP_HandleTypeDef *hcryp, const uint32_t *AuthTag, uint32_t Timeout); /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dac.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dac.h index 908ef5e9cd..5fae3f5876 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dac.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dac.h @@ -275,20 +275,6 @@ typedef void (*pDAC_CallbackTypeDef)(DAC_HandleTypeDef *hdac); * @} */ -/* Delay for DAC channel voltage settling time from DAC channel startup */ -/* (transition from disable to enable). */ -/* Note: DAC channel startup time depends on board application environment: */ -/* impedance connected to DAC channel output. */ -/* The delay below is specified under conditions: */ -/* - voltage maximum transition (lowest to highest value) */ -/* - until voltage reaches final value +-1LSB */ -/* - DAC channel output buffer enabled */ -/* - load impedance of 5kOhm (min), 50pF (max) */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tWAKEUP"). */ -/* Unit: us */ -#define DAC_DELAY_STARTUP_US (8UL) /*!< Delay for DAC channel voltage settling time from DAC channel startup (transition from disable to enable) */ - /* Exported macro ------------------------------------------------------------*/ /** @defgroup DAC_Exported_Macros DAC Exported Macros diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h index a25b9678ac..5d09387066 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_def.h @@ -22,7 +22,7 @@ #define __STM32WLxx_HAL_DEF #ifdef __cplusplus - extern "C" { +extern "C" { #endif /* Includes ------------------------------------------------------------------*/ @@ -54,7 +54,9 @@ typedef enum /* Exported macros -----------------------------------------------------------*/ +#if !defined(UNUSED) #define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */ +#endif /* UNUSED */ #define HAL_MAX_DELAY 0xFFFFFFFFU @@ -62,10 +64,10 @@ typedef enum #define HAL_IS_BIT_CLR(REG, BIT) (((REG) & (BIT)) == 0U) #define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD__, __DMA_HANDLE__) \ - do{ \ - (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ - (__DMA_HANDLE__).Parent = (__HANDLE__); \ - } while(0) + do{ \ + (__HANDLE__)->__PPP_DMA_FIELD__ = &(__DMA_HANDLE__); \ + (__DMA_HANDLE__).Parent = (__HANDLE__); \ + } while(0) /** @brief Reset the Handle's State field. * @param __HANDLE__ specifies the Peripheral Handle. @@ -85,71 +87,71 @@ typedef enum #define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0) #if (USE_RTOS == 1) - /* Reserved for future use */ - #error " USE_RTOS should be 0 in the current HAL release " +/* Reserved for future use */ +#error " USE_RTOS should be 0 in the current HAL release " #else - #define __HAL_LOCK(__HANDLE__) \ - do{ \ - if((__HANDLE__)->Lock == HAL_LOCKED) \ - { \ - return HAL_BUSY; \ - } \ - else \ - { \ - (__HANDLE__)->Lock = HAL_LOCKED; \ - } \ - }while (0) - - #define __HAL_UNLOCK(__HANDLE__) \ - do{ \ - (__HANDLE__)->Lock = HAL_UNLOCKED; \ - }while (0) +#define __HAL_LOCK(__HANDLE__) \ + do { \ + if ((__HANDLE__)->Lock == HAL_LOCKED) \ + { \ + return HAL_BUSY; \ + } \ + else \ + { \ + (__HANDLE__)->Lock = HAL_LOCKED; \ + } \ + } while (0) + +#define __HAL_UNLOCK(__HANDLE__) \ + do{ \ + (__HANDLE__)->Lock = HAL_UNLOCKED; \ + }while (0) #endif /* USE_RTOS */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif - #ifndef __packed - #define __packed __attribute__((packed)) - #endif +#ifndef __weak +#define __weak __attribute__((weak)) +#endif +#ifndef __packed +#define __packed __attribute__((packed)) +#endif #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __weak - #define __weak __attribute__((weak)) - #endif /* __weak */ - #ifndef __packed - #define __packed __attribute__((__packed__)) - #endif /* __packed */ +#ifndef __weak +#define __weak __attribute__((weak)) +#endif /* __weak */ +#ifndef __packed +#define __packed __attribute__((__packed__)) +#endif /* __packed */ #endif /* __GNUC__ */ /* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */ #if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) /* ARM Compiler V6 */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif #elif defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */ - #ifndef __ALIGN_END - #define __ALIGN_END __attribute__ ((aligned (4))) - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #define __ALIGN_BEGIN - #endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END __attribute__ ((aligned (4))) +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#define __ALIGN_BEGIN +#endif /* __ALIGN_BEGIN */ #else - #ifndef __ALIGN_END - #define __ALIGN_END - #endif /* __ALIGN_END */ - #ifndef __ALIGN_BEGIN - #if defined (__CC_ARM) /* ARM Compiler V5 */ - #define __ALIGN_BEGIN __align(4) - #elif defined (__ICCARM__) /* IAR Compiler */ - #define __ALIGN_BEGIN - #endif /* __CC_ARM */ - #endif /* __ALIGN_BEGIN */ +#ifndef __ALIGN_END +#define __ALIGN_END +#endif /* __ALIGN_END */ +#ifndef __ALIGN_BEGIN +#if defined (__CC_ARM) /* ARM Compiler V5 */ +#define __ALIGN_BEGIN __align(4) +#elif defined (__ICCARM__) /* IAR Compiler */ +#define __ALIGN_BEGIN +#endif /* __CC_ARM */ +#endif /* __ALIGN_BEGIN */ #endif /* __GNUC__ */ /** @@ -187,7 +189,7 @@ typedef enum /** * @brief __NOINLINE definition */ -#if defined ( __CC_ARM ) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) +#if defined (__CC_ARM) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) || defined ( __GNUC__ ) /* ARM V4/V5 and V6 & GNU Compiler ------------------------------- */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h index fc8db4c424..23171f4198 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma.h @@ -494,7 +494,7 @@ typedef struct __DMA_HandleTypeDef * @retval The state of FLAG (SET or RESET). */ #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) + (DMA2->ISR & (__FLAG__)) : (DMA1->ISR & (__FLAG__))) /** * @brief Clear the DMA Channel pending flags. @@ -509,7 +509,7 @@ typedef struct __DMA_HandleTypeDef * @retval None */ #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (((uint32_t)((__HANDLE__)->Instance) > ((uint32_t)DMA1_Channel7))? \ - (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) + (DMA2->IFCR = (__FLAG__)) : (DMA1->IFCR = (__FLAG__))) /** * @brief Enable the specified DMA Channel interrupts. @@ -582,10 +582,12 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma); */ /* IO operation functions *****************************************************/ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); -HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength); +HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, + uint32_t DataLength); HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma); -HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout); +HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, + uint32_t Timeout); void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma); HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma)); HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID); @@ -657,9 +659,11 @@ HAL_StatusTypeDef HAL_DMA_GetConfigChannelAttributes(DMA_HandleTypeDef *hdma, ui #if defined(DMA_CCR_SECM) && defined(DMA_CCR_PRIV) #if defined (CORE_CM0PLUS) -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U)) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE)\ + & (~(0x001E001EU))) == 0U) && (((ATTRIBUTE) & 0x0000001EU) != 0U)) #else -#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE) & (~(0x00100010U))) == 0U) && (((ATTRIBUTE) & 0x00000010U) != 0U)) +#define IS_DMA_ATTRIBUTES(ATTRIBUTE) ((((ATTRIBUTE)\ + & (~(0x00100010U))) == 0U) && (((ATTRIBUTE) & 0x00000010U) != 0U)) #endif /* CORE_CM0PLUS */ #endif /* DMA_SECURE_SWITCH */ /** diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h index 940de25ea1..d57575fa2f 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_dma_ex.h @@ -215,8 +215,8 @@ void HAL_DMAEx_MUX_IRQHandler(DMA_HandleTypeDef *hdma); /* Private macros ------------------------------------------------------------*/ /** @defgroup DMAEx_Private_Macros DMAEx Private Macros * @brief DMAEx private macros - * @{ - */ + * @{ + */ #define IS_DMAMUX_SYNC_SIGNAL_ID(SIGNAL_ID) (((SIGNAL_ID) == HAL_DMAMUX1_SYNC_EXTI0) || \ (((SIGNAL_ID) >= HAL_DMAMUX1_SYNC_EXTI1) && \ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h index 20cbd8df50..6efa9d3d5b 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_exti.h @@ -287,7 +287,7 @@ typedef struct /* Configuration functions ****************************************************/ HAL_StatusTypeDef HAL_EXTI_SetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); HAL_StatusTypeDef HAL_EXTI_GetConfigLine(EXTI_HandleTypeDef *hexti, EXTI_ConfigTypeDef *pExtiConfig); -HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(EXTI_HandleTypeDef *hexti); +HAL_StatusTypeDef HAL_EXTI_ClearConfigLine(const EXTI_HandleTypeDef *hexti); HAL_StatusTypeDef HAL_EXTI_RegisterCallback(EXTI_HandleTypeDef *hexti, EXTI_CallbackIDTypeDef CallbackID, void (*pPendingCbfn)(void)); HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLine); /** @@ -299,10 +299,10 @@ HAL_StatusTypeDef HAL_EXTI_GetHandle(EXTI_HandleTypeDef *hexti, uint32_t ExtiLin * @{ */ /* IO operation functions *****************************************************/ -void HAL_EXTI_IRQHandler(EXTI_HandleTypeDef *hexti); -uint32_t HAL_EXTI_GetPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_ClearPending(EXTI_HandleTypeDef *hexti, uint32_t Edge); -void HAL_EXTI_GenerateSWI(EXTI_HandleTypeDef *hexti); +void HAL_EXTI_IRQHandler(const EXTI_HandleTypeDef *hexti); +uint32_t HAL_EXTI_GetPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_ClearPending(const EXTI_HandleTypeDef *hexti, uint32_t Edge); +void HAL_EXTI_GenerateSWI(const EXTI_HandleTypeDef *hexti); /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h index 2f5023cf57..3eaa6bf170 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash.h @@ -133,8 +133,8 @@ typedef struct } FLASH_OBProgramInitTypeDef; /** -* @brief FLASH handle Structure definition -*/ + * @brief FLASH handle Structure definition + */ typedef struct { HAL_LockTypeDef Lock; /* FLASH locking object */ @@ -694,9 +694,9 @@ typedef struct */ /** @defgroup FLASH_Interrupt FLASH Interrupts Macros - * @brief macros to handle FLASH interrupts - * @{ - */ + * @brief macros to handle FLASH interrupts + * @{ + */ /** * @brief Enable the specified FLASH interrupt. @@ -906,17 +906,22 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); /* Private macros ------------------------------------------------------------*/ /** @defgroup FLASH_Private_Macros FLASH Private Macros - * @{ - */ -#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) + * @{ + */ +#define IS_FLASH_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 1UL))) -#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) +#define IS_FLASH_FAST_PROGRAM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 256UL)) && (((__VALUE__) % 256UL) == 0UL)) -#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) +#define IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= (FLASH_BASE + FLASH_SIZE - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) -#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) && ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) +#define IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__) (((__VALUE__) >= OTP_AREA_BASE) &&\ + ((__VALUE__) <= (OTP_AREA_END_ADDR + 1UL - 8UL)) && (((__VALUE__) % 8UL) == 0UL)) -#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) || IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) +#define IS_FLASH_PROGRAM_ADDRESS(__VALUE__) (IS_FLASH_PROGRAM_MAIN_MEM_ADDRESS(__VALUE__) ||\ + IS_FLASH_PROGRAM_OTP_ADDRESS(__VALUE__)) #define IS_FLASH_PAGE(__VALUE__) ((__VALUE__) < FLASH_PAGE_NB) @@ -929,10 +934,13 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); ((__VALUE__) == FLASH_TYPEPROGRAM_FAST)) #if defined(DUAL_CORE) -#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) && ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~0x7FFU) == (__VALUE__))) +#define IS_OB_SFSA_START_ADDR(__VALUE__) (((__VALUE__) >= FLASH_BASE) &&\ + ((__VALUE__) <= FLASH_END_ADDR) && (((__VALUE__) & ~0x7FFU) == (__VALUE__))) #define IS_OB_HDPSA_START_ADDR(__VALUE__) IS_OB_SFSA_START_ADDR(__VALUE__) -#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2_BASE) && ((__VALUE__) <= (SRAM2_BASE + SRAM2_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) -#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM1_BASE) && ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) +#define IS_OB_SBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM2_BASE) &&\ + ((__VALUE__) <= (SRAM2_BASE + SRAM2_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) +#define IS_OB_SNBRSA_START_ADDR(__VALUE__) (((__VALUE__) >= SRAM1_BASE) &&\ + ((__VALUE__) <= (SRAM1_BASE + SRAM1_SIZE)) && (((__VALUE__) & ~0x3FFU) == (__VALUE__))) #define IS_OB_SECURE_MODE(__VALUE__) ( (((__VALUE__) & (OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) != 0U) && \ (((__VALUE__) & ~(OB_SECURE_SYSTEM_AND_ALL_AREAS_ENABLE | OB_SECURE_SYSTEM_AND_ALL_AREAS_DISABLE)) == 0U) && \ @@ -944,15 +952,17 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); #if defined(DUAL_CORE) #define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP | \ - OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE | \ - OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS)) + OPTIONBYTE_IPCC_BUF_ADDR | OPTIONBYTE_C2_BOOT_VECT | OPTIONBYTE_SECURE_MODE | \ + OPTIONBYTE_C2_DEBUG_ACCESS | OPTIONBYTE_SUBGHZSPI_SECURE_ACCESS)) #else -#define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)) +#define IS_OPTIONBYTE(__VALUE__) ((__VALUE__) <= (OPTIONBYTE_WRP |\ + OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_PCROP)) #endif /* DUAL_CORE */ -#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) || ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) +#define IS_OB_WRPAREA(__VALUE__) (((__VALUE__) == OB_WRPAREA_BANK1_AREAA) ||\ + ((__VALUE__) == OB_WRPAREA_BANK1_AREAB)) #define IS_OB_RDP_LEVEL(__VALUE__) (((__VALUE__) == OB_RDP_LEVEL_0) ||\ ((__VALUE__) == OB_RDP_LEVEL_1) ||\ @@ -962,28 +972,34 @@ HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout); (((__VALUE__) & ~OB_USER_ALL) == 0U)) #define IS_OB_USER_CONFIG(__TYPE__, __VALUE__) ((((__TYPE__) & OB_USER_BOR_LEV) == OB_USER_BOR_LEV) \ - ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ - (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ - : ((~(__TYPE__) & (__VALUE__)) == 0U)) + ? ((((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_0) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_1) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_2) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_3) || \ + (((__VALUE__) & ~(OB_USER_ALL & ~OB_USER_BOR_LEV)) == OB_BOR_LEVEL_4)) \ + : ((~(__TYPE__) & (__VALUE__)) == 0U)) #define IS_OB_USER_BOR_LEVEL(__VALUE__) (((__VALUE__) == OB_BOR_LEVEL_0) || ((__VALUE__) == OB_BOR_LEVEL_1) || \ ((__VALUE__) == OB_BOR_LEVEL_2) || ((__VALUE__) == OB_BOR_LEVEL_3) || \ ((__VALUE__) == OB_BOR_LEVEL_4)) -#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) & ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) +#define IS_OB_PCROP_CONFIG(__VALUE__) (((__VALUE__) &\ + ~(OB_PCROP_ZONE_A | OB_PCROP_ZONE_B | OB_PCROP_RDP_ERASE)) == 0U) #if defined(DUAL_CORE) -#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) +#define IS_OB_IPCC_BUF_ADDR(__VALUE__) (IS_OB_SBRSA_START_ADDR(__VALUE__) ||\ + IS_OB_SNBRSA_START_ADDR(__VALUE__)) -#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) (IS_OB_SFSA_START_ADDR(__VALUE__) || IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) -#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) || ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) +#define IS_OB_BOOT_VECTOR_ADDR(__VALUE__) (IS_OB_SFSA_START_ADDR(__VALUE__) ||\ + IS_OB_SBRSA_START_ADDR(__VALUE__) || IS_OB_SNBRSA_START_ADDR(__VALUE__)) +#define IS_OB_BOOT_REGION(__VALUE__) (((__VALUE__) == OB_C2_BOOT_FROM_FLASH) ||\ + ((__VALUE__) == OB_C2_BOOT_FROM_SRAM)) -#define IS_OB_SUBGHZSPI_SECURE_ACCESS(__VALUE__) (((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_ENABLE) || ((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_DISABLE)) +#define IS_OB_SUBGHZSPI_SECURE_ACCESS(__VALUE__) (((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_ENABLE) ||\ + ((__VALUE__) == OB_SUBGHZSPI_SECURE_ACCESS_DISABLE)) -#define IS_OB_C2_DEBUG_MODE(__VALUE__) (((__VALUE__) == OB_C2_DEBUG_ACCESS_ENABLE) || ((__VALUE__) == OB_C2_DEBUG_ACCESS_DISABLE)) +#define IS_OB_C2_DEBUG_MODE(__VALUE__) (((__VALUE__) == OB_C2_DEBUG_ACCESS_ENABLE) ||\ + ((__VALUE__) == OB_C2_DEBUG_ACCESS_DISABLE)) #endif /* DUAL_CORE */ #define IS_FLASH_LATENCY(__VALUE__) (((__VALUE__) == FLASH_LATENCY_0) || \ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h index 166edb6ce9..06cffff278 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_flash_ex.h @@ -71,7 +71,7 @@ extern "C" { /** @addtogroup FLASHEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); +HAL_StatusTypeDef HAL_FLASHEx_Erase(const FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError); HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit); uint32_t HAL_FLASHEx_FlashEmptyCheck(void); void HAL_FLASHEx_ForceFlashEmpty(uint32_t FlashEmpty); @@ -99,9 +99,11 @@ uint32_t HAL_FLASHEx_GetPrivMode(void); /** @defgroup FLASHEx_Private_Macros FLASHEx Private Macros * @{ */ -#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) || ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) +#define IS_FLASH_EMPTY_CHECK(__VALUE__) (((__VALUE__) == FLASH_PROG_EMPTY) ||\ + ((__VALUE__) == FLASH_PROG_NOT_EMPTY)) -#define IS_FLASH_CFGPRIVMODE(__VALUE__) (((__VALUE__) == FLASH_PRIV_GRANTED) || ((__VALUE__) == FLASH_PRIV_DENIED)) +#define IS_FLASH_CFGPRIVMODE(__VALUE__) (((__VALUE__) == FLASH_PRIV_GRANTED) ||\ + ((__VALUE__) == FLASH_PRIV_DENIED)) /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h index 6a1f23ea85..5c5112f3ae 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gpio.h @@ -283,7 +283,7 @@ typedef enum */ /* Initialization and de-initialization functions *****************************/ -void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, GPIO_InitTypeDef *GPIO_Init); +void HAL_GPIO_Init(GPIO_TypeDef *GPIOx, const GPIO_InitTypeDef *GPIO_Init); void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); /** @@ -296,7 +296,7 @@ void HAL_GPIO_DeInit(GPIO_TypeDef *GPIOx, uint32_t GPIO_Pin); */ /* IO operation functions *****************************************************/ -GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); +GPIO_PinState HAL_GPIO_ReadPin(const GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); void HAL_GPIO_WritePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState); void HAL_GPIO_WriteMultipleStatePin(GPIO_TypeDef *GPIOx, uint16_t PinReset, uint16_t PinSet); void HAL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint16_t GPIO_Pin); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gtzc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gtzc.h index 9d7cd5dda5..b5258d5a8b 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gtzc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_gtzc.h @@ -217,7 +217,7 @@ HAL_StatusTypeDef HAL_GTZC_TZSC_MPCWM_GetConfigMemAttributes(uint32_t MemBaseAdd * @{ */ /* TZSC and TZSC-MPCWM Lock functions *****************************************/ -uint32_t HAL_GTZC_TZSC_GetLock(GTZC_TZSC_TypeDef *TZSCx); +uint32_t HAL_GTZC_TZSC_GetLock(const GTZC_TZSC_TypeDef *TZSCx); #if defined(CORE_CM0PLUS) void HAL_GTZC_TZSC_Lock(GTZC_TZSC_TypeDef *TZSCx); /** @@ -267,21 +267,25 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); * in case of GTZC_PERIPH_ALL usage in the two following functions: * HAL_GTZC_TZSC_ConfigPeriphAttributes and HAL_GTZC_TZSC_GetConfigPeriphAttributes */ -#define GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) ((GTZC_GET_REG_INDEX(__PERIPHERAL__) * 32U) + GTZC_GET_PERIPH_POS(__PERIPHERAL__)) +#define GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) \ + ((GTZC_GET_REG_INDEX(__PERIPHERAL__) * 32U) + GTZC_GET_PERIPH_POS(__PERIPHERAL__)) /** * @brief GTZC private macros to check function input parameters */ -#define IS_GTZC_ATTRIBUTE(__ATTRIBUTES__) (((__ATTRIBUTES__) & ~(GTZC_TZSC_ATTRIBUTE_SEC | GTZC_TZSC_ATTRIBUTE_PRIV)) == 0x00u) +#define IS_GTZC_ATTRIBUTE(__ATTRIBUTES__) \ + (((__ATTRIBUTES__) & ~(GTZC_TZSC_ATTRIBUTE_SEC | GTZC_TZSC_ATTRIBUTE_PRIV)) == 0x00u) -#define IS_GTZC_TZSC_PERIPHERAL(__PERIPHERAL__) (((__PERIPHERAL__) == GTZC_PERIPH_AES) || ((__PERIPHERAL__) == GTZC_PERIPH_RNG) || \ - ((__PERIPHERAL__) == GTZC_PERIPH_SUBGHZSPI) || ((__PERIPHERAL__) == GTZC_PERIPH_PKA) ||\ - ((__PERIPHERAL__) == GTZC_PERIPH_ALL)) +#define IS_GTZC_TZSC_PERIPHERAL(__PERIPHERAL__) \ + (((__PERIPHERAL__) == GTZC_PERIPH_AES) || ((__PERIPHERAL__) == GTZC_PERIPH_RNG) || \ + ((__PERIPHERAL__) == GTZC_PERIPH_SUBGHZSPI) || ((__PERIPHERAL__) == GTZC_PERIPH_PKA) || \ + ((__PERIPHERAL__) == GTZC_PERIPH_ALL)) -#define IS_GTZC_TZIC_PERIPHERAL(__PERIPHERAL__) (((((__PERIPHERAL__) & ~(GTZC_PERIPH_REG_Pos | GTZC_PERIPH_BITPOS_Msk)) == 0x00u) && \ - ((GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) <= GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_TZIC_MAX)))) || \ - ((__PERIPHERAL__) == GTZC_PERIPH_ALLPERIPH_Msk)) +#define IS_GTZC_TZIC_PERIPHERAL(__PERIPHERAL__) \ + (((((__PERIPHERAL__) & ~(GTZC_PERIPH_REG_Pos | GTZC_PERIPH_BITPOS_Msk)) == 0x00u) && \ + ((GTZC_GET_ARRAY_INDEX(__PERIPHERAL__) <= GTZC_GET_ARRAY_INDEX(GTZC_PERIPH_TZIC_MAX)))) || \ + ((__PERIPHERAL__) == GTZC_PERIPH_ALLPERIPH_Msk)) #define IS_GTZC_MPCWM_MEMORY_BASEADDRESS(__BASE_ADDRESS__) (((__BASE_ADDRESS__) == FLASH_BASE) || \ ((__BASE_ADDRESS__) == SRAM1_BASE) || \ @@ -295,13 +299,13 @@ void HAL_GTZC_TZIC_Callback(uint32_t PeriphId); #define IS_GTZC_MPCWM_SRAM2_AREAID(__AREAID__) ((__AREAID__) == GTZC_TZSC_MPCWM_AREAID_UNPRIV) #define IS_GTZC_MPCWM_FLASH_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_FLASH) == 0x00u) && \ - ((__LENGTH__) <= FLASH_SIZE)) + ((__LENGTH__) <= FLASH_SIZE)) #define IS_GTZC_MPCWM_SRAM1_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM1) == 0x00u) && \ - ((__LENGTH__) <= SRAM1_SIZE)) + ((__LENGTH__) <= SRAM1_SIZE)) #define IS_GTZC_MPCWM_SRAM2_LENGTH(__LENGTH__) ((((__LENGTH__) % GTZC_TZSC_MPCWM_GRANULARITY_SRAM2) == 0x00u) && \ - ((__LENGTH__) <= SRAM2_SIZE)) + ((__LENGTH__) <= SRAM2_SIZE)) /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_hsem.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_hsem.h index 2e83042401..7e2774d8b9 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_hsem.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_hsem.h @@ -57,7 +57,7 @@ extern "C" { (HSEM->C1IER |= (__SEM_MASK__)) : \ (HSEM->C2IER |= (__SEM_MASK__))) #else -#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->IER |= (__SEM_MASK__)) +#define __HAL_HSEM_ENABLE_IT(__SEM_MASK__) (HSEM->C1IER |= (__SEM_MASK__)) #endif /* DUAL_CORE */ /** * @brief Disables the specified HSEM interrupts. @@ -69,7 +69,7 @@ extern "C" { (HSEM->C1IER &= ~(__SEM_MASK__)) : \ (HSEM->C2IER &= ~(__SEM_MASK__))) #else -#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->IER &= ~(__SEM_MASK__)) +#define __HAL_HSEM_DISABLE_IT(__SEM_MASK__) (HSEM->C1IER &= ~(__SEM_MASK__)) #endif /* DUAL_CORE */ /** @@ -80,9 +80,9 @@ extern "C" { #if defined(DUAL_CORE) #define __HAL_HSEM_GET_IT(__SEM_MASK__) ((((SCB->CPUID & 0x000000F0) >> 4 )== 0x7) ? \ ((__SEM_MASK__) & HSEM->C1MISR) : \ - ((__SEM_MASK__) & HSEM->C2MISR1)) + ((__SEM_MASK__) & HSEM->C2MISR)) #else -#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->MISR) +#define __HAL_HSEM_GET_IT(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1MISR) #endif /* DUAL_CORE */ /** @@ -95,7 +95,7 @@ extern "C" { (__SEM_MASK__) & HSEM->C1ISR : \ (__SEM_MASK__) & HSEM->C2ISR) #else -#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->ISR) +#define __HAL_HSEM_GET_FLAG(__SEM_MASK__) ((__SEM_MASK__) & HSEM->C1ISR) #endif /* DUAL_CORE */ /** @@ -108,7 +108,7 @@ extern "C" { (HSEM->C1ICR |= (__SEM_MASK__)) : \ (HSEM->C2ICR |= (__SEM_MASK__))) #else -#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->ICR |= (__SEM_MASK__)) +#define __HAL_HSEM_CLEAR_FLAG(__SEM_MASK__) (HSEM->C1ICR |= (__SEM_MASK__)) #endif /* DUAL_CORE */ /** diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h index 9cf8b1a1f7..2b3176d437 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2c.h @@ -118,8 +118,6 @@ typedef enum HAL_I2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception process is ongoing */ HAL_I2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */ - HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */ - HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */ } HAL_I2C_StateTypeDef; diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2s.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2s.h index 8665b1725f..3506355ca0 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2s.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_i2s.h @@ -451,8 +451,8 @@ void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s); * @{ */ /* Peripheral Control and State functions ************************************/ -HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s); -uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s); +HAL_I2S_StateTypeDef HAL_I2S_GetState(const I2S_HandleTypeDef *hi2s); +uint32_t HAL_I2S_GetError(const I2S_HandleTypeDef *hi2s); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_irda.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_irda.h index a531b8c8fd..a344b3da5a 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_irda.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_irda.h @@ -77,7 +77,8 @@ typedef struct /** * @brief HAL IRDA State definition - * @note HAL IRDA State value is a combination of 2 different substates: gState and RxState (see @ref IRDA_State_Definition). + * @note HAL IRDA State value is a combination of 2 different substates: + * gState and RxState (see @ref IRDA_State_Definition). * - gState contains IRDA state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -247,7 +248,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer Value is allowed for RxState only */ #define HAL_IRDA_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ + Value is result of combination (Or) between + gState and RxState values */ #define HAL_IRDA_STATE_TIMEOUT 0x000000A0U /*!< Timeout state Value is allowed for gState only */ #define HAL_IRDA_STATE_ERROR 0x000000E0U /*!< Error @@ -259,15 +261,15 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer /** @defgroup IRDA_Error_Definition IRDA Error Code Definition * @{ */ -#define HAL_IRDA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_IRDA_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_IRDA_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_IRDA_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_IRDA_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_IRDA_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_IRDA_ERROR_BUSY ((uint32_t)0x00000020U) /*!< Busy Error */ +#define HAL_IRDA_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_IRDA_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_IRDA_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_IRDA_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_IRDA_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_IRDA_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_IRDA_ERROR_BUSY (0x00000020U) /*!< Busy Error */ #if (USE_HAL_IRDA_REGISTER_CALLBACKS == 1) -#define HAL_IRDA_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_IRDA_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_IRDA_REGISTER_CALLBACKS */ /** * @} @@ -570,9 +572,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) +#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))):\ + ((__HANDLE__)->Instance->CR3 |= (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Disable the specified IRDA interrupt. * @param __HANDLE__ specifies the IRDA Handle. @@ -586,10 +593,14 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & IRDA_IT_MASK)))) - +#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 1U)? \ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 2U)? \ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << \ + ((__INTERRUPT__) & IRDA_IT_MASK)))) /** @brief Check whether the specified IRDA interrupt has occurred or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -605,8 +616,8 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>> IRDA_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT(__HANDLE__, __INTERRUPT__) \ + ((((__HANDLE__)->Instance->ISR& (0x01U << (((__INTERRUPT__) & IRDA_ISR_MASK)>>IRDA_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified IRDA interrupt source is enabled or not. * @param __HANDLE__ specifies the IRDA Handle. @@ -620,9 +631,10 @@ typedef void (*pIRDA_CallbackTypeDef)(IRDA_HandleTypeDef *hirda); /*!< pointer * @arg @ref IRDA_IT_PE Parity Error interrupt * @retval The new state of __IT__ (SET or RESET). */ -#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & IRDA_CR_MASK) >> IRDA_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \ + ((((((((__INTERRUPT__) & IRDA_CR_MASK) >>IRDA_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 :(((((__INTERRUPT__) \ + & IRDA_CR_MASK) >> IRDA_CR_POS)== 0x02U)? (__HANDLE__)->Instance->CR2 :(__HANDLE__)->Instance->CR3)) \ + & (0x01U <<(((uint16_t)(__INTERRUPT__)) & IRDA_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the IRDA Handle. diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_lptim.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_lptim.h index 0bc2b78acc..7b291e4403 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_lptim.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_lptim.h @@ -453,6 +453,7 @@ typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef *hlptim); /*!< poin * @brief Write the passed parameter in the Autoreload register. * @param __HANDLE__ LPTIM handle * @param __VALUE__ Autoreload value + * This parameter must be a value between Min_Data = 0x0001 and Max_Data = 0xFFFF. * @retval None * @note The ARR register can only be modified when the LPTIM instance is enabled. */ @@ -718,9 +719,9 @@ void HAL_LPTIM_RepCounterWriteCallback(LPTIM_HandleTypeDef *hlptim); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID, +HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback); -HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_LPTIM_CallbackIDTypeDef CallbackID); +HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */ /** * @} @@ -731,7 +732,7 @@ HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *lphtim, HAL_ * @{ */ /* Peripheral State functions ************************************************/ -HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); +HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(const LPTIM_HandleTypeDef *hlptim); /** * @} */ @@ -824,9 +825,6 @@ HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim); #define IS_LPTIM_COUNTER_SOURCE(__SOURCE__) (((__SOURCE__) == LPTIM_COUNTERSOURCE_INTERNAL) || \ ((__SOURCE__) == LPTIM_COUNTERSOURCE_EXTERNAL)) -#define IS_LPTIM_AUTORELOAD(__AUTORELOAD__) ((0x00000001UL <= (__AUTORELOAD__)) &&\ - ((__AUTORELOAD__) <= 0x0000FFFFUL)) - #define IS_LPTIM_COMPARE(__COMPARE__) ((__COMPARE__) <= 0x0000FFFFUL) #define IS_LPTIM_PERIOD(__PERIOD__) ((0x00000001UL <= (__PERIOD__)) &&\ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pka.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pka.h index e3eec34dd9..3e65398aa3 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pka.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pka.h @@ -541,8 +541,8 @@ void HAL_PKA_IRQHandler(PKA_HandleTypeDef *hpka); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_PKA_StateTypeDef HAL_PKA_GetState(PKA_HandleTypeDef *hpka); -uint32_t HAL_PKA_GetError(PKA_HandleTypeDef *hpka); +HAL_PKA_StateTypeDef HAL_PKA_GetState(const PKA_HandleTypeDef *hpka); +uint32_t HAL_PKA_GetError(const PKA_HandleTypeDef *hpka); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h index a69df4ea73..4a82fff57f 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr.h @@ -110,7 +110,7 @@ typedef struct #define PWR_LOWPOWERMODE_STOP2 (PWR_CR1_LPMS_1) /*!< Stop 2: Stop mode with low power regulator and VDD12I interruptible digital core domain supply OFF (less peripherals activated than low power mode stop 1 to reduce power consumption)*/ #define PWR_LOWPOWERMODE_STANDBY (PWR_CR1_LPMS_0 | PWR_CR1_LPMS_1) /*!< Standby mode */ #define PWR_LOWPOWERMODE_SHUTDOWN (PWR_CR1_LPMS_2 | PWR_CR1_LPMS_1 | PWR_CR1_LPMS_0) /*!< Shutdown mode */ -#endif +#endif /* CORE_CM0PLUS */ /** * @} */ @@ -298,22 +298,22 @@ typedef struct * * @retval The new state of __FLAG__ (TRUE or FALSE). */ -#endif +#endif /* DUAL_CORE */ #define __HAL_PWR_GET_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR1) ? \ ( \ - PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ + PWR->SR1 & (1UL << ((__FLAG__) & 31UL)) \ ) \ : \ ( \ - (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ - ( \ - PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ - ) \ - : \ - ( \ - PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ - ) \ - ) \ + (((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_SR2) ? \ + ( \ + PWR->SR2 & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + : \ + ( \ + PWR->EXTSCR & (1UL << ((__FLAG__) & 31UL)) \ + ) \ + ) \ ) #if defined(DUAL_CORE) @@ -371,17 +371,17 @@ typedef struct * * @retval None */ -#endif -#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ - ( \ - PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ - ) \ - : \ - ( \ - (((__FLAG__)) == PWR_FLAG_WU) ? \ - (PWR->SCR = PWR_SCR_CWUF) : \ - (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ - ) \ +#endif /* DUAL_CORE */ +#define __HAL_PWR_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & PWR_FLAG_REG_MASK) == PWR_FLAG_REG_EXTSCR) ? \ + ( \ + PWR->EXTSCR = (1UL << (((__FLAG__) & PWR_FLAG_EXTSCR_CLR_MASK) >> PWR_FLAG_EXTSCR_CLR_POS)) \ + ) \ + : \ + ( \ + (((__FLAG__)) == PWR_FLAG_WU) ? \ + (PWR->SCR = PWR_SCR_CWUF) : \ + (PWR->SCR = (1UL << ((__FLAG__) & 31UL))) \ + ) \ ) /** @@ -392,7 +392,7 @@ typedef struct #define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD) #else #define __HAL_PWR_PVD_EXTI_ENABLE_IT() LL_EXTI_EnableIT_0_31(PWR_EXTI_LINE_PVD) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Disable the PVD Extended Interrupt line. @@ -402,7 +402,7 @@ typedef struct #define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD) #else #define __HAL_PWR_PVD_EXTI_DISABLE_IT() LL_EXTI_DisableIT_0_31(PWR_EXTI_LINE_PVD) -#endif +#endif /* CORE_CM0PLUS */ /* Note: On STM32WL series, power PVD event is not available on EXTI lines */ /* (only interruption is available through EXTI line 16). */ @@ -533,7 +533,7 @@ void HAL_PWR_DisableBkUpAccess(void); * @{ */ /* Peripheral Control functions ************************************************/ -HAL_StatusTypeDef HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); +HAL_StatusTypeDef HAL_PWR_ConfigPVD(const PWR_PVDTypeDef *sConfigPVD); void HAL_PWR_EnablePVD(void); void HAL_PWR_DisablePVD(void); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h index 331b20c863..ce9821e0f2 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_pwr_ex.h @@ -79,7 +79,7 @@ typedef struct #define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos | PWR_EXTSCR_C2CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ #else #define PWR_FLAG_EXTSCR_CLR_MASK ((PWR_EXTSCR_C1CSSF_Pos) << PWR_FLAG_EXTSCR_CLR_POS) /* Bitfield for register PWR_EXTSCR clearable bits positions: mask of bitfield in flag literals */ -#endif +#endif /* DUAL_CORE */ /** * @} */ @@ -304,17 +304,17 @@ typedef struct #define PWR_FLAG_C2SB (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2SBF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Standby flag for CPU2 */ #define PWR_FLAG_C2STOP2 (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOP2F_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 2 flag for CPU2 */ #define PWR_FLAG_C2STOP (PWR_FLAG_REG_EXTSCR | PWR_EXTSCR_C2STOPF_Pos | (PWR_EXTSCR_C2CSSF_Pos << PWR_FLAG_EXTSCR_CLR_POS)) /*!< System Stop 0 or Stop 1 flag for CPU2 */ -#endif +#endif /* DUAL_CORE */ #define PWR_FLAG_LPMODES (PWR_FLAG_SB) /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU1, used when clearing flags */ #if defined(DUAL_CORE) #define PWR_FLAG_C2LPMODES (PWR_FLAG_C2SB) /*!< System flag encompassing all low-powers flags (Stop0, 1, 2 and Standby) for CPU2, used when clearing flags */ -#endif +#endif /* DUAL_CORE */ #define PWR_FLAG_C1DEEPSLEEP (PWR_EXTSCR_C1DS_Pos | PWR_FLAG_REG_EXTSCR) /*!< CPU1 DeepSleep Flag */ #if defined(DUAL_CORE) #define PWR_FLAG_C2DEEPSLEEP (PWR_EXTSCR_C2DS_Pos | PWR_FLAG_REG_EXTSCR) /*!< CPU2 DeepSleep Flag */ -#endif +#endif /* DUAL_CORE */ /** * @} */ @@ -325,7 +325,7 @@ typedef struct #define PWR_CORE_CPU1 (0x00000000UL) #if defined(DUAL_CORE) #define PWR_CORE_CPU2 (0x00000001UL) -#endif +#endif /* DUAL_CORE */ /** * @} */ @@ -344,8 +344,8 @@ typedef struct /* Exported macros -----------------------------------------------------------*/ /** @defgroup PWREx_Exported_Macros PWR Extended Exported Macros - * @{ - */ + * @{ + */ /** * @brief Enable the PVM3 Extended Interrupt line. @@ -355,7 +355,7 @@ typedef struct #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_C2_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) #else #define __HAL_PWR_PVM3_EXTI_ENABLE_IT() LL_EXTI_EnableIT_32_63(PWR_EXTI_LINE_PVM3) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Disable the PVM3 Extended Interrupt line. @@ -365,7 +365,7 @@ typedef struct #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_C2_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) #else #define __HAL_PWR_PVM3_EXTI_DISABLE_IT() LL_EXTI_DisableIT_32_63(PWR_EXTI_LINE_PVM3) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Enable the PVM3 Event line. @@ -375,7 +375,7 @@ typedef struct #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_C2_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) #else #define __HAL_PWR_PVM3_EXTI_ENABLE_EVENT() LL_EXTI_EnableEvent_32_63(PWR_EXTI_LINE_PVM3) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Disable the PVM3 Event line. @@ -385,7 +385,7 @@ typedef struct #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_C2_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) #else #define __HAL_PWR_PVM3_EXTI_DISABLE_EVENT() LL_EXTI_DisableEvent_32_63(PWR_EXTI_LINE_PVM3) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Enable the PVM3 Extended Interrupt Rising Trigger. @@ -541,11 +541,11 @@ typedef struct #define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1) || ((__CPU__) == PWR_CORE_CPU2)) #else #define IS_PWR_CORE(__CPU__) (((__CPU__) == PWR_CORE_CPU1)) -#endif +#endif /* DUAL_CORE */ #if defined(DUAL_CORE) #define IS_PWR_CORE_HOLD_RELEASE(__CPU__) ((__CPU__) == PWR_CORE_CPU2) -#endif +#endif /* DUAL_CORE */ /** * @} @@ -585,7 +585,7 @@ void HAL_PWREx_ReleaseCore(uint32_t CPU); void HAL_PWREx_EnableWakeUp_ILAC(void); void HAL_PWREx_DisableWakeUp_ILAC(void); uint32_t HAL_PWREx_IsEnabledWakeUp_ILAC(void); -#endif +#endif /* CORE_CM0PLUS */ HAL_StatusTypeDef HAL_PWREx_EnableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); HAL_StatusTypeDef HAL_PWREx_DisableGPIOPullUp(uint32_t GPIO, uint32_t GPIONumber); @@ -608,7 +608,7 @@ void HAL_PWREx_DisableBORPVD_ULP(void); void HAL_PWREx_EnablePVM3(void); void HAL_PWREx_DisablePVM3(void); -HAL_StatusTypeDef HAL_PWREx_ConfigPVM(PWR_PVMTypeDef *sConfigPVM); +HAL_StatusTypeDef HAL_PWREx_ConfigPVM(const PWR_PVMTypeDef *sConfigPVM); void HAL_PWREx_SetRadioEOL(uint32_t RadioEOL); void HAL_PWREx_SMPS_SetMode(uint32_t OperatingMode); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h index 64d9836e18..99dc4200fe 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rcc.h @@ -633,11 +633,11 @@ typedef struct */ /* @cond */ - /* 32 28 20 16 0 - -------------------------------- - | MCO | GPIO | GPIO | GPIO | - | Index | AF | Port | Pin | - -------------------------------*/ +/* 32 28 20 16 0 + -------------------------------- + | MCO | GPIO | GPIO | GPIO | + | Index | AF | Port | Pin | + -------------------------------*/ #define RCC_MCO_GPIOPORT_POS 16U #define RCC_MCO_GPIOPORT_MASK (0xFUL << RCC_MCO_GPIOPORT_POS) @@ -2005,26 +2005,38 @@ typedef struct * This parameter can be one of the following values: * @arg @ref RCC_LSE_OFF Turn OFF the LSE oscillator, LSERDY flag goes low after * 6 LSE oscillator clock cycles. - * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator. - * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock. + * @arg @ref RCC_LSE_ON_RTC_ONLY Turn ON the LSE oscillator to be used only for RTC. + * @arg @ref RCC_LSE_ON Turn ON the LSE oscillator to be used by any peripheral. + * @arg @ref RCC_LSE_BYPASS_RTC_ONLY LSE oscillator bypassed with external clock to be used only for RTC. + * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock to be used by any peripheral. * @retval None */ -#define __HAL_RCC_LSE_CONFIG(__STATE__) do { \ - if((__STATE__) == RCC_LSE_ON) \ - { \ - LL_RCC_LSE_Enable(); \ - } \ - else if((__STATE__) == RCC_LSE_BYPASS) \ - { \ - LL_RCC_LSE_EnableBypass(); \ - LL_RCC_LSE_Enable(); \ - } \ - else \ - { \ - LL_RCC_LSE_Disable(); \ - LL_RCC_LSE_DisableBypass(); \ - } \ - } while(0U) +#define __HAL_RCC_LSE_CONFIG(__STATE__) \ + do { \ + if((__STATE__) == RCC_LSE_ON_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR,RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_ON) \ + { \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS_RTC_ONLY) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \ + } \ + else if((__STATE__) == RCC_LSE_BYPASS) \ + { \ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + SET_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + } \ + else \ + { \ + CLEAR_BIT(RCC->BDCR, (RCC_BDCR_LSEON | RCC_BDCR_LSESYSEN)); \ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \ + } \ + } while(0) /** @brief Macro to configure the RTC clock (RTCCLK). * @note As the RTC clock configuration bits are in the Backup domain and write diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng.h index c8078227ec..13989e4a37 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng.h @@ -178,6 +178,7 @@ typedef void (*pRNG_ReadyDataCallbackTypeDef)(RNG_HandleTypeDef *hrng, uint32_t #define HAL_RNG_ERROR_BUSY 0x00000004U /*!< Busy error */ #define HAL_RNG_ERROR_SEED 0x00000008U /*!< Seed error */ #define HAL_RNG_ERROR_CLOCK 0x00000010U /*!< Clock error */ +#define HAL_RNG_ERROR_RECOVERSEED 0x00000020U /*!< Recover Seed error */ /** * @} */ @@ -317,7 +318,7 @@ HAL_StatusTypeDef HAL_RNG_UnRegisterReadyDataCallback(RNG_HandleTypeDef *hrng); */ HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit); HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber_IT(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_ReadLastRandomNumber(RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_ReadLastRandomNumber(const RNG_HandleTypeDef *hrng); void HAL_RNG_IRQHandler(RNG_HandleTypeDef *hrng); void HAL_RNG_ErrorCallback(RNG_HandleTypeDef *hrng); @@ -330,8 +331,8 @@ void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit); /** @defgroup RNG_Exported_Functions_Group3 Peripheral State functions * @{ */ -HAL_RNG_StateTypeDef HAL_RNG_GetState(RNG_HandleTypeDef *hrng); -uint32_t HAL_RNG_GetError(RNG_HandleTypeDef *hrng); +HAL_RNG_StateTypeDef HAL_RNG_GetState(const RNG_HandleTypeDef *hrng); +uint32_t HAL_RNG_GetError(const RNG_HandleTypeDef *hrng); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng_ex.h index 4e96a95773..ce3640cf4a 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rng_ex.h @@ -34,19 +34,19 @@ extern "C" { #if defined(RNG) #if defined(RNG_CR_CONDRST) -/** @defgroup RNG_Ex RNG_Ex +/** @defgroup RNGEx RNGEx * @brief RNG Extension HAL module driver * @{ */ /* Exported types ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Types RNG_Ex Exported Types - * @brief RNG_Ex Exported types +/** @defgroup RNGEx_Exported_Types RNGEx Exported Types + * @brief RNGEx Exported types * @{ */ /** - * @brief RNG_Ex Configuration Structure definition + * @brief RNGEx Configuration Structure definition */ typedef struct @@ -55,9 +55,9 @@ typedef struct uint32_t Config2; /*!< Config2 must be a value between 0 and 0x7 */ uint32_t Config3; /*!< Config3 must be a value between 0 and 0xF */ uint32_t ClockDivider; /*!< Clock Divider factor.This parameter can - be a value of @ref RNG_Ex_Clock_Divider_Factor */ + be a value of @ref RNGEx_Clock_Divider_Factor */ uint32_t NistCompliance; /*!< NIST compliance.This parameter can be a - value of @ref RNG_Ex_NIST_Compliance */ + value of @ref RNGEx_NIST_Compliance */ } RNG_ConfigTypeDef; /** @@ -65,11 +65,11 @@ typedef struct */ /* Exported constants --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Constants RNG_Ex Exported Constants +/** @defgroup RNGEx_Exported_Constants RNGEx Exported Constants * @{ */ -/** @defgroup RNG_Ex_Clock_Divider_Factor Value used to configure an internal +/** @defgroup RNGEx_Clock_Divider_Factor Value used to configure an internal * programmable divider acting on the incoming RNG clock * @{ */ @@ -108,7 +108,7 @@ typedef struct * @} */ -/** @defgroup RNG_Ex_NIST_Compliance NIST Compliance configuration +/** @defgroup RNGEx_NIST_Compliance NIST Compliance configuration * @{ */ #define RNG_NIST_COMPLIANT (0x00000000UL) /*!< NIST compliant configuration*/ @@ -123,7 +123,7 @@ typedef struct */ /* Private types -------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Types RNG_Ex Private Types +/** @defgroup RNGEx_Private_Types RNGEx Private Types * @{ */ @@ -132,7 +132,7 @@ typedef struct */ /* Private variables ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Variables RNG_Ex Private Variables +/** @defgroup RNGEx_Private_Variables RNGEx Private Variables * @{ */ @@ -141,7 +141,7 @@ typedef struct */ /* Private constants ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Constants RNG_Ex Private Constants +/** @defgroup RNGEx_Private_Constants RNGEx Private Constants * @{ */ @@ -150,7 +150,7 @@ typedef struct */ /* Private macros ------------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Macros RNG_Ex Private Macros +/** @defgroup RNGEx_Private_Macros RNGEx Private Macros * @{ */ @@ -187,7 +187,7 @@ typedef struct */ /* Private functions ---------------------------------------------------------*/ -/** @defgroup RNG_Ex_Private_Functions RNG_Ex Private Functions +/** @defgroup RNGEx_Private_Functions RNGEx Private Functions * @{ */ @@ -196,14 +196,14 @@ typedef struct */ /* Exported functions --------------------------------------------------------*/ -/** @defgroup RNG_Ex_Exported_Functions RNG_Ex Exported Functions +/** @addtogroup RNGEx_Exported_Functions * @{ */ -/** @addtogroup RNG_Ex_Exported_Functions_Group1 +/** @addtogroup RNGEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); +HAL_StatusTypeDef HAL_RNGEx_SetConfig(RNG_HandleTypeDef *hrng, const RNG_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_RNGEx_GetConfig(RNG_HandleTypeDef *hrng, RNG_ConfigTypeDef *pConf); HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); @@ -211,7 +211,7 @@ HAL_StatusTypeDef HAL_RNGEx_LockConfig(RNG_HandleTypeDef *hrng); * @} */ -/** @addtogroup RNG_Ex_Exported_Functions_Group2 +/** @addtogroup RNGEx_Exported_Functions_Group2 * @{ */ HAL_StatusTypeDef HAL_RNGEx_RecoverSeedError(RNG_HandleTypeDef *hrng); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h index 2519a94f0e..d904523122 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc.h @@ -561,10 +561,11 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ - do{ \ - RTC->WPR = 0xCAU; \ - RTC->WPR = 0x53U; \ +#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->WPR = 0xCAU; \ + RTC->WPR = 0x53U; \ } while(0U) /** @@ -572,9 +573,10 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ - do{ \ - RTC->WPR = 0xFFU; \ +#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->WPR = 0xFFU; \ } while(0U) /** @@ -588,13 +590,13 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_STOREOPERATION_SET * @retval None */ -#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ - do { \ - __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ - SET_BIT(RTC->CR, RTC_CR_ADD1H); \ - MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ - __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ - } while(0); +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_ADD1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_ADD1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0U); /** * @brief Subtract 1 hour (winter time change). @@ -607,41 +609,41 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_STOREOPERATION_SET * @retval None */ -#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ - do { \ - __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ - SET_BIT(RTC->CR, RTC_CR_SUB1H); \ - MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ - __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ - } while(0); +#define __HAL_RTC_DAYLIGHT_SAVING_TIME_SUB1H(__HANDLE__, __BKP__) \ + do { \ + __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__); \ + SET_BIT(RTC->CR, RTC_CR_SUB1H); \ + MODIFY_REG(RTC->CR, RTC_CR_BKP , (__BKP__)); \ + __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__); \ + } while(0U); /** - * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__ specifies the RTC handle. - * @retval None - */ -#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRAE)) + * @brief Enable the RTC ALARMA peripheral. + * @param __HANDLE__ specifies the RTC handle. + * @retval None + */ +#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ALRAE))) /** * @brief Disable the RTC ALARMA peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRAE)) +#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ALRAE))) /** * @brief Enable the RTC ALARMB peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ALRBE))) /** * @brief Disable the RTC ALARMB peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ALRBE)) +#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ALRBE))) /** * @brief Enable the RTC Alarm interrupt. @@ -652,7 +654,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC Alarm interrupt. @@ -663,7 +665,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. @@ -674,7 +676,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR)& ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)) /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. @@ -685,7 +687,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_IT_ALRB Alarm B interrupt * @retval None */ -#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_ALARM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) /** * @brief Get the selected RTC Alarms flag status. @@ -696,7 +698,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__))) +#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (__HAL_RTC_GET_FLAG((__HANDLE__), (__FLAG__)))) /** * @brief Clear the RTC Alarms pending flags. @@ -707,16 +709,23 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to * @arg @ref RTC_FLAG_ALRBF * @retval None */ -#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == RTC_FLAG_ALRAF) ? ((RTC->SCR = (RTC_CLEAR_ALRAF))) : \ - (RTC->SCR = (RTC_CLEAR_ALRBF))) - +#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), \ + (((__FLAG__) == RTC_FLAG_ALRAF) ? (RTC->SCR = (RTC_CLEAR_ALRAF)) : \ + (RTC->SCR = (RTC_CLEAR_ALRBF)))) /** - * @brief Check whether if the RTC Calendar is initialized. + * @brief Check whether the RTC Calendar is initialized. * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_IS_CALENDAR_INITIALIZED(__HANDLE__) ((((RTC->ICSR) & (RTC_ICSR_INITS)) == RTC_ICSR_INITS) ? 1U : 0U) +/** + * @brief Get Binary mode + * @param __HANDLE__ specifies the RTC handle. + * @retval Selected Binary mode (RTC_BINARY_NONE, RTC_BINARY_ONLY, or RTC_BINARY_MIX) + */ +#define __HAL_RTC_GET_BINARY_MODE(__HANDLE__) (READ_REG(RTC->ICSR & RTC_ICSR_BIN)) + #if defined(CORE_CM0PLUS) #define __HAL_RTC_ALARM_EXTI_ENABLE_IT() (EXTI->C2IMR1 |= RTC_EXTI_LINE_ALARM_EVENT) #define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->C2IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) @@ -727,7 +736,7 @@ typedef void (*pRTC_CallbackTypeDef)(RTC_HandleTypeDef *hrtc); /*!< pointer to #define __HAL_RTC_ALARM_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) #define __HAL_RTC_ALARM_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_ALARM_EVENT) #define __HAL_RTC_ALARM_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_ALARM_EVENT)) -#endif +#endif /* CORE_CM0PLUS */ /** @@ -754,7 +763,8 @@ void HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc); /* Callbacks Register/UnRegister functions ***********************************/ #if (USE_HAL_RTC_REGISTER_CALLBACKS == 1) -HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, pRTC_CallbackTypeDef pCallback); +HAL_StatusTypeDef HAL_RTC_RegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID, + pRTC_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_RTC_REGISTER_CALLBACKS */ @@ -767,14 +777,14 @@ HAL_StatusTypeDef HAL_RTC_UnRegisterCallback(RTC_HandleTypeDef *hrtc, HAL_RTC_Ca */ /* RTC Time and Date functions ************************************************/ HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetTime(const RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); -void HAL_RTC_DST_Add1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_Sub1Hour(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_SetStoreOperation(RTC_HandleTypeDef *hrtc); -void HAL_RTC_DST_ClearStoreOperation(RTC_HandleTypeDef *hrtc); -uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_GetDate(const RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format); +void HAL_RTC_DST_Add1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_Sub1Hour(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_SetStoreOperation(const RTC_HandleTypeDef *hrtc); +void HAL_RTC_DST_ClearStoreOperation(const RTC_HandleTypeDef *hrtc); +uint32_t HAL_RTC_DST_ReadStoreOperation(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -786,7 +796,7 @@ uint32_t HAL_RTC_DST_ReadStoreOperation(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format); HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm); -HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); +HAL_StatusTypeDef HAL_RTC_GetAlarm(const RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format); void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); @@ -798,7 +808,7 @@ void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral Control functions ***********************************************/ -HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); +HAL_StatusTypeDef HAL_RTC_WaitForSynchro(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -807,7 +817,7 @@ HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef *hrtc); * @{ */ /* Peripheral State functions *************************************************/ -HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); +HAL_RTCStateTypeDef HAL_RTC_GetState(const RTC_HandleTypeDef *hrtc); /** * @} */ @@ -823,12 +833,12 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ /* Masks Definition */ -#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ - RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ - RTC_TR_SU) +#define RTC_TR_RESERVED_MASK (RTC_TR_PM | RTC_TR_HT | RTC_TR_HU | \ + RTC_TR_MNT | RTC_TR_MNU| RTC_TR_ST | \ + RTC_TR_SU) #define RTC_DR_RESERVED_MASK (RTC_DR_YT | RTC_DR_YU | RTC_DR_WDU | \ - RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ - RTC_DR_DU) + RTC_DR_MT | RTC_DR_MU | RTC_DR_DT | \ + RTC_DR_DU) #define RTC_INIT_MASK 0xFFFFFFFFu #define RTC_RSF_MASK (~(RTC_ICSR_INIT | RTC_ICSR_RSF)) @@ -849,10 +859,10 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); * @{ */ #define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ - ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ - ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ - ((OUTPUT) == RTC_OUTPUT_TAMPER)) + ((OUTPUT) == RTC_OUTPUT_ALARMA) || \ + ((OUTPUT) == RTC_OUTPUT_ALARMB) || \ + ((OUTPUT) == RTC_OUTPUT_WAKEUP) || \ + ((OUTPUT) == RTC_OUTPUT_TAMPER)) #define IS_RTC_HOUR_FORMAT(FORMAT) (((FORMAT) == RTC_HOURFORMAT_12) || \ ((FORMAT) == RTC_HOURFORMAT_24)) @@ -917,7 +927,7 @@ HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc); #define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= RTC_ALRMASSR_SS) #define IS_RTC_ALARM_SUB_SECOND_MASK(MASK) (((MASK) == 0UL) || \ - (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) + (((MASK) >= RTC_ALARMSUBSECONDMASK_SS14_1) && ((MASK) <= RTC_ALARMSUBSECONDMASK_NONE))) #define IS_RTC_ASYNCH_PREDIV(PREDIV) ((PREDIV) <= (RTC_PRER_PREDIV_A >> RTC_PRER_PREDIV_A_Pos)) diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h index ff66df3471..d8eb6efdef 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_rtc_ex.h @@ -173,8 +173,8 @@ typedef struct */ /** @defgroup RTCEx_Calib_Output_selection_Definitions RTCEx Calib Output selection Definitions - * @{ - */ + * @{ + */ #define RTC_CALIBOUTPUT_512HZ 0x00000000u #define RTC_CALIBOUTPUT_1HZ RTC_CR_COSEL @@ -236,8 +236,8 @@ typedef struct */ /** @defgroup RTCEx_Tamper_EraseBackUp RTCEx Tamper EraseBackUp -* @{ -*/ + * @{ + */ #define RTC_TAMPER_ERASE_BACKUP_ENABLE 0x00u #define RTC_TAMPER_ERASE_BACKUP_DISABLE 0x01u /** @@ -276,7 +276,7 @@ typedef struct #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512 (TAMP_FLTCR_TAMPFREQ_1 | TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 512 */ #define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256 (TAMP_FLTCR_TAMPFREQ_0 | TAMP_FLTCR_TAMPFREQ_1 | \ - TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled + TAMP_FLTCR_TAMPFREQ_2) /*!< Each of the tamper inputs are sampled with a frequency = RTCCLK / 256 */ /** * @} @@ -327,7 +327,8 @@ typedef struct #define RTC_IT_INT_TAMP_5 TAMP_IER_ITAMP5IE #define RTC_IT_INT_TAMP_6 TAMP_IER_ITAMP6IE #define RTC_IT_INT_TAMP_8 TAMP_IER_ITAMP8IE -#define RTC_IT_INT_TAMP_ALL (TAMP_IER_ITAMP3IE | TAMP_IER_ITAMP5IE | TAMP_IER_ITAMP6IE | TAMP_IER_ITAMP8IE) +#define RTC_IT_INT_TAMP_ALL (TAMP_IER_ITAMP3IE |\ + TAMP_IER_ITAMP5IE | TAMP_IER_ITAMP6IE | TAMP_IER_ITAMP8IE) /** * @} */ @@ -345,7 +346,8 @@ typedef struct #define RTC_FLAG_INT_TAMP_5 TAMP_SR_ITAMP5F #define RTC_FLAG_INT_TAMP_6 TAMP_SR_ITAMP6F #define RTC_FLAG_INT_TAMP_8 TAMP_SR_ITAMP8F -#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP3 | RTC_FLAG_INT_TAMP5 | RTC_FLAG_INT_TAMP6 | RTC_FLAG_INT_TAMP8) +#define RTC_FLAG_INT_TAMP_ALL (RTC_FLAG_INT_TAMP3 |\ + RTC_FLAG_INT_TAMP5 | RTC_FLAG_INT_TAMP6 | RTC_FLAG_INT_TAMP8) /** * @} */ @@ -518,7 +520,7 @@ typedef struct * @arg @ref RTC_CLEAR_ALRAF Clear Alarm A flag * @retval None */ -#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (RTC->SCR = (__FLAG__)) +#define __HAL_RTC_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (RTC->SCR = (__FLAG__))) /** @brief Check whether the specified RTC flag is set or not. * @param __HANDLE__ specifies the RTC Handle. @@ -538,8 +540,8 @@ typedef struct * @arg @ref RTC_FLAG_ALRAF Alarm A flag * @retval None */ -#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ - (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK)))) +#define __HAL_RTC_GET_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (((((__FLAG__)) >> 8U) == 1U) ? (RTC->ICSR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))) : \ + (RTC->SR & (1U << (((uint16_t)(__FLAG__)) & RTC_FLAG_MASK))))) /* ---------------------------------WAKEUPTIMER---------------------------------*/ /** @defgroup RTCEx_WakeUp_Timer RTC WakeUp Timer @@ -550,14 +552,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_WUTE))) /** * @brief Disable the RTC WakeUp Timer peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_WUTE)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_WUTE))) /** * @brief Enable the RTC WakeUpTimer interrupt. @@ -567,7 +569,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC WakeUpTimer interrupt. @@ -577,7 +579,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** @@ -588,7 +590,8 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0UL) ? 1UL : 0UL)) + /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -597,7 +600,7 @@ typedef struct * @arg @ref RTC_IT_WUT WakeUpTimer interrupt * @retval None */ -#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL) +#define __HAL_RTC_WAKEUPTIMER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0UL) ? 1UL : 0UL)) /** * @brief Get the selected RTC WakeUpTimers flag status. @@ -632,7 +635,7 @@ typedef struct #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) #define __HAL_RTC_WAKEUPTIMER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT) #define __HAL_RTC_WAKEUPTIMER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_WAKEUPTIMER_EVENT)) -#endif +#endif /* CORE_CM0PLUS */ /** * @} @@ -651,14 +654,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TSE)) +#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TSE))) /** * @brief Disable the RTC TimeStamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TSE)) +#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TSE))) /** * @brief Enable the RTC TimeStamp interrupt. @@ -668,7 +671,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR |= (__INTERRUPT__))) /** * @brief Disable the RTC TimeStamp interrupt. @@ -678,7 +681,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) +#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (RTC->CR &= ~(__INTERRUPT__))) /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. @@ -688,7 +691,8 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) ((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__),((((RTC->MISR) & ((__INTERRUPT__)>> 12U)) != 0U) ? 1UL : 0UL)) + /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -697,7 +701,7 @@ typedef struct * @arg @ref RTC_IT_TS TimeStamp interrupt * @retval None */ -#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TIMESTAMP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) /** * @brief Get the selected RTC TimeStamps flag status. @@ -733,21 +737,21 @@ typedef struct #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) #define __HAL_RTC_TIMESTAMP_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TIMESTAMP_EVENT) #define __HAL_RTC_TIMESTAMP_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TIMESTAMP_EVENT)) -#endif +#endif /* CORE_CM0PLUS */ /** * @brief Enable the RTC internal TimeStamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_ITSE)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_ITSE))) /** * @brief Disable the RTC internal TimeStamp peripheral. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_ITSE)) +#define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_ITSE))) /** * @brief Get the selected RTC Internal Time Stamps flag status. @@ -774,28 +778,28 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPTS)) +#define __HAL_RTC_TAMPTS_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TAMPTS))) /** * @brief Disable the RTC TimeStamp on Tamper detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPTS)) +#define __HAL_RTC_TAMPTS_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TAMPTS))) /** * @brief Enable the RTC Tamper detection output. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_TAMPOE)) +#define __HAL_RTC_TAMPOE_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_TAMPOE))) /** * @brief Disable the RTC Tamper detection output. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_TAMPOE)) +#define __HAL_RTC_TAMPOE_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_TAMPOE))) /** @@ -813,14 +817,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_COE))) /** * @brief Disable the calibration output. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_COE)) +#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_COE))) /** @@ -828,14 +832,14 @@ typedef struct * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (RTC->CR |= (RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR |= (RTC_CR_REFCKON))) /** * @brief Disable the clock reference detection. * @param __HANDLE__ specifies the RTC handle. * @retval None */ -#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (RTC->CR &= ~(RTC_CR_REFCKON)) +#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) (UNUSED(__HANDLE__), (RTC->CR &= ~(RTC_CR_REFCKON))) /** @@ -872,7 +876,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 |= (__TAMPER__)) +#define __HAL_RTC_TAMPER_ENABLE(__HANDLE__, __TAMPER__) (UNUSED(__HANDLE__), (TAMP->CR1 |= (__TAMPER__))) /** * @brief Disable the TAMP Tamper input detection. @@ -889,7 +893,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_6: Internal Tamper6 interrupt * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt */ -#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (TAMP->CR1 &= ~(__TAMPER__)) +#define __HAL_RTC_TAMPER_DISABLE(__HANDLE__, __TAMPER__) (UNUSED(__HANDLE__), (TAMP->CR1 &= ~(__TAMPER__))) /**************************************************************************************************/ @@ -909,7 +913,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER |= (__INTERRUPT__)) +#define __HAL_RTC_TAMPER_ENABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (TAMP->IER |= (__INTERRUPT__))) /** * @brief Disable the TAMP Tamper interrupt. @@ -927,7 +931,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (TAMP->IER &= ~(__INTERRUPT__)) +#define __HAL_RTC_TAMPER_DISABLE_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (TAMP->IER &= ~(__INTERRUPT__))) /**************************************************************************************************/ @@ -947,8 +951,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) - +#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((TAMP->MISR) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. @@ -966,7 +969,7 @@ typedef struct * @arg RTC_IT_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TAMPER_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((TAMP->IER) & (__INTERRUPT__)) != 0U) ? 1UL : 0UL)) /** @@ -983,7 +986,7 @@ typedef struct * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) ((((TAMP->SR) & (__FLAG__)) != 0U) ? 1UL : 0UL) +#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), (((TAMP->SR) & (__FLAG__)) != 0UL)) /** * @brief Clear the RTC Tamper's pending flags. @@ -1001,7 +1004,7 @@ typedef struct * @arg RTC_FLAG_INT_TAMP_8: Internal Tamper8 interrupt * @retval None */ -#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) (((TAMP->SCR) = (__FLAG__))) +#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__) (UNUSED(__HANDLE__), ((TAMP->SCR) = (__FLAG__))) /* TAMPER EXTI */ /* ----------- */ @@ -1015,7 +1018,7 @@ typedef struct #define __HAL_RTC_TAMPER_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) #define __HAL_RTC_TAMPER_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_TAMPER_EVENT) #define __HAL_RTC_TAMPER_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_TAMPER_EVENT)) -#endif +#endif /* CORE_CM0PLUS */ /** * @} @@ -1034,7 +1037,11 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR |= (__INTERRUPT__)) +#define __HAL_RTC_SSRU_ENABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->CR |= (__INTERRUPT__); \ + } while(0U); /** * @brief Disable the RTC SSRU interrupt. @@ -1044,8 +1051,11 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) (RTC->CR &= ~(__INTERRUPT__)) - +#define __HAL_RTC_SSRU_DISABLE_IT(__HANDLE__, __INTERRUPT__) \ + do{ \ + UNUSED(__HANDLE__); \ + RTC->CR &= ~(__INTERRUPT__); \ + } while(0U); /** * @brief Check whether the specified RTC SSRU interrupt has occurred or not. @@ -1055,7 +1065,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), (((RTC->MISR) & ((__INTERRUPT__) >> 1) != 0U) ? 1U : 0U)) /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. * @param __HANDLE__ specifies the RTC handle. @@ -1064,7 +1074,7 @@ typedef struct * @arg @ref RTC_IT_SSRU SSRU interrupt * @retval None */ -#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U) +#define __HAL_RTC_SSRU_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (UNUSED(__HANDLE__), ((((RTC->CR) & (__INTERRUPT__)) != 0U) ? 1U : 0U)) /** * @brief Get the selected RTC SSRU's flag status. @@ -1098,7 +1108,7 @@ typedef struct #define __HAL_RTC_SSRU_EXTI_DISABLE_IT() (EXTI->IMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT)) #define __HAL_RTC_SSRU_EXTI_ENABLE_EVENT() (EXTI->EMR1 |= RTC_EXTI_LINE_SSRU_EVENT) #define __HAL_RTC_SSRU_EXTI_DISABLE_EVENT() (EXTI->EMR1 &= ~(RTC_EXTI_LINE_SSRU_EVENT)) -#endif +#endif /* CORE_CM0PLUS */ /** * @} @@ -1123,7 +1133,8 @@ HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t Ti HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_SetInternalTimeStamp(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_DeactivateInternalTimeStamp(RTC_HandleTypeDef *hrtc); -HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format); +HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, + RTC_DateTypeDef *sTimeStampDate, uint32_t Format); void HAL_RTCEx_TimeStampIRQHandler(RTC_HandleTypeDef *hrtc); HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout); void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); @@ -1134,11 +1145,12 @@ void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc); /* RTC Wake-up functions ******************************************************/ /** @defgroup RTCEx_Exported_Functions_Group2 Extended RTC Wake-up functions - * @{ - */ + * @{ + */ HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock); -HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, uint32_t WakeUpAutoClr); +HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock, + uint32_t WakeUpAutoClr); HAL_StatusTypeDef HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc); uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc); void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc); @@ -1150,10 +1162,11 @@ HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uin /* Extended Control functions ************************************************/ /** @defgroup RTCEx_Exported_Functions_Group3 Extended Peripheral Control functions - * @{ - */ + * @{ + */ -HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); +HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, + uint32_t SmoothCalibPlusPulses, uint32_t SmoothCalibMinusPulsesValue); HAL_StatusTypeDef HAL_RTCEx_SetLowPowerCalib(RTC_HandleTypeDef *hrtc, uint32_t LowPowerCalib); HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS); HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput); @@ -1207,8 +1220,8 @@ void HAL_RTCEx_InternalTamper8EventCallback(RTC_HandleTypeDef *hrtc */ /** @defgroup RTCEx_Exported_Functions_Group6 Extended RTC Backup register functions - * @{ - */ + * @{ + */ void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data); uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister); /** @@ -1332,7 +1345,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg #define IS_RTC_BINARY_MODE(MODE) (((MODE) == RTC_BINARY_NONE) || \ ((MODE) == RTC_BINARY_ONLY) || \ - ((MODE) == RTC_BINARY_MIX )) + ((MODE) == RTC_BINARY_MIX )) #define IS_RTC_BINARY_MIX_BCDU(BDCU) (((BDCU) == RTC_BINARY_MIX_BCDU_0) || \ ((BDCU) == RTC_BINARY_MIX_BCDU_1) || \ @@ -1344,7 +1357,7 @@ uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupReg ((BDCU) == RTC_BINARY_MIX_BCDU_7)) #define IS_RTC_ALARM_SUB_SECOND_BINARY_MASK(MASK) (((MASK) == 0u) || \ - (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) && ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) + (((MASK) >= RTC_ALARMSUBSECONDBINMASK_SS31_1) && ((MASK) <= RTC_ALARMSUBSECONDBINMASK_NONE))) #define IS_RTC_ALARMSUBSECONDBIN_AUTOCLR(SEL) (((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_NO) || \ ((SEL) == RTC_ALARMSUBSECONDBIN_AUTOCLR_YES)) diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smartcard.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smartcard.h index 4a1abab101..bf130fd7ff 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smartcard.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smartcard.h @@ -51,7 +51,8 @@ typedef struct where usart_ker_ckpres is the USART input clock divided by a prescaler */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter @ref SMARTCARD_Word_Length can only be set to 9 (8 data + 1 parity bits). */ + This parameter @ref SMARTCARD_Word_Length can only be + set to 9 (8 data + 1 parity bits). */ uint32_t StopBits; /*!< Specifies the number of stop bits. This parameter can be a value of @ref SMARTCARD_Stop_Bits. */ @@ -75,13 +76,14 @@ typedef struct data bit (MSB) has to be output on the SCLK pin in synchronous mode. This parameter can be a value of @ref SMARTCARD_Last_Bit */ - uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref SMARTCARD_OneBit_Sampling. */ + uint16_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote + is selected. Selecting the single sample method increases + the receiver tolerance to clock deviations. This parameter can be a value + of @ref SMARTCARD_OneBit_Sampling. */ uint8_t Prescaler; /*!< Specifies the SmartCard Prescaler. - This parameter can be any value from 0x01 to 0x1F. Prescaler value is multiplied - by 2 to give the division factor of the source clock frequency */ + This parameter can be any value from 0x01 to 0x1F. Prescaler value is + multiplied by 2 to give the division factor of the source clock frequency */ uint8_t GuardTime; /*!< Specifies the SmartCard Guard Time applied after stop bits. */ @@ -140,14 +142,16 @@ typedef struct uint32_t MSBFirst; /*!< Specifies whether MSB is sent first on UART line. This parameter can be a value of @ref SMARTCARD_MSB_First */ - uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when - relevant flag is available) or once guard time period has elapsed. - This parameter can be a value of @ref SMARTCARDEx_Transmission_Completion_Indication. */ + uint16_t TxCompletionIndication; /*!< Specifies which transmission completion indication is used: before (when + relevant flag is available) or once guard time period has elapsed. + This parameter can be a value + of @ref SMARTCARDEx_Transmission_Completion_Indication. */ } SMARTCARD_AdvFeatureInitTypeDef; /** * @brief HAL SMARTCARD State definition - * @note HAL SMARTCARD State value is a combination of 2 different substates: gState and RxState (see @ref SMARTCARD_State_Definition). + * @note HAL SMARTCARD State value is a combination of 2 different substates: + * gState and RxState (see @ref SMARTCARD_State_Definition). * - gState contains SMARTCARD state information related to global Handle management * and also information related to Tx operations. * gState value coding follow below described bitmap : @@ -214,7 +218,8 @@ typedef struct __SMARTCARD_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. - This parameter can be a value of @ref SMARTCARDEx_FIFO_mode. */ + This parameter can be a value of + @ref SMARTCARDEx_FIFO_mode. */ void (*RxISR)(struct __SMARTCARD_HandleTypeDef *huart); /*!< Function pointer on Rx IRQ handler */ @@ -226,12 +231,14 @@ typedef struct __SMARTCARD_HandleTypeDef HAL_LockTypeDef Lock; /*!< Locking object */ - __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global Handle management - and also related to Tx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + __IO HAL_SMARTCARD_StateTypeDef gState; /*!< SmartCard state information related to global + Handle management and also related to Tx operations. + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO HAL_SMARTCARD_StateTypeDef RxState; /*!< SmartCard state information related to Rx operations. - This parameter can be a value of @ref HAL_SMARTCARD_StateTypeDef */ + This parameter can be a value + of @ref HAL_SMARTCARD_StateTypeDef */ __IO uint32_t ErrorCode; /*!< SmartCard Error code */ @@ -311,23 +318,26 @@ typedef enum /** @defgroup SMARTCARD_State_Definition SMARTCARD State Code Definition * @{ */ -#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized - Value is allowed for gState and RxState */ -#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for use - Value is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_RESET 0x00000000U /*!< Peripheral is not initialized. Value + is allowed for gState and RxState */ +#define HAL_SMARTCARD_STATE_READY 0x00000020U /*!< Peripheral Initialized and ready for + use. Value is allowed for gState + and RxState */ #define HAL_SMARTCARD_STATE_BUSY 0x00000024U /*!< an internal process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_TX 0x00000021U /*!< Data Transmission process is ongoing - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_BUSY_RX 0x00000022U /*!< Data Reception process is ongoing Value is allowed for RxState only */ -#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception process is ongoing - Not to be used for neither gState nor RxState. - Value is result of combination (Or) between gState and RxState values */ +#define HAL_SMARTCARD_STATE_BUSY_TX_RX 0x00000023U /*!< Data Transmission and Reception + process is ongoing Not to be used for + neither gState nor RxState. + Value is result of combination (Or) + between gState and RxState values */ #define HAL_SMARTCARD_STATE_TIMEOUT 0x000000A0U /*!< Timeout state - Value is allowed for gState only */ + Value is allowed for gState only */ #define HAL_SMARTCARD_STATE_ERROR 0x000000E0U /*!< Error - Value is allowed for gState only */ + Value is allowed for gState only */ /** * @} */ @@ -335,15 +345,15 @@ typedef enum /** @defgroup SMARTCARD_Error_Definition SMARTCARD Error Code Definition * @{ */ -#define HAL_SMARTCARD_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_SMARTCARD_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_SMARTCARD_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_SMARTCARD_ERROR_FE ((uint32_t)0x00000004U) /*!< frame error */ -#define HAL_SMARTCARD_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_SMARTCARD_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_SMARTCARD_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver TimeOut error */ +#define HAL_SMARTCARD_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_SMARTCARD_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_SMARTCARD_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_SMARTCARD_ERROR_FE (0x00000004U) /*!< frame error */ +#define HAL_SMARTCARD_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_SMARTCARD_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_SMARTCARD_ERROR_RTO (0x00000020U) /*!< Receiver TimeOut error */ #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) -#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_SMARTCARD_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ /** * @} @@ -663,7 +673,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before + * guard time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -676,9 +687,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))):\ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Disable the specified SmartCard interrupt. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -688,7 +706,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard + * time interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -701,9 +720,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval None */ -#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) +#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1UL <<\ + ((__INTERRUPT__) & SMARTCARD_IT_MASK)))) /** @brief Check whether the specified SmartCard interrupt has occurred or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -713,7 +739,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -726,8 +753,10 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __INTERRUPT__) (\ + (((__HANDLE__)->Instance->ISR & (0x01UL << (((__INTERRUPT__)\ + & SMARTCARD_ISR_MASK)>> SMARTCARD_ISR_POS)))!= 0U)\ + ? SET : RESET) /** @brief Check whether the specified SmartCard interrupt source is enabled or not. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -737,7 +766,8 @@ typedef enum * @arg @ref SMARTCARD_IT_RTO Receive timeout interrupt * @arg @ref SMARTCARD_IT_TXE Transmit data register empty interrupt * @arg @ref SMARTCARD_IT_TC Transmission complete interrupt - * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time interrupt (when interruption available) + * @arg @ref SMARTCARD_IT_TCBGT Transmission complete before guard time + * interrupt (when interruption available) * @arg @ref SMARTCARD_IT_RXNE Receive data register not empty interrupt * @arg @ref SMARTCARD_IT_IDLE Idle line detection interrupt * @arg @ref SMARTCARD_IT_PE Parity error interrupt @@ -750,9 +780,16 @@ typedef enum * @arg @ref SMARTCARD_IT_TXFT TXFIFO threshold reached interruption * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x01U)? (__HANDLE__)->Instance->CR1 : \ - (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >> SMARTCARD_CR_POS) == 0x02U)? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & ((uint32_t)0x01U << (((uint16_t)(__INTERRUPT__)) & SMARTCARD_IT_MASK))) != 0U) ? SET : RESET) +#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x01U)?\ + (__HANDLE__)->Instance->CR1 : \ + (((((__INTERRUPT__) & SMARTCARD_CR_MASK) >>\ + SMARTCARD_CR_POS) == 0x02U)?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) &\ + (0x01UL << (((uint16_t)(__INTERRUPT__))\ + & SMARTCARD_IT_MASK))) != 0U)\ + ? SET : RESET) /** @brief Clear the specified SMARTCARD ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the SMARTCARD Handle. @@ -873,7 +910,7 @@ typedef enum } while(0U) /** @brief Check the Baud rate range. - * @note The maximum Baud Rate is derived from the maximum clock on WB (48 MHz) + * @note The maximum Baud Rate is derived from the maximum clock on WL (48 MHz) * divided by the oversampling used on the SMARTCARD (i.e. 16). * @param __BAUDRATE__ Baud rate set by the configuration function. * @retval Test result (TRUE or FALSE) @@ -1079,7 +1116,8 @@ void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsmartcard); #if (USE_HAL_SMARTCARD_REGISTER_CALLBACKS == 1) /* Callbacks Register/UnRegister functions ***********************************/ HAL_StatusTypeDef HAL_SMARTCARD_RegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, - HAL_SMARTCARD_CallbackIDTypeDef CallbackID, pSMARTCARD_CallbackTypeDef pCallback); + HAL_SMARTCARD_CallbackIDTypeDef CallbackID, + pSMARTCARD_CallbackTypeDef pCallback); HAL_StatusTypeDef HAL_SMARTCARD_UnRegisterCallback(SMARTCARD_HandleTypeDef *hsmartcard, HAL_SMARTCARD_CallbackIDTypeDef CallbackID); #endif /* USE_HAL_SMARTCARD_REGISTER_CALLBACKS */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h index 423f747b6c..9157ba8ea8 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_smbus.h @@ -100,8 +100,6 @@ typedef struct #define HAL_SMBUS_STATE_MASTER_BUSY_RX (0x00000022U) /*!< Master Data Reception process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_TX (0x00000032U) /*!< Slave Data Transmission process is ongoing */ #define HAL_SMBUS_STATE_SLAVE_BUSY_RX (0x00000042U) /*!< Slave Data Reception process is ongoing */ -#define HAL_SMBUS_STATE_TIMEOUT (0x00000003U) /*!< Timeout state */ -#define HAL_SMBUS_STATE_ERROR (0x00000004U) /*!< Reception process is ongoing */ #define HAL_SMBUS_STATE_LISTEN (0x00000008U) /*!< Address Listen Mode is ongoing */ /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi.h index 1dda8b4f92..f6953357c4 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi.h @@ -118,7 +118,7 @@ typedef struct __SPI_HandleTypeDef SPI_InitTypeDef Init; /*!< SPI communication parameters */ - uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ + const uint8_t *pTxBuffPtr; /*!< Pointer to SPI Tx transfer Buffer */ uint16_t TxXferSize; /*!< SPI Tx Transfer size */ @@ -426,11 +426,12 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval None */ #if (USE_HAL_SPI_REGISTER_CALLBACKS == 1U) -#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) do{ \ - (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ - (__HANDLE__)->MspInitCallback = NULL; \ - (__HANDLE__)->MspDeInitCallback = NULL; \ - } while(0) +#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) \ + do{ \ + (__HANDLE__)->State = HAL_SPI_STATE_RESET; \ + (__HANDLE__)->MspInitCallback = NULL; \ + (__HANDLE__)->MspDeInitCallback = NULL; \ + } while(0) #else #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) #endif /* USE_HAL_SPI_REGISTER_CALLBACKS */ @@ -533,7 +534,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to __IO uint32_t tmpreg_fre = 0x00U; \ tmpreg_fre = (__HANDLE__)->Instance->SR; \ UNUSED(tmpreg_fre); \ - }while(0U) + } while(0U) /** @brief Enable the SPI peripheral. * @param __HANDLE__ specifies the SPI Handle. @@ -577,8 +578,11 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ -#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\ - SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0U) +#define SPI_RESET_CRC(__HANDLE__) \ + do{ \ + CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN); \ + } while(0U) /** @brief Check whether the specified SPI flag is set or not. * @param __SR__ copy of SPI SR register. @@ -596,7 +600,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_FLAG(__SR__, __FLAG__) ((((__SR__) & ((__FLAG__) & SPI_FLAG_MASK)) == \ - ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) + ((__FLAG__) & SPI_FLAG_MASK)) ? SET : RESET) /** @brief Check whether the specified SPI Interrupt is set or not. * @param __CR2__ copy of SPI CR2 register. @@ -608,7 +612,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to * @retval SET or RESET. */ #define SPI_CHECK_IT_SOURCE(__CR2__, __INTERRUPT__) ((((__CR2__) & (__INTERRUPT__)) == \ - (__INTERRUPT__)) ? SET : RESET) + (__INTERRUPT__)) ? SET : RESET) /** @brief Checks if SPI Mode parameter is in allowed range. * @param __MODE__ specifies the SPI Mode. @@ -746,7 +750,7 @@ typedef void (*pSPI_CallbackTypeDef)(SPI_HandleTypeDef *hspi); /*!< pointer to */ #define IS_SPI_CRC_POLYNOMIAL(__POLYNOMIAL__) (((__POLYNOMIAL__) >= 0x1U) && \ ((__POLYNOMIAL__) <= 0xFFFFU) && \ - (((__POLYNOMIAL__)&0x1U) != 0U)) + (((__POLYNOMIAL__)&0x1U) != 0U)) /** @brief Checks if DMA handle is valid. * @param __HANDLE__ specifies a DMA Handle. @@ -789,17 +793,17 @@ HAL_StatusTypeDef HAL_SPI_UnRegisterCallback(SPI_HandleTypeDef *hspi, HAL_SPI_Ca * @{ */ /* I/O operation functions ***************************************************/ -HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, - uint32_t Timeout); -HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, + uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); +HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size); -HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, +HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size); HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi); HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi); @@ -825,8 +829,8 @@ void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi); -uint32_t HAL_SPI_GetError(SPI_HandleTypeDef *hspi); +HAL_SPI_StateTypeDef HAL_SPI_GetState(const SPI_HandleTypeDef *hspi); +uint32_t HAL_SPI_GetError(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi_ex.h index 49d73588ed..2bbd7f7786 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_spi_ex.h @@ -48,7 +48,7 @@ extern "C" { /** @addtogroup SPIEx_Exported_Functions_Group1 * @{ */ -HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(SPI_HandleTypeDef *hspi); +HAL_StatusTypeDef HAL_SPIEx_FlushRxFifo(const SPI_HandleTypeDef *hspi); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h index 895a44320e..007306cffb 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_subghz.h @@ -201,6 +201,7 @@ typedef enum #define HAL_SUBGHZ_ERROR_NONE (0x00000000U) /*!< No error */ #define HAL_SUBGHZ_ERROR_TIMEOUT (0x00000001U) /*!< Timeout Error */ #define HAL_SUBGHZ_ERROR_RF_BUSY (0x00000002U) /*!< RF Busy Error */ +#define HAL_SUBGHZ_ERROR_CRC_MISMATCH (0x00000004U) /*!< CRC mismatch Error */ #if (USE_HAL_SUBGHZ_REGISTER_CALLBACKS == 1) #define HAL_SUBGHZ_ERROR_INVALID_CALLBACK (0x00000080U) /*!< Invalid Callback error */ #endif /* USE_HAL_SUBGHZ_REGISTER_CALLBACKS */ @@ -399,8 +400,8 @@ void HAL_SUBGHZ_LrFhssHopCallback(SUBGHZ_HandleTypeDef *hsubghz); * @{ */ /* Peripheral State and Error functions ***************************************/ -HAL_SUBGHZ_StateTypeDef HAL_SUBGHZ_GetState(SUBGHZ_HandleTypeDef *hsubghz); -uint32_t HAL_SUBGHZ_GetError(SUBGHZ_HandleTypeDef *hsubghz); +HAL_SUBGHZ_StateTypeDef HAL_SUBGHZ_GetState(const SUBGHZ_HandleTypeDef *hsubghz); +uint32_t HAL_SUBGHZ_GetError(const SUBGHZ_HandleTypeDef *hsubghz); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim.h index 406da1389b..be6dff2e2d 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim.h @@ -402,29 +402,28 @@ typedef struct */ typedef enum { - HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ - , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ - , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ - , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ - , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ - , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ - , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ - , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ - , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ - , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ - , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ - , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ + HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U /*!< TIM Base MspInit Callback ID */ + , HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U /*!< TIM Base MspDeInit Callback ID */ + , HAL_TIM_IC_MSPINIT_CB_ID = 0x02U /*!< TIM IC MspInit Callback ID */ + , HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U /*!< TIM IC MspDeInit Callback ID */ + , HAL_TIM_OC_MSPINIT_CB_ID = 0x04U /*!< TIM OC MspInit Callback ID */ + , HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U /*!< TIM OC MspDeInit Callback ID */ + , HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U /*!< TIM PWM MspInit Callback ID */ + , HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U /*!< TIM PWM MspDeInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U /*!< TIM One Pulse MspInit Callback ID */ + , HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U /*!< TIM One Pulse MspDeInit Callback ID */ + , HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU /*!< TIM Encoder MspInit Callback ID */ + , HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU /*!< TIM Encoder MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU /*!< TIM Hall Sensor MspDeInit Callback ID */ + , HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU /*!< TIM Hall Sensor MspDeInit Callback ID */ , HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU /*!< TIM Period Elapsed Callback ID */ , HAL_TIM_PERIOD_ELAPSED_HALF_CB_ID = 0x0FU /*!< TIM Period Elapsed half complete Callback ID */ , HAL_TIM_TRIGGER_CB_ID = 0x10U /*!< TIM Trigger Callback ID */ , HAL_TIM_TRIGGER_HALF_CB_ID = 0x11U /*!< TIM Trigger half complete Callback ID */ - , HAL_TIM_IC_CAPTURE_CB_ID = 0x12U /*!< TIM Input Capture Callback ID */ , HAL_TIM_IC_CAPTURE_HALF_CB_ID = 0x13U /*!< TIM Input Capture half complete Callback ID */ , HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x14U /*!< TIM Output Compare Delay Elapsed Callback ID */ - , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ + , HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x15U /*!< TIM PWM Pulse Finished Callback ID */ , HAL_TIM_PWM_PULSE_FINISHED_HALF_CB_ID = 0x16U /*!< TIM PWM Pulse Finished half complete Callback ID */ , HAL_TIM_ERROR_CB_ID = 0x17U /*!< TIM Error Callback ID */ , HAL_TIM_COMMUTATION_CB_ID = 0x18U /*!< TIM Commutation Callback ID */ @@ -1024,8 +1023,8 @@ typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef *htim); /*!< pointer to #define TIM_OCMODE_RETRIGERRABLE_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!< Retrigerrable OPM mode 2 */ #define TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 1 */ #define TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!< Combined PWM mode 2 */ -#define TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ -#define TIM_OCMODE_ASSYMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ +#define TIM_OCMODE_ASYMMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!< Asymmetric PWM mode 1 */ +#define TIM_OCMODE_ASYMMETRIC_PWM2 TIM_CCMR1_OC1M /*!< Asymmetric PWM mode 2 */ /** * @} */ @@ -1752,7 +1751,8 @@ mode. */ /* The counter of a timer instance is disabled only if all the CCx and CCxN channels have been disabled */ -#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) +#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E | \ + TIM_CCER_CC5E | TIM_CCER_CC6E)) #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) /** * @} @@ -1842,6 +1842,10 @@ mode. ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ ((__PRESCALER__) == TIM_ICPSC_DIV8)) +#define IS_TIM_CCX_CHANNEL(__INSTANCE__, __CHANNEL__) (IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) && \ + ((__CHANNEL__) != (TIM_CHANNEL_5)) && \ + ((__CHANNEL__) != (TIM_CHANNEL_6))) + #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ ((__MODE__) == TIM_OPMODE_REPETITIVE)) @@ -1862,8 +1866,9 @@ mode. #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2)) -#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) \ - ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : ((__PERIOD__) > 0U)) +#define IS_TIM_PERIOD(__HANDLE__, __PERIOD__) ((IS_TIM_32B_COUNTER_INSTANCE(((__HANDLE__)->Instance)) == 0U) ? \ + (((__PERIOD__) > 0U) && ((__PERIOD__) <= 0x0000FFFFU)) : \ + ((__PERIOD__) > 0U)) #define IS_TIM_COMPLEMENTARY_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ ((__CHANNEL__) == TIM_CHANNEL_2) || \ @@ -1916,7 +1921,6 @@ mode. #define IS_TIM_BREAK_FILTER(__BRKFILTER__) ((__BRKFILTER__) <= 0xFUL) - #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \ ((__STATE__) == TIM_BREAK_DISABLE)) @@ -1983,8 +1987,8 @@ mode. ((__MODE__) == TIM_OCMODE_PWM2) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM1) || \ ((__MODE__) == TIM_OCMODE_COMBINED_PWM2) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM1) || \ - ((__MODE__) == TIM_OCMODE_ASSYMETRIC_PWM2)) + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM1) || \ + ((__MODE__) == TIM_OCMODE_ASYMMETRIC_PWM2)) #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ ((__MODE__) == TIM_OCMODE_ACTIVE) || \ @@ -2099,20 +2103,15 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_5) ? ((__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[3] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[4] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelState[5] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[3] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[4] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelState[5] = (__CHANNEL_STATE__); \ + } while(0) #define TIM_CHANNEL_N_STATE_GET(__HANDLE__, __CHANNEL__)\ (((__CHANNEL__) == TIM_CHANNEL_1) ? (__HANDLE__)->ChannelNState[0] :\ @@ -2126,16 +2125,13 @@ mode. ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__)) :\ ((__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__))) -#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__) do { \ - (__HANDLE__)->ChannelNState[0] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[1] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[2] = \ - (__CHANNEL_STATE__); \ - (__HANDLE__)->ChannelNState[3] = \ - (__CHANNEL_STATE__); \ - } while(0) +#define TIM_CHANNEL_N_STATE_SET_ALL(__HANDLE__, __CHANNEL_STATE__)\ + do {\ + (__HANDLE__)->ChannelNState[0] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[1] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[2] = (__CHANNEL_STATE__); \ + (__HANDLE__)->ChannelNState[3] = (__CHANNEL_STATE__); \ + } while(0) /** * @} @@ -2264,7 +2260,7 @@ HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Out * @{ */ /* Timer Encoder functions ****************************************************/ -HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef *sConfig); +HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, const TIM_Encoder_InitTypeDef *sConfig); HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); @@ -2313,7 +2309,8 @@ HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_S HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchro_IT(TIM_HandleTypeDef *htim, const TIM_SlaveConfigTypeDef *sSlaveConfig); HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, - uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength); + uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, + uint32_t BurstLength); HAL_StatusTypeDef HAL_TIM_DMABurst_MultiWriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, const uint32_t *BurstBuffer, uint32_t BurstLength, uint32_t DataLength); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim_ex.h index a1b4a0b14f..9ff28e113c 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_tim_ex.h @@ -309,7 +309,7 @@ HAL_StatusTypeDef HAL_TIMEx_GroupChannel5(TIM_HandleTypeDef *htim, uint32_t Chan HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap); HAL_StatusTypeDef HAL_TIMEx_DisarmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); -HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(TIM_HandleTypeDef *htim, uint32_t BreakInput); +HAL_StatusTypeDef HAL_TIMEx_ReArmBreakInput(const TIM_HandleTypeDef *htim, uint32_t BreakInput); /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h index 912f6ffcce..94f4a63251 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart.h @@ -45,54 +45,52 @@ extern "C" { */ typedef struct { - uint32_t BaudRate; /*!< This member configures the UART communication baud rate. - The baud rate register is computed using the following formula: - - LPUART: - Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) - - where lpuart_ker_ck_pres is the UART input clock divided by a prescaler - - UART: - - If oversampling is 16 or in LIN mode, - Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) - - If oversampling is 8, - Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[15:4] - Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / - ((huart->Init.BaudRate)))[3:0]) >> 1 - - where uart_ker_ckpres is the UART input clock divided by a prescaler */ - - uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref UARTEx_Word_Length. */ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref UART_Stop_Bits. */ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref UART_Parity - @note When parity is enabled, the computed parity is inserted - at the MSB position of the transmitted data (9th bit when - the word length is set to 9 data bits; 8th bit when the - word length is set to 8 data bits). */ - - uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. - This parameter can be a value of @ref UART_Mode. */ - - uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled - or disabled. - This parameter can be a value of @ref UART_Hardware_Flow_Control. */ - - uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, - to achieve higher speed (up to f_PCLK/8). - This parameter can be a value of @ref UART_Over_Sampling. */ - - uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. - Selecting the single sample method increases the receiver tolerance to clock - deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ - - uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. - This parameter can be a value of @ref UART_ClockPrescaler. */ + uint32_t BaudRate; /*!< This member configures the UART communication baud rate. + The baud rate register is computed using the following formula: + @note For LPUART : + Baud Rate Register = ((256 * lpuart_ker_ckpres) / ((huart->Init.BaudRate))) + where lpuart_ker_ck_pres is the UART input clock divided by a prescaler. + @note For UART : + - If oversampling is 16 or in LIN mode, + Baud Rate Register = ((uart_ker_ckpres) / ((huart->Init.BaudRate))) + - If oversampling is 8, + Baud Rate Register[15:4] = ((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[3] = 0 + Baud Rate Register[2:0] = (((2 * uart_ker_ckpres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where uart_ker_ck_pres is the UART input clock divided by a prescaler */ + + uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref UARTEx_Word_Length. */ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref UART_Stop_Bits. */ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref UART_Parity + @note When parity is enabled, the computed parity is inserted + at the MSB position of the transmitted data (9th bit when + the word length is set to 9 data bits; 8th bit when the + word length is set to 8 data bits). */ + + uint32_t Mode; /*!< Specifies whether the Receive or Transmit mode is enabled or disabled. + This parameter can be a value of @ref UART_Mode. */ + + uint32_t HwFlowCtl; /*!< Specifies whether the hardware flow control mode is enabled + or disabled. + This parameter can be a value of @ref UART_Hardware_Flow_Control. */ + + uint32_t OverSampling; /*!< Specifies whether the Over sampling 8 is enabled or disabled, + to achieve higher speed (up to f_PCLK/8). + This parameter can be a value of @ref UART_Over_Sampling. */ + + uint32_t OneBitSampling; /*!< Specifies whether a single sample or three samples' majority vote is selected. + Selecting the single sample method increases the receiver tolerance to clock + deviations. This parameter can be a value of @ref UART_OneBit_Sampling. */ + + uint32_t ClockPrescaler; /*!< Specifies the prescaler value used to divide the UART clock source. + This parameter can be a value of @ref UART_ClockPrescaler. */ } UART_InitTypeDef; @@ -314,8 +312,9 @@ typedef enum /** * @brief HAL UART Callback pointer definition */ -typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ -typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ +typedef void (*pUART_CallbackTypeDef)(UART_HandleTypeDef *huart); /*!< pointer to an UART callback function */ +typedef void (*pUART_RxEventCallbackTypeDef) +(struct __UART_HandleTypeDef *huart, uint16_t Pos); /*!< pointer to a UART Rx Event specific callback function */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ @@ -355,16 +354,16 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart /** @defgroup UART_Error_Definition UART Error Definition * @{ */ -#define HAL_UART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_UART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_UART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_UART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_UART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_UART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_UART_ERROR_RTO ((uint32_t)0x00000020U) /*!< Receiver Timeout error */ +#define HAL_UART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_UART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_UART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_UART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_UART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_UART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_UART_ERROR_RTO (0x00000020U) /*!< Receiver Timeout error */ #if (USE_HAL_UART_REGISTER_CALLBACKS == 1) -#define HAL_UART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_UART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_UART_REGISTER_CALLBACKS */ /** * @} @@ -1229,7 +1228,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart /** @defgroup UART_Private_Macros UART Private Macros * @{ */ -/** @brief Get UART clok division factor from clock prescaler value. +/** @brief Get UART clock division factor from clock prescaler value. * @param __CLOCKPRESCALER__ UART prescaler value. * @retval UART clock division factor */ @@ -1244,8 +1243,7 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV16) ? 16U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV32) ? 32U : \ ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV64) ? 64U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : \ - ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV256) ? 256U : 1U) + ((__CLOCKPRESCALER__) == UART_PRESCALER_DIV128) ? 128U : 256U) /** @brief BRR division operation to set BRR register with LPUART. * @param __PCLK__ LPUART clock. @@ -1593,12 +1591,6 @@ typedef void (*pUART_RxEventCallbackTypeDef)(struct __UART_HandleTypeDef *huart /* Include UART HAL Extended module */ #include "stm32wlxx_hal_uart_ex.h" - -/* Prescaler Table used in BRR computation macros. - Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ -extern const uint16_t UARTPrescTable[12]; - - /* Exported functions --------------------------------------------------------*/ /** @addtogroup UART_Exported_Functions UART Exported Functions * @{ @@ -1720,6 +1712,17 @@ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart); HAL_StatusTypeDef UART_Start_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef UART_Start_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); +/** + * @} + */ + +/* Private variables -----------------------------------------------------------*/ +/** @defgroup UART_Private_variables UART Private variables + * @{ + */ +/* Prescaler Table used in BRR computation macros. + Declared as extern here to allow use of private UART macros, outside of HAL UART functions */ +extern const uint16_t UARTPrescTable[12]; /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h index c45cdef103..206becd77f 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_uart_ex.h @@ -98,12 +98,12 @@ typedef struct * @brief UART TXFIFO threshold level * @{ */ -#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TXFIFO reaches 1/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TXFIFO reaches 1/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TXFIFO reaches 1/2 of its depth */ -#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TXFIFO reaches 3/4 of its depth */ -#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TXFIFO reaches 7/8 of its depth */ -#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TXFIFO becomes empty */ +#define UART_TXFIFO_THRESHOLD_1_8 0x00000000U /*!< TX FIFO reaches 1/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_4 USART_CR3_TXFTCFG_0 /*!< TX FIFO reaches 1/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_1_2 USART_CR3_TXFTCFG_1 /*!< TX FIFO reaches 1/2 of its depth */ +#define UART_TXFIFO_THRESHOLD_3_4 (USART_CR3_TXFTCFG_0|USART_CR3_TXFTCFG_1) /*!< TX FIFO reaches 3/4 of its depth */ +#define UART_TXFIFO_THRESHOLD_7_8 USART_CR3_TXFTCFG_2 /*!< TX FIFO reaches 7/8 of its depth */ +#define UART_TXFIFO_THRESHOLD_8_8 (USART_CR3_TXFTCFG_2|USART_CR3_TXFTCFG_0) /*!< TX FIFO becomes empty */ /** * @} */ @@ -112,12 +112,12 @@ typedef struct * @brief UART RXFIFO threshold level * @{ */ -#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RXFIFO FIFO reaches 1/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RXFIFO FIFO reaches 1/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RXFIFO FIFO reaches 1/2 of its depth */ -#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RXFIFO FIFO reaches 3/4 of its depth */ -#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RXFIFO FIFO reaches 7/8 of its depth */ -#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RXFIFO FIFO becomes full */ +#define UART_RXFIFO_THRESHOLD_1_8 0x00000000U /*!< RX FIFO reaches 1/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_4 USART_CR3_RXFTCFG_0 /*!< RX FIFO reaches 1/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_1_2 USART_CR3_RXFTCFG_1 /*!< RX FIFO reaches 1/2 of its depth */ +#define UART_RXFIFO_THRESHOLD_3_4 (USART_CR3_RXFTCFG_0|USART_CR3_RXFTCFG_1) /*!< RX FIFO reaches 3/4 of its depth */ +#define UART_RXFIFO_THRESHOLD_7_8 USART_CR3_RXFTCFG_2 /*!< RX FIFO reaches 7/8 of its depth */ +#define UART_RXFIFO_THRESHOLD_8_8 (USART_CR3_RXFTCFG_2|USART_CR3_RXFTCFG_0) /*!< RX FIFO becomes full */ /** * @} */ @@ -173,11 +173,12 @@ HAL_StatusTypeDef HAL_UARTEx_DisableFifoMode(UART_HandleTypeDef *huart); HAL_StatusTypeDef HAL_UARTEx_SetTxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); HAL_StatusTypeDef HAL_UARTEx_SetRxFifoThreshold(UART_HandleTypeDef *huart, uint32_t Threshold); -HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, uint32_t Timeout); +HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint16_t *RxLen, + uint32_t Timeout); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); HAL_StatusTypeDef HAL_UARTEx_ReceiveToIdle_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size); -HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(UART_HandleTypeDef *huart); +HAL_UART_RxEventTypeTypeDef HAL_UARTEx_GetRxEventType(const UART_HandleTypeDef *huart); /** diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart.h index 1902c1128d..9f24a61390 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart.h @@ -47,11 +47,15 @@ typedef struct { uint32_t BaudRate; /*!< This member configures the Usart communication baud rate. The baud rate is computed using the following formula: - Baud Rate Register[15:4] = ((2 * fclk_pres) / ((huart->Init.BaudRate)))[15:4] + Baud Rate Register[15:4] = ((2 * fclk_pres) / + ((huart->Init.BaudRate)))[15:4] Baud Rate Register[3] = 0 - Baud Rate Register[2:0] = (((2 * fclk_pres) / ((huart->Init.BaudRate)))[3:0]) >> 1 - where fclk_pres is the USART input clock frequency (fclk) divided by a prescaler. - @note Oversampling by 8 is systematically applied to achieve high baud rates. */ + Baud Rate Register[2:0] = (((2 * fclk_pres) / + ((huart->Init.BaudRate)))[3:0]) >> 1 + where fclk_pres is the USART input clock frequency (fclk) + divided by a prescaler. + @note Oversampling by 8 is systematically applied to + achieve high baud rates. */ uint32_t WordLength; /*!< Specifies the number of data bits transmitted or received in a frame. This parameter can be a value of @ref USARTEx_Word_Length. */ @@ -138,13 +142,12 @@ typedef struct __USART_HandleTypeDef uint16_t NbTxDataToProcess; /*!< Number of data to process during TX ISR execution */ - uint32_t SlaveMode; /*!< Enable/Disable UART SPI Slave Mode. This parameter can be a value + uint32_t SlaveMode; /*!< Enable/Disable USART SPI Slave Mode. This parameter can be a value of @ref USARTEx_Slave_Mode */ uint32_t FifoMode; /*!< Specifies if the FIFO mode will be used. This parameter can be a value of @ref USARTEx_FIFO_mode. */ - void (*RxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Rx IRQ handler */ void (*TxISR)(struct __USART_HandleTypeDef *husart); /*!< Function pointer on Tx IRQ handler */ @@ -216,16 +219,17 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin /** @defgroup USART_Error_Definition USART Error Definition * @{ */ -#define HAL_USART_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */ -#define HAL_USART_ERROR_PE ((uint32_t)0x00000001U) /*!< Parity error */ -#define HAL_USART_ERROR_NE ((uint32_t)0x00000002U) /*!< Noise error */ -#define HAL_USART_ERROR_FE ((uint32_t)0x00000004U) /*!< Frame error */ -#define HAL_USART_ERROR_ORE ((uint32_t)0x00000008U) /*!< Overrun error */ -#define HAL_USART_ERROR_DMA ((uint32_t)0x00000010U) /*!< DMA transfer error */ -#define HAL_USART_ERROR_UDR ((uint32_t)0x00000020U) /*!< SPI slave underrun error */ +#define HAL_USART_ERROR_NONE (0x00000000U) /*!< No error */ +#define HAL_USART_ERROR_PE (0x00000001U) /*!< Parity error */ +#define HAL_USART_ERROR_NE (0x00000002U) /*!< Noise error */ +#define HAL_USART_ERROR_FE (0x00000004U) /*!< Frame error */ +#define HAL_USART_ERROR_ORE (0x00000008U) /*!< Overrun error */ +#define HAL_USART_ERROR_DMA (0x00000010U) /*!< DMA transfer error */ +#define HAL_USART_ERROR_UDR (0x00000020U) /*!< SPI slave underrun error */ #if (USE_HAL_USART_REGISTER_CALLBACKS == 1) -#define HAL_USART_ERROR_INVALID_CALLBACK ((uint32_t)0x00000040U) /*!< Invalid Callback error */ +#define HAL_USART_ERROR_INVALID_CALLBACK (0x00000040U) /*!< Invalid Callback error */ #endif /* USE_HAL_USART_REGISTER_CALLBACKS */ +#define HAL_USART_ERROR_RTO (0x00000080U) /*!< Receiver Timeout error */ /** * @} */ @@ -261,15 +265,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @} */ -/** @defgroup USART_Over_Sampling USART Over Sampling - * @{ - */ -#define USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#define USART_OVERSAMPLING_8 USART_CR1_OVER8 /*!< Oversampling by 8 */ -/** - * @} - */ - /** @defgroup USART_Clock USART Clock * @{ */ @@ -350,6 +345,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_FLAG_UDR USART_ISR_UDR /*!< SPI slave underrun error flag */ #define USART_FLAG_TXE USART_ISR_TXE_TXFNF /*!< USART transmit data register empty */ #define USART_FLAG_TXFNF USART_ISR_TXE_TXFNF /*!< USART TXFIFO not full */ +#define USART_FLAG_RTOF USART_ISR_RTOF /*!< USART receiver timeout flag */ #define USART_FLAG_TC USART_ISR_TC /*!< USART transmission complete */ #define USART_FLAG_RXNE USART_ISR_RXNE_RXFNE /*!< USART read data register not empty */ #define USART_FLAG_RXFNE USART_ISR_RXNE_RXFNE /*!< USART RXFIFO not empty */ @@ -404,6 +400,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin #define USART_CLEAR_TCF USART_ICR_TCCF /*!< Transmission Complete Clear Flag */ #define USART_CLEAR_UDRF USART_ICR_UDRCF /*!< SPI slave underrun error Clear Flag */ #define USART_CLEAR_TXFECF USART_ICR_TXFECF /*!< TXFIFO Empty Clear Flag */ +#define USART_CLEAR_RTOF USART_ICR_RTOCF /*!< USART receiver timeout clear flag */ /** * @} */ @@ -460,6 +457,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_FLAG_TC Transmission Complete flag * @arg @ref USART_FLAG_RXNE Receive data register not empty flag * @arg @ref USART_FLAG_RXFNE RXFIFO not empty flag + * @arg @ref USART_FLAG_RTOF Receiver Timeout flag * @arg @ref USART_FLAG_IDLE Idle Line detection flag * @arg @ref USART_FLAG_ORE OverRun Error flag * @arg @ref USART_FLAG_NE Noise Error flag @@ -480,6 +478,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver Timeout clear flag * @arg @ref USART_CLEAR_UDRF SPI slave underrun error Clear Flag * @retval None */ @@ -545,9 +544,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 |= ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) +#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Disable the specified USART interrupt. * @param __HANDLE__ specifies the USART Handle. @@ -567,10 +569,12 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_ERR Error interrupt(Frame error, noise error, overrun error) * @retval None */ -#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)? ((__HANDLE__)->Instance->CR1 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)? ((__HANDLE__)->Instance->CR2 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK))): \ - ((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & USART_IT_MASK)))) - +#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)\ + (((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 1U)?\ + ((__HANDLE__)->Instance->CR1 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((((__INTERRUPT__) & USART_CR_MASK) >> USART_CR_POS) == 2U)?\ + ((__HANDLE__)->Instance->CR2 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK))): \ + ((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & USART_IT_MASK)))) /** @brief Check whether the specified USART interrupt has occurred or not. * @param __HANDLE__ specifies the USART Handle. @@ -593,7 +597,8 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @retval The new state of __INTERRUPT__ (SET or RESET). */ #define __HAL_USART_GET_IT(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->ISR\ - & ((uint32_t)0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>> USART_ISR_POS))) != 0U) ? SET : RESET) + & (0x01U << (((__INTERRUPT__) & USART_ISR_MASK)>>\ + USART_ISR_POS))) != 0U) ? SET : RESET) /** @brief Check whether the specified USART interrupt source is enabled or not. * @param __HANDLE__ specifies the USART Handle. @@ -615,10 +620,13 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_IT_PE Parity Error interrupt * @retval The new state of __INTERRUPT__ (SET or RESET). */ -#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ? (__HANDLE__)->Instance->CR1 : \ - (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ? (__HANDLE__)->Instance->CR2 : \ - (__HANDLE__)->Instance->CR3)) & (0x01U << (((uint16_t)(__INTERRUPT__)) & USART_IT_MASK))) != 0U) ? SET : RESET) - +#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x01U) ?\ + (__HANDLE__)->Instance->CR1 : \ + (((((uint8_t)(__INTERRUPT__)) >> 0x05U) == 0x02U) ?\ + (__HANDLE__)->Instance->CR2 : \ + (__HANDLE__)->Instance->CR3)) & (0x01U <<\ + (((uint16_t)(__INTERRUPT__)) &\ + USART_IT_MASK))) != 0U) ? SET : RESET) /** @brief Clear the specified USART ISR flag, in setting the proper ICR register flag. * @param __HANDLE__ specifies the USART Handle. @@ -630,6 +638,7 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @arg @ref USART_CLEAR_NEF Noise detected Clear Flag * @arg @ref USART_CLEAR_OREF Overrun Error Clear Flag * @arg @ref USART_CLEAR_IDLEF IDLE line detected Clear Flag + * @arg @ref USART_CLEAR_RTOF Receiver timeout clear flag * @arg @ref USART_CLEAR_TXFECF TXFIFO empty clear Flag * @arg @ref USART_CLEAR_TCF Transmission Complete Clear Flag * @retval None @@ -704,8 +713,9 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin * @param __CLOCKPRESCALER__ USART prescaler value. * @retval Division result */ -#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__) (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ - + ((__BAUD__)/2U)) / (__BAUD__)) +#define USART_DIV_SAMPLING8(__PCLK__, __BAUD__, __CLOCKPRESCALER__)\ + (((((__PCLK__)/USART_GET_DIV_FACTOR(__CLOCKPRESCALER__))*2U)\ + + ((__BAUD__)/2U)) / (__BAUD__)) /** @brief Report the USART clock source. * @param __HANDLE__ specifies the USART Handle. @@ -801,14 +811,6 @@ typedef void (*pUSART_CallbackTypeDef)(USART_HandleTypeDef *husart); /*!< poin */ #define IS_USART_MODE(__MODE__) ((((__MODE__) & 0xFFFFFFF3U) == 0x00U) && ((__MODE__) != 0x00U)) -/** - * @brief Ensure that USART oversampling is valid. - * @param __SAMPLING__ USART oversampling. - * @retval SET (__SAMPLING__ is valid) or RESET (__SAMPLING__ is invalid) - */ -#define IS_USART_OVERSAMPLING(__SAMPLING__) (((__SAMPLING__) == USART_OVERSAMPLING_16) || \ - ((__SAMPLING__) == USART_OVERSAMPLING_8)) - /** * @brief Ensure that USART clock state is valid. * @param __CLOCK__ USART clock state. @@ -903,7 +905,8 @@ HAL_StatusTypeDef HAL_USART_UnRegisterCallback(USART_HandleTypeDef *husart, HAL_ */ /* IO operation functions *****************************************************/ -HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, uint32_t Timeout); +HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint16_t Size, + uint32_t Timeout); HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart_ex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart_ex.h index 64c04115e6..deea080fd1 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart_ex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_hal_usart_ex.h @@ -44,9 +44,9 @@ extern "C" { /** @defgroup USARTEx_Word_Length USARTEx Word Length * @{ */ -#define USART_WORDLENGTH_7B ((uint32_t)USART_CR1_M1) /*!< 7-bit long USART frame */ -#define USART_WORDLENGTH_8B 0x00000000U /*!< 8-bit long USART frame */ -#define USART_WORDLENGTH_9B ((uint32_t)USART_CR1_M0) /*!< 9-bit long USART frame */ +#define USART_WORDLENGTH_7B (USART_CR1_M1) /*!< 7-bit long USART frame */ +#define USART_WORDLENGTH_8B (0x00000000U) /*!< 8-bit long USART frame */ +#define USART_WORDLENGTH_9B (USART_CR1_M0) /*!< 9-bit long USART frame */ /** * @} */ @@ -108,9 +108,11 @@ extern "C" { /** * @} */ + /** * @} */ + /* Private macros ------------------------------------------------------------*/ /** @defgroup USARTEx_Private_Macros USARTEx Private Macros * @{ @@ -166,7 +168,6 @@ extern "C" { } \ } while(0U) - /** * @brief Ensure that USART frame length is valid. * @param __LENGTH__ USART frame length. @@ -256,6 +257,7 @@ HAL_StatusTypeDef HAL_USARTEx_EnableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_DisableFifoMode(USART_HandleTypeDef *husart); HAL_StatusTypeDef HAL_USARTEx_SetTxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); HAL_StatusTypeDef HAL_USARTEx_SetRxFifoThreshold(USART_HandleTypeDef *husart, uint32_t Threshold); + /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h index f7666badf2..8797096094 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_adc.h @@ -63,37 +63,35 @@ extern "C" { #define ADC_REG_RANK_8_SQRX_BITOFFSET_POS (28UL) /* Equivalent to bitfield "ADC_CHSELR_SQ8" position in register */ - /* Internal mask for ADC group regular trigger: */ /* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ /* - regular trigger source */ /* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for - compatibility with some ADC on other STM32 families - having this setting set by HW default value) */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for + compatibility with some ADC on other STM32 series + having this setting set by HW default value) */ /* Mask containing trigger source masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ - ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ - ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ - ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 1UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 2UL)) | \ + ((ADC_CFGR1_EXTSEL) << (4U * 3UL)) ) /* Mask containing trigger edge masks for each of possible */ /* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ /* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2UL)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3UL)) ) /* Definition of ADC group regular trigger bits information. */ #define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6UL) /* Equivalent to bitfield "ADC_CFGR1_EXTSEL" position in register */ #define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10UL) /* Equivalent to bitfield "ADC_CFGR1_EXTEN" position in register */ - /* Internal mask for ADC channel: */ /* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ /* - channel identifier defined by number */ @@ -177,7 +175,7 @@ extern "C" { /* Internal mask for ADC analog watchdog: */ /* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ /* (concatenation of multiple bits used in different analog watchdogs, */ -/* (feature of several watchdogs not available on all STM32 families)). */ +/* (feature of several watchdogs not available on all STM32 series)). */ /* - analog watchdog 1: monitored channel defined by number, */ /* selection of ADC group (ADC group regular). */ /* - analog watchdog 2 and 3: monitored channel defined by bitfield, no */ @@ -219,7 +217,6 @@ extern "C" { #define ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS (20UL) - /* ADC registers bits positions */ #define ADC_CFGR1_RES_BITOFFSET_POS ( 3UL) /* Equivalent to bitfield "ADC_CFGR1_RES" position in register */ #define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22UL) /* Equivalent to bitfield "ADC_CFGR1_AWDSGL" position in register */ @@ -251,29 +248,34 @@ extern "C" { /* ADC registers bits groups */ #define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADEN | ADC_CR_ADDIS \ | ADC_CR_ADSTART | ADC_CR_ADSTP) /* ADC register CR bits with - HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ + HW property "rs": Software can read as well as set this bit. + Writing '0' has no effect on the bit value. */ /* ADC internal channels related definitions */ /* Internal voltage reference VrefInt */ -#define VREFINT_CAL_ADDR ((uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, - address of parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), - Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define VREFINT_CAL_ADDR ((const uint16_t*) (0x1FFF75AAUL)) /* Internal voltage reference, address of + parameter VREFINT_CAL: VrefInt ADC raw data acquired at temperature 30 Deg + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define VREFINT_CAL_VREF ( 3300UL) /* Analog voltage reference (Vref+) value - with which VrefInt has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ + with which VrefInt has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ /* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On STM32WL, - temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V - (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1FFF75C8UL)) /* Address of parameter TS_CAL2: On STM32WL, - temperature sensor ADC raw data acquired at temperature 130 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V - (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_ADDR ((const uint16_t*) (0x1FFF75A8UL)) /* Address of parameter TS_CAL1: On + STM32WL, temperature sensor ADC raw data acquired at temperature 30 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((const uint16_t*) (0x1FFF75C8UL)) /* Address of parameter TS_CAL2: On + STM32WL, temperature sensor ADC raw data acquired at temperature 130 DegC + (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ #define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Temperature at which temperature sensor - has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ + has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL2_TEMP (( int32_t) 130) /* Temperature at which temperature sensor - has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ + has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR + (tolerance: +-5 DegC) (unit: DegC). */ #define TEMPSENSOR_CAL_VREFANALOG ( 3300UL) /* Analog voltage reference (Vref+) value - with which temperature sensor has been calibrated in production (tolerance: +-10 mV) (unit: mV). */ + with which temperature sensor has been calibrated in production + (tolerance: +-10 mV) (unit: mV). */ /** * @} @@ -335,7 +337,7 @@ typedef struct * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -384,7 +386,7 @@ typedef struct * is conditioned to ADC state: * ADC instance must be disabled. * This condition is applied to all ADC features, for efficiency - * and compatibility over all STM32 families. However, the different + * and compatibility over all STM32 series. However, the different * features can be set under different ADC state conditions * (setting possible with ADC enabled without conversion on going, * ADC enabled with conversion on going, ...) @@ -400,12 +402,12 @@ typedef struct This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE @note On this STM32 series, setting trigger source to external trigger also set trigger polarity to rising edge(default setting for compatibility - with some ADC on other STM32 families having this setting set by HW + with some ADC on other STM32 series having this setting set by HW default value). In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetTriggerSource(). */ + @ref LL_ADC_REG_SetTriggerSource(). */ uint32_t SequencerLength; /*!< Set ADC group regular sequencer length. @note This parameter has an effect only if group regular sequencer is set @@ -413,7 +415,7 @@ typedef struct @ref LL_ADC_REG_SetSequencerConfigurable(). This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_SCAN_LENGTH This feature can be modified afterwards using unitary function - @ref LL_ADC_REG_SetSequencerLength(). */ + @ref LL_ADC_REG_SetSequencerLength(). */ uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. @@ -465,8 +467,10 @@ typedef struct */ #define LL_ADC_FLAG_ADRDY ADC_ISR_ADRDY /*!< ADC flag ADC instance ready */ #define LL_ADC_FLAG_CCRDY ADC_ISR_CCRDY /*!< ADC flag ADC channel configuration ready */ -#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence conversions */ +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary + conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOS /*!< ADC flag ADC group regular end of sequence + conversions */ #define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ #define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ #define LL_ADC_FLAG_AWD1 ADC_ISR_AWD1 /*!< ADC flag ADC analog watchdog 1 */ @@ -483,10 +487,13 @@ typedef struct */ #define LL_ADC_IT_ADRDY ADC_IER_ADRDYIE /*!< ADC interruption ADC instance ready */ #define LL_ADC_IT_CCRDY ADC_IER_CCRDYIE /*!< ADC interruption channel configuration ready */ -#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ -#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence conversions */ +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary + conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSIE /*!< ADC interruption ADC group regular end of sequence + conversions */ #define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling + phase */ #define LL_ADC_IT_AWD1 ADC_IER_AWD1IE /*!< ADC interruption ADC analog watchdog 1 */ #define LL_ADC_IT_AWD2 ADC_IER_AWD2IE /*!< ADC interruption ADC analog watchdog 2 */ #define LL_ADC_IT_AWD3 ADC_IER_AWD3IE /*!< ADC interruption ADC analog watchdog 3 */ @@ -501,12 +508,11 @@ typedef struct /* List of ADC registers intended to be used (most commonly) with */ /* DMA transfer. */ /* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register - (corresponding to register DR) to be used with ADC - configured in independent mode. Without DMA transfer, - register accessed by LL function - @ref LL_ADC_REG_ReadConversionData32() and other - functions @ref LL_ADC_REG_ReadConversionDatax() */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000UL) /* ADC group regular conversion data register + (corresponding to register DR) to be used with ADC configured in independent + mode. Without DMA transfer, register accessed by LL function + @ref LL_ADC_REG_ReadConversionData32() and other + functions @ref LL_ADC_REG_ReadConversionDatax() */ /** * @} */ @@ -514,18 +520,54 @@ typedef struct /** @defgroup ADC_LL_EC_COMMON_CLOCK_SOURCE ADC common - Clock source * @{ */ -#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without prescaler */ -#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 2. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 4. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 6. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2 ) /*!< ADC asynchronous clock with prescaler division by 8. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 10. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 ) /*!< ADC asynchronous clock with prescaler division by 12. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 16. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with prescaler division by 32. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 64. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with prescaler division by 128. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ -#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with prescaler division by 256. ADC common clock asynchronous prescaler is applied to each ADC instance if the corresponding ADC instance clock is set to clock source asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV1 (0x00000000UL) /*!< ADC asynchronous clock without + prescaler */ +#define LL_ADC_CLOCK_ASYNC_DIV2 (ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 2. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV4 (ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 4. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV6 (ADC_CCR_PRESC_1 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 6. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV8 (ADC_CCR_PRESC_2) /*!< ADC asynchronous clock with + prescaler division by 8. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV10 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 10. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV12 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 12. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV16 (ADC_CCR_PRESC_2 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 16. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV32 (ADC_CCR_PRESC_3) /*!< ADC asynchronous clock with + prescaler division by 32. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV64 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 64. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV128 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1) /*!< ADC asynchronous clock with + prescaler division by 128. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ +#define LL_ADC_CLOCK_ASYNC_DIV256 (ADC_CCR_PRESC_3 | ADC_CCR_PRESC_1 \ + | ADC_CCR_PRESC_0) /*!< ADC asynchronous clock with + prescaler division by 256. Setting common to ADC instances of ADC common + group, applied ADC instance wise to each instance clock set to clock source + asynchronous (refer to function @ref LL_ADC_SetClock() ). */ /** * @} */ @@ -538,10 +580,11 @@ typedef struct /* If they are not listed below, they do not require any specific */ /* path enable. In this case, Access to measurement path is done */ /* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ -#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000UL) /*!< ADC measurement paths all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel + temperature sensor */ +#define LL_ADC_PATH_INTERNAL_VBAT (ADC_CCR_VBATEN) /*!< ADC measurement path to internal channel Vbat */ /** * @} */ @@ -549,10 +592,15 @@ typedef struct /** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source * @{ */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock divided by 4 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock divided by 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock not divided */ -#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 (ADC_CFGR2_CKMODE_1) /*!< ADC synchronous clock derived from AHB clock + divided by 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock + divided by 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (ADC_CFGR2_CKMODE_1 \ + | ADC_CFGR2_CKMODE_0) /*!< ADC synchronous clock derived from AHB clock + not divided */ +#define LL_ADC_CLOCK_ASYNC (0x00000000UL) /*!< ADC asynchronous clock. Asynchronous clock + prescaler can be configured using function @ref LL_ADC_SetCommonClock(). */ /** * @} */ @@ -571,8 +619,10 @@ typedef struct /** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment * @{ */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (alignment on data register MSB bit 15)*/ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000UL) /*!< ADC conversion data alignment: right aligned + (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned + (alignment on data register MSB bit 15)*/ /** * @} */ @@ -580,10 +630,18 @@ typedef struct /** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode * @{ */ -#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ -#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ -#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC automatically powers-off after a ADC conversion and automatically wakes up when a new ADC conversion is triggered (with startup time between trigger and start of sampling). See description with function @ref LL_ADC_SetLowPowerMode(). */ -#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_MODE_NONE (0x00000000UL) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power + mode, ADC conversions are performed only when necessary + (when previous ADC conversion data is read). + See description with function @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOPOWEROFF (ADC_CFGR1_AUTOFF) /*!< ADC low power mode auto power-off: the ADC + automatically powers-off after a ADC conversion and automatically wakes up + when a new ADC conversion is triggered (with startup time between trigger + and start of sampling). See description with function + @ref LL_ADC_SetLowPowerMode(). */ +#define LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF) /*!< ADC low power modes auto wait +and auto power-off combined. See description with function @ref LL_ADC_SetLowPowerMode(). */ /** * @} */ @@ -591,8 +649,18 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_FREQ ADC group regular - Trigger frequency mode * @{ */ -#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ -#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. Note: ADC trigger frequency mode must be set to low frequency when a duration is exceeded before ADC conversion start trigger event (between ADC enable and ADC conversion start trigger event or between two ADC conversion start trigger event). Duration value: Refer to device datasheet, parameter "tIdle". */ +#define LL_ADC_TRIGGER_FREQ_HIGH (0x00000000UL) /*!< ADC trigger frequency mode set to high frequency. + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ +#define LL_ADC_TRIGGER_FREQ_LOW (ADC_CFGR2_LFTRIG) /*!< ADC trigger frequency mode set to low frequency. + Note: ADC trigger frequency mode must be set to low frequency when a duration + is exceeded before ADC conversion start trigger event (between ADC enable + and ADC conversion start trigger event or between two ADC conversion start + trigger event). + Duration value: Refer to device datasheet, parameter "tIdle". */ /** * @} */ @@ -600,8 +668,11 @@ typedef struct /** @defgroup ADC_LL_EC_SAMPLINGTIME_COMMON ADC instance - Sampling time common to a group of channels * @{ */ -#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group of channels: sampling time nb 1 */ -#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group of channels: sampling time nb 2 */ +#define LL_ADC_SAMPLINGTIME_COMMON_1 (ADC_SMPR_SMP1_BITOFFSET_POS) /*!< Set sampling time common to a group + of channels: sampling time nb 1 */ +#define LL_ADC_SAMPLINGTIME_COMMON_2 (ADC_SMPR_SMP2_BITOFFSET_POS \ + | ADC_SAMPLING_TIME_CH_MASK) /*!< Set sampling time common to a group + of channels: sampling time nb 2 */ /** * @} */ @@ -609,7 +680,7 @@ typedef struct /** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups * @{ */ -#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ +#define LL_ADC_GROUP_REGULAR (0x00000001UL) /*!< ADC group regular (available on all STM32 devices) */ /** * @} */ @@ -617,28 +688,51 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number * @{ */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER | ADC_CHANNEL_10_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN10 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER | ADC_CHANNEL_13_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN13 */ -#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER | ADC_CHANNEL_14_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN14 */ -#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER | ADC_CHANNEL_15_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN15 */ -#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER | ADC_CHANNEL_16_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN16 */ -#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER | ADC_CHANNEL_17_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN17 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ -#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ -#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. */ -#define LL_ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to DAC channel 1. */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER \ + | ADC_CHANNEL_0_BITFIELD ) /*!< ADC channel ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER \ + | ADC_CHANNEL_1_BITFIELD ) /*!< ADC channel ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER \ + | ADC_CHANNEL_2_BITFIELD ) /*!< ADC channel ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER \ + | ADC_CHANNEL_3_BITFIELD ) /*!< ADC channel ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER \ + | ADC_CHANNEL_4_BITFIELD ) /*!< ADC channel ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER \ + | ADC_CHANNEL_5_BITFIELD ) /*!< ADC channel ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER \ + | ADC_CHANNEL_6_BITFIELD ) /*!< ADC channel ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER \ + | ADC_CHANNEL_7_BITFIELD ) /*!< ADC channel ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER \ + | ADC_CHANNEL_8_BITFIELD ) /*!< ADC channel ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER \ + | ADC_CHANNEL_9_BITFIELD ) /*!< ADC channel ADCx_IN9 */ +#define LL_ADC_CHANNEL_10 (ADC_CHANNEL_10_NUMBER \ + | ADC_CHANNEL_10_BITFIELD) /*!< ADC channel ADCx_IN10 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER \ + | ADC_CHANNEL_11_BITFIELD) /*!< ADC channel ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER \ + | ADC_CHANNEL_12_BITFIELD) /*!< ADC channel ADCx_IN12 */ +#define LL_ADC_CHANNEL_13 (ADC_CHANNEL_13_NUMBER \ + | ADC_CHANNEL_13_BITFIELD) /*!< ADC channel ADCx_IN13 */ +#define LL_ADC_CHANNEL_14 (ADC_CHANNEL_14_NUMBER \ + | ADC_CHANNEL_14_BITFIELD) /*!< ADC channel ADCx_IN14 */ +#define LL_ADC_CHANNEL_15 (ADC_CHANNEL_15_NUMBER \ + | ADC_CHANNEL_15_BITFIELD) /*!< ADC channel ADCx_IN15 */ +#define LL_ADC_CHANNEL_16 (ADC_CHANNEL_16_NUMBER \ + | ADC_CHANNEL_16_BITFIELD) /*!< ADC channel ADCx_IN16 */ +#define LL_ADC_CHANNEL_17 (ADC_CHANNEL_17_NUMBER \ + | ADC_CHANNEL_17_BITFIELD) /*!< ADC channel ADCx_IN17 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_13 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to internal temperature sensor. */ +#define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_14 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 + to have channel voltage always below Vdda. */ +#define LL_ADC_CHANNEL_DACCH1 (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel + connected to DAC channel 1. */ /** * @} */ @@ -646,13 +740,32 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source * @{ */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO ( ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 ( ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: TIM2 channel 3 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external peripheral: external interrupt line 11. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000UL) /*!< ADC group regular + conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO2 (ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 (ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM1 channel 4 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 TRGO. + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH4 (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 channel 4 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM2_CH3 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_0 \ + | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: TIM2 channel 3 event + (capture compare: input capture or output capture). + Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_EXTI_LINE11 (ADC_CFGR1_EXTSEL_2 | ADC_CFGR1_EXTSEL_1 \ + | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular + conversion trigger from external peripheral: external interrupt line 11. + Trigger edge set to rising edge (default setting). */ /** * @} */ @@ -660,9 +773,12 @@ typedef struct /** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge * @{ */ -#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +#define LL_ADC_REG_TRIG_EXT_RISING (ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1) /*!< ADC group regular conversion + trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion + trigger polarity set to both rising and falling edges */ /** * @} */ @@ -670,8 +786,11 @@ typedef struct /** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode * @{ */ -#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions are performed in single mode: one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +#define LL_ADC_REG_CONV_SINGLE (0x00000000UL) /*!< ADC conversions performed in single mode: + one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions performed in continuous mode: + after the first trigger, following conversions launched successively + automatically */ /** * @} */ @@ -679,9 +798,15 @@ typedef struct /** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data * @{ */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000UL) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED (ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, + in limited mode (one shot mode): DMA transfer requests are stopped when + number of DMA data transfers (number of ADC conversions) is reached. + This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are + transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, + whatever number of DMA data transferred (number of ADC conversions). + This ADC mode is intended to be used with DMA mode circular. */ /** * @} */ @@ -689,8 +814,10 @@ typedef struct /** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data * @{ */ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000UL) /*!< ADC group regular behavior in case of overrun: + data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: + data overwritten */ /** * @} */ @@ -698,8 +825,13 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_MODE ADC group regular - Sequencer configuration flexibility * @{ */ -#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: sequencer length and each rank affectation to a channel are fixed by channel HW number. Refer to description of function @ref LL_ADC_REG_SetSequencerChannels(). */ -#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: sequencer length and each rank affectation to a channel are configurable. Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ +#define LL_ADC_REG_SEQ_FIXED (0x00000000UL) /*!< Sequencer configured to not fully configurable: + sequencer length and each rank affectation to a channel are fixed + by channel HW number. Refer to description of function + @ref LL_ADC_REG_SetSequencerChannels(). */ +#define LL_ADC_REG_SEQ_CONFIGURABLE (ADC_CFGR1_CHSELRMOD) /*!< Sequencer configured to fully configurable: + sequencer length and each rank affectation to a channel are configurable. + Refer to description of function @ref LL_ADC_REG_SetSequencerLength(). */ /** * @} */ @@ -707,14 +839,22 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_LENGTH ADC group regular - Sequencer scan length * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable with 2 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable with 3 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable with 4 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable with 5 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable with 6 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable with 7 ranks in the sequence */ -#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable with 8 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_DISABLE (ADC_CHSELR_SQ2) /*!< ADC group regular sequencer disable + (equivalent to sequencer of 1 rank: ADC conversion on only 1 channel) */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS (ADC_CHSELR_SQ3) /*!< ADC group regular sequencer enable + with 2 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS (ADC_CHSELR_SQ4) /*!< ADC group regular sequencer enable + with 3 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS (ADC_CHSELR_SQ5) /*!< ADC group regular sequencer enable + with 4 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS (ADC_CHSELR_SQ6) /*!< ADC group regular sequencer enable + with 5 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS (ADC_CHSELR_SQ7) /*!< ADC group regular sequencer enable + with 6 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS (ADC_CHSELR_SQ8) /*!< ADC group regular sequencer enable + with 7 ranks in the sequence */ +#define LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS (0x00000000UL) /*!< ADC group regular sequencer enable + with 8 ranks in the sequence */ /** * @} */ @@ -722,8 +862,19 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction * @{ */ -#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other STM32 families, this setting is not available and the default scan direction is forward. */ -#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only is sequencer set to mode not fully configurable, refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000UL) /*!< On this STM32 series, parameter relevant only if + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction forward: from lowest channel number to highest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer). On some other STM32 series, this setting is not available + and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< On this STM32 series, parameter relevant only if + sequencer set to mode not fully configurable, refer to function + @ref LL_ADC_REG_SetSequencerConfigurable(). ADC group regular sequencer scan + direction backward: from highest channel number to lowest channel number + (scan of all ranks, ADC conversion of ranks with channels enabled in + sequencer) */ /** * @} */ @@ -731,8 +882,10 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode * @{ */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000UL) /*!< ADC group regular sequencer + discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer + discontinuous mode enable with sequence interruption every rank */ /** * @} */ @@ -740,14 +893,14 @@ typedef struct /** @defgroup ADC_LL_EC_REG_SEQ_RANKS ADC group regular - Sequencer ranks * @{ */ -#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 1 */ -#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 2 */ -#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 3 */ -#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 4 */ -#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 5 */ -#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 6 */ -#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 7 */ -#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular sequencer rank 8 */ +#define LL_ADC_REG_RANK_1 (ADC_REG_RANK_1_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 1 */ +#define LL_ADC_REG_RANK_2 (ADC_REG_RANK_2_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 2 */ +#define LL_ADC_REG_RANK_3 (ADC_REG_RANK_3_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 3 */ +#define LL_ADC_REG_RANK_4 (ADC_REG_RANK_4_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 4 */ +#define LL_ADC_REG_RANK_5 (ADC_REG_RANK_5_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 5 */ +#define LL_ADC_REG_RANK_6 (ADC_REG_RANK_6_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 6 */ +#define LL_ADC_REG_RANK_7 (ADC_REG_RANK_7_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 7 */ +#define LL_ADC_REG_RANK_8 (ADC_REG_RANK_8_SQRX_BITOFFSET_POS) /*!< ADC group regular seq. rank 8 */ /** * @} */ @@ -755,14 +908,19 @@ typedef struct /** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time * @{ */ -#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ -#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 | ADC_SMPR_SMP1_1 | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_1CYCLE_5 (0x00000000UL) /*!< Sampling time 1.5 ADC clock cycle */ +#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (ADC_SMPR_SMP1_0) /*!< Sampling time 3.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 (ADC_SMPR_SMP1_1) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_12CYCLES_5 (ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 12.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_19CYCLES_5 (ADC_SMPR_SMP1_2) /*!< Sampling time 19.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_39CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 39.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_79CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_1) /*!< Sampling time 79.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_160CYCLES_5 (ADC_SMPR_SMP1_2 \ + | ADC_SMPR_SMP1_1 \ + | ADC_SMPR_SMP1_0) /*!< Sampling time 160.5 ADC clock cycles */ /** * @} */ @@ -770,9 +928,12 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number * @{ */ -#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ -#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ +#define LL_ADC_AWD1 (ADC_AWD_CR1_CHANNEL_MASK \ + | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +#define LL_ADC_AWD2 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR2_REGOFFSET) /*!< ADC analog watchdog number 2 */ +#define LL_ADC_AWD3 (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_AWD_CR3_REGOFFSET) /*!< ADC analog watchdog number 3 */ /** * @} */ @@ -780,30 +941,82 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels * @{ */ -#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK | ADC_CFGR1_AWD1EN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN10, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN13, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN14, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN15, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN16, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN17, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ -#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ -#define LL_ADC_AWD_CH_DACCH1_REG ((LL_ADC_CHANNEL_DACCH1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to DAC channel 1, converted by group regular only */ +#define LL_ADC_AWD_DISABLE (0x00000000UL) /*!< ADC analog watchdog monitoring + disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG (ADC_AWD_CR23_CHANNEL_MASK \ + | ADC_CFGR1_AWD1EN) /*!< ADC analog watchdog monitoring + of all channels, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_10_REG ((LL_ADC_CHANNEL_10 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN10, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_13_REG ((LL_ADC_CHANNEL_13 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN13, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_14_REG ((LL_ADC_CHANNEL_14 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN14, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_15_REG ((LL_ADC_CHANNEL_15 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN15, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_16_REG ((LL_ADC_CHANNEL_16 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN16, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_17_REG ((LL_ADC_CHANNEL_17 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC channel ADCx_IN17, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to VrefInt: Internal + voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to internal temperature sensor, + converted by group regular only */ +#define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to Vbat/3: Vbat + voltage through a divider ladder of factor 1/3 to have channel voltage always + below Vdda, converted by group regular only */ +#define LL_ADC_AWD_CH_DACCH1_REG ((LL_ADC_CHANNEL_DACCH1 & ADC_CHANNEL_ID_MASK) \ + | ADC_CFGR1_AWD1EN | ADC_CFGR1_AWD1SGL) /*!< ADC analog watchdog monitoring + of ADC internal channel connected to DAC channel 1, + converted by group regular only */ /** * @} */ @@ -811,9 +1024,11 @@ typedef struct /** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds * @{ */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1 ) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ -#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_AWD1TR_HT1) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW (ADC_AWD1TR_LT1) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_AWD1TR_HT1 \ + | ADC_AWD1TR_LT1) /*!< ADC analog watchdog both thresholds high and low + concatenated into the same data */ /** * @} */ @@ -821,8 +1036,11 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_SCOPE Oversampling - Oversampling scope * @{ */ -#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ -#define LL_ADC_OVS_GRP_REGULAR_CONTINUED ( ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of ADC group regular. Literal suffix "continued" is kept for compatibility with other STM32 devices featuring ADC group injected, in this case other oversampling scope parameters are available. */ +#define LL_ADC_OVS_DISABLE (0x00000000UL) /*!< ADC oversampling disabled. */ +#define LL_ADC_OVS_GRP_REGULAR_CONTINUED (ADC_CFGR2_OVSE) /*!< ADC oversampling on conversions of + ADC group regular. Literal suffix "continued" is kept for compatibility + with other STM32 devices featuring ADC group injected, in this case other + oversampling scope parameters are available. */ /** * @} */ @@ -830,8 +1048,10 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_DISCONT_MODE Oversampling - Discontinuous mode * @{ */ -#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode (all conversions of oversampling ratio are done from 1 trigger) */ -#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous mode (each conversion of oversampling ratio needs a trigger) */ +#define LL_ADC_OVS_REG_CONT (0x00000000UL) /*!< ADC oversampling discontinuous mode: continuous mode +(all conversions of oversampling ratio are done from 1 trigger) */ +#define LL_ADC_OVS_REG_DISCONT (ADC_CFGR2_TOVS) /*!< ADC oversampling discontinuous mode: discontinuous + mode (each conversion of oversampling ratio needs a trigger) */ /** * @} */ @@ -839,30 +1059,66 @@ typedef struct /** @defgroup ADC_LL_EC_OVS_RATIO Oversampling - Ratio * @{ */ -#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 (2 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_4 ( ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 (4 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_8 ( ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 8 (8 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_16 ( ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 (16 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2 ) /*!< ADC oversampling ratio of 32 (32 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 (64 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 ) /*!< ADC oversampling ratio of 128 (128 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ -#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 (256 ADC conversions are performed, sum of these conversions data is computed to result as the ADC oversampling conversion data (before potential shift) */ +#define LL_ADC_OVS_RATIO_2 (0x00000000UL) /*!< ADC oversampling ratio of 2 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_4 (ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 4 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_8 (ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 8 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_16 (ADC_CFGR2_OVSR_1 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 16 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_32 (ADC_CFGR2_OVSR_2) /*!< ADC oversampling ratio of 32 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_64 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 64 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_128 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1) /*!< ADC oversampling ratio of 128 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ +#define LL_ADC_OVS_RATIO_256 (ADC_CFGR2_OVSR_2 | ADC_CFGR2_OVSR_1 \ + | ADC_CFGR2_OVSR_0) /*!< ADC oversampling ratio of 256 + (sum of conversions data computed to result as oversampling conversion data + (before potential shift) */ /** * @} */ -/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data shift +/** @defgroup ADC_LL_EC_OVS_SHIFT Oversampling - Data right shift * @{ */ -#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift (sum of the ADC conversions data is not divided to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_1 ( ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 1 (sum of the ADC conversions data is divided by 2 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_2 ( ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 2 (sum of the ADC conversions data is divided by 4 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_3 ( ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 3 (sum of the ADC conversions data is divided by 8 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_4 ( ADC_CFGR2_OVSS_2 ) /*!< ADC oversampling shift of 4 (sum of the ADC conversions data is divided by 16 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_5 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 5 (sum of the ADC conversions data is divided by 32 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_6 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 ) /*!< ADC oversampling shift of 6 (sum of the ADC conversions data is divided by 64 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_7 ( ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling shift of 7 (sum of the ADC conversions data is divided by 128 to result as the ADC oversampling conversion data) */ -#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3 ) /*!< ADC oversampling shift of 8 (sum of the ADC conversions data is divided by 256 to result as the ADC oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_NONE (0x00000000UL) /*!< ADC oversampling no shift + (sum of the ADC conversions data is not divided to result as oversampling + conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_1 (ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 1 + (sum of the ADC conversions data (after OVS ratio) is divided by 2 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_2 (ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 2 + (sum of the ADC conversions data (after OVS ratio) is divided by 4 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_3 (ADC_CFGR2_OVSS_1 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 3 + (sum of the ADC conversions data (after OVS ratio) is divided by 8 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_4 (ADC_CFGR2_OVSS_2) /*!< ADC oversampling right shift of 4 + (sum of the ADC conversions data (after OVS ratio) is divided by 16 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_5 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 5 + (sum of the ADC conversions data (after OVS ratio) is divided by 32 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_6 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1) /*!< ADC oversampling right shift of 6 + (sum of the ADC conversions data (after OVS ratio) is divided by 64 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_7 (ADC_CFGR2_OVSS_2 | ADC_CFGR2_OVSS_1 \ + | ADC_CFGR2_OVSS_0) /*!< ADC oversampling right shift of 7 + (sum of the ADC conversions data (after OVS ratio) is divided by 128 + to result as oversampling conversion data) */ +#define LL_ADC_OVS_SHIFT_RIGHT_8 (ADC_CFGR2_OVSS_3) /*!< ADC oversampling right shift of 8 + (sum of the ADC conversions data (after OVS ratio) is divided by 256 + to result as oversampling conversion data) */ /** * @} */ @@ -909,20 +1165,26 @@ typedef struct /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tADCVREG_STUP"). */ /* Unit: us */ -#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage regulator start-up time) */ +#define LL_ADC_DELAY_INTERNAL_REGUL_STAB_US ( 20UL) /*!< Delay for ADC stabilization time (ADC voltage + regulator start-up time) */ /* Delay for internal voltage reference stabilization time. */ /* Delay set to maximum value (refer to device datasheet, */ /* parameter "tstart_vrefint"). */ /* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization time */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 12UL) /*!< Delay for internal voltage reference stabilization + time */ /* Delay for temperature sensor stabilization time. */ /* Literal set to maximum value (refer to device datasheet, */ /* parameter "tSTART"). */ /* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time (starting from temperature sensor enable, refer to @ref LL_ADC_SetCommonPathInternalCh()) */ -#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization time (starting from ADC enable, refer to @ref LL_ADC_Enable()) */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US (120UL) /*!< Delay for temperature sensor stabilization time + (starting from temperature sensor enable, refer to + @ref LL_ADC_SetCommonPathInternalCh()) */ +#define LL_ADC_DELAY_TEMPSENSOR_BUFFER_STAB_US ( 15UL) /*!< Delay for temperature sensor buffer stabilization + time (starting from ADC enable, refer to + @ref LL_ADC_Enable()) */ /* Delay required between ADC end of calibration and ADC enable. */ /* Note: On this STM32 series, a minimum number of ADC clock cycles */ @@ -931,7 +1193,8 @@ typedef struct /* equivalent number of CPU cycles, by taking into account */ /* ratio of CPU clock versus ADC clock prescalers. */ /* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration and ADC enable */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 2UL) /*!< Delay required between ADC end of calibration + and ADC enable */ /** * @} @@ -1547,19 +1810,19 @@ typedef struct #define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ __TEMPSENSOR_ADC_DATA__,\ __ADC_RESOLUTION__)\ -((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) \ - : \ - ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ +((((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) != 0) ? \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) \ + : \ + ((int32_t)LL_ADC_TEMPERATURE_CALC_ERROR) \ ) /** @@ -1598,7 +1861,7 @@ typedef struct (at temperature and Vref+ defined in parameters below) (unit: mV). * On STM32WL, refer to datasheet parameter "V30" (corresponding to TS_CAL1). * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage - (see parameter above) is corresponding (unit: mV) + (see parameter above) is corresponding (unit: degree Celsius) * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) value (unit: mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. @@ -1672,7 +1935,7 @@ typedef struct * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA * @retval ADC register address */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(const ADC_TypeDef *ADCx, uint32_t Register) { /* Prevent unused argument(s) compilation warning */ (void)(Register); @@ -1750,7 +2013,7 @@ __STATIC_INLINE void LL_ADC_SetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON, uin * is set to clock source asynchronous. * (refer to function @ref LL_ADC_SetClock() ). */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonClock(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_PRESC)); } @@ -1887,7 +2150,7 @@ __STATIC_INLINE void LL_ADC_SetCommonPathInternalChRem(ADC_Common_TypeDef *ADCxy * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR * @arg @ref LL_ADC_PATH_INTERNAL_VBAT */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(const ADC_Common_TypeDef *ADCxy_COMMON) { return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN | ADC_CCR_VBATEN)); } @@ -1947,7 +2210,7 @@ __STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) * cycle). * Refer to reference manual. */ -__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetClock(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); } @@ -1983,7 +2246,7 @@ __STATIC_INLINE void LL_ADC_SetCalibrationFactor(ADC_TypeDef *ADCx, uint32_t Cal * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x7F */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationFactor(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT)); } @@ -2021,7 +2284,7 @@ __STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution * @arg @ref LL_ADC_RESOLUTION_8B * @arg @ref LL_ADC_RESOLUTION_6B */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetResolution(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RES)); } @@ -2055,7 +2318,7 @@ __STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAli * @arg @ref LL_ADC_DATA_ALIGN_RIGHT * @arg @ref LL_ADC_DATA_ALIGN_LEFT */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); } @@ -2165,7 +2428,7 @@ __STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPower * @arg @ref LL_ADC_LP_AUTOPOWEROFF * @arg @ref LL_ADC_LP_AUTOWAIT_AUTOPOWEROFF */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT | ADC_CFGR1_AUTOFF))); } @@ -2208,7 +2471,7 @@ __STATIC_INLINE void LL_ADC_SetTriggerFrequencyMode(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_TRIGGER_FREQ_HIGH * @arg @ref LL_ADC_TRIGGER_FREQ_LOW */ -__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_LFTRIG)); } @@ -2218,7 +2481,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetTriggerFrequencyMode(ADC_TypeDef *ADCx) * @note Unit: ADC clock cycles. * @note On this STM32 series, sampling time scope is on ADC instance: * Sampling time common to all channels. - * (on some other STM32 families, sampling time is channel wise) + * (on some other STM32 series, sampling time is channel wise) * @note In case of internal channel (VrefInt, TempSensor, ...) to be * converted: * sampling time constraints must be respected (sampling time can be @@ -2270,7 +2533,7 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @note Unit: ADC clock cycles. * @note On this STM32 series, sampling time scope is on ADC instance: * Sampling time common to all channels. - * (on some other STM32 families, sampling time is channel wise) + * (on some other STM32 series, sampling time is channel wise) * @note Conversion time is the addition of sampling time and processing time. * Refer to reference manual for ADC processing time of * this STM32 series. @@ -2290,7 +2553,7 @@ __STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_SAMPLINGTIME_79CYCLES_5 * @arg @ref LL_ADC_SAMPLINGTIME_160CYCLES_5 */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTimeY) +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(const ADC_TypeDef *ADCx, uint32_t SamplingTimeY) { return (uint32_t)((READ_BIT(ADCx->SMPR, ADC_SMPR_SMP1 << (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK))) >> (SamplingTimeY & ADC_SAMPLING_TIME_SMP_SHIFT_MASK)); @@ -2311,7 +2574,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, * @note On this STM32 series, setting trigger source to external trigger * also set trigger polarity to rising edge * (default setting for compatibility with some ADC on other - * STM32 families having this setting set by HW default value). + * STM32 series having this setting set by HW default value). * In case of need to modify trigger edge, use * function @ref LL_ADC_REG_SetTriggerEdge(). * @note On this STM32 series, ADC trigger frequency mode must be set @@ -2365,7 +2628,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t Tri * @arg @ref LL_ADC_REG_TRIG_EXT_TIM2_CH4 * @arg @ref LL_ADC_REG_TRIG_EXT_EXTI_LINE11 */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(const ADC_TypeDef *ADCx) { __IO uint32_t trigger_source = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); @@ -2392,7 +2655,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) * @retval Value "0" if trigger source external trigger * Value "1" if trigger source SW start. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)) ? 1UL : 0UL); } @@ -2426,7 +2689,7 @@ __STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t Exter * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); } @@ -2489,7 +2752,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerConfigurable(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_REG_SEQ_FIXED * @arg @ref LL_ADC_REG_SEQ_CONFIGURABLE */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerConfigurable(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CHSELRMOD)); } @@ -2620,7 +2883,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerLength(ADC_TypeDef *ADCx, uint32_t S * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS * @arg @ref LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerLength(const ADC_TypeDef *ADCx) { __IO uint32_t channels_ranks = READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ_ALL); uint32_t sequencer_length = LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS; @@ -2679,7 +2942,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uin * @note On this STM32 series, parameter relevant only is sequencer is set * to mode not fully configurable, * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). - * @note On some other STM32 families, this setting is not available and + * @note On some other STM32 series, this setting is not available and * the default scan direction is forward. * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection * @param ADCx ADC instance @@ -2687,7 +2950,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uin * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); } @@ -2723,7 +2986,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); } @@ -2812,7 +3075,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra MODIFY_REG(ADCx->CHSELR, ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK), ((Channel & ADC_CHANNEL_ID_NUMBER_MASK_SEQ) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) - << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); + << (Rank & ADC_REG_RANK_ID_SQRX_MASK)); } /** @@ -2884,7 +3147,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Ra * comparison with internal channel parameter to be done * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(ADC_TypeDef *ADCx, uint32_t Rank) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerRanks(const ADC_TypeDef *ADCx, uint32_t Rank) { return (uint32_t)((READ_BIT(ADCx->CHSELR, ADC_CHSELR_SQ1 << (Rank & ADC_REG_RANK_ID_SQRX_MASK)) @@ -3243,7 +3506,7 @@ __STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Ch * only if sequencer is set in mode "not fully configurable", * refer to function @ref LL_ADC_REG_SetSequencerConfigurable(). */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(const ADC_TypeDef *ADCx) { uint32_t channels_bitfield = (uint32_t)READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); @@ -3303,7 +3566,7 @@ __STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Co * @arg @ref LL_ADC_REG_CONV_SINGLE * @arg @ref LL_ADC_REG_CONV_CONTINUOUS */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); } @@ -3373,7 +3636,7 @@ __STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATr * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); } @@ -3411,7 +3674,7 @@ __STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); } @@ -3568,7 +3831,7 @@ __STATIC_INLINE void LL_ADC_SetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t C * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_1 * @arg @ref LL_ADC_SAMPLINGTIME_COMMON_2 */ -__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(ADC_TypeDef *ADCx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_ADC_GetChannelSamplingTime(const ADC_TypeDef *ADCx, uint32_t Channel) { __IO uint32_t smpr = READ_REG(ADCx->SMPR); @@ -3761,12 +4024,12 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t * @arg @ref LL_ADC_AWD_CHANNEL_16_REG * @arg @ref LL_ADC_AWD_CHANNEL_17_REG */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDy) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(const ADC_TypeDef *ADCx, uint32_t AWDy) { - __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, - ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) - + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) - * ADC_AWD_CR12_REGOFFSETGAP_VAL)); + __IO const uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->CFGR1, + ((AWDy & ADC_AWD_CRX_REGOFFSET_MASK) >> ADC_AWD_CRX_REGOFFSET_POS) + + ((AWDy & ADC_AWD_CR12_REGOFFSETGAP_MASK) + * ADC_AWD_CR12_REGOFFSETGAP_VAL)); uint32_t analog_wd_monit_channels = (READ_BIT(*preg, AWDy) & AWDy & ADC_AWD_CR_ALL_CHANNEL_MASK); @@ -3890,10 +4153,10 @@ __STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) - ); + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL)) + ); MODIFY_REG(*preg, ADC_AWD1TR_HT1 | ADC_AWD1TR_LT1, @@ -3973,9 +4236,9 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW /* containing other bits reserved for other purpose. */ __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); MODIFY_REG(*preg, AWDThresholdsHighLow, @@ -4010,7 +4273,8 @@ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AW * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDy, uint32_t AWDThresholdsHighLow) +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(const ADC_TypeDef *ADCx, + uint32_t AWDy, uint32_t AWDThresholdsHighLow) { /* Set bits with content of parameter "AWDThresholdValue" with bits */ /* position in register and register position depending on parameters */ @@ -4019,9 +4283,9 @@ __STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_ /* containing other bits reserved for other purpose. */ const __IO uint32_t *preg = __ADC_PTR_REG_OFFSET(ADCx->AWD1TR, (((AWDy & ADC_AWD_TRX_REGOFFSET_MASK)) - >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + >> (ADC_AWD_TRX_REGOFFSET_BITOFFSET_POS)) + ((ADC_AWD_CR3_REGOFFSET & AWDy) - >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); + >> (ADC_AWD_CRX_REGOFFSET_BITOFFSET_POS + 1UL))); return (uint32_t)(READ_BIT(*preg, (AWDThresholdsHighLow | ADC_AWD1TR_LT1)) @@ -4062,7 +4326,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingScope(ADC_TypeDef *ADCx, uint32_t Ovs * @arg @ref LL_ADC_OVS_DISABLE * @arg @ref LL_ADC_OVS_GRP_REGULAR_CONTINUED */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingScope(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSE)); } @@ -4104,7 +4368,7 @@ __STATIC_INLINE void LL_ADC_SetOverSamplingDiscont(ADC_TypeDef *ADCx, uint32_t O * @arg @ref LL_ADC_OVS_REG_CONT * @arg @ref LL_ADC_OVS_REG_DISCONT */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingDiscont(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_TOVS)); } @@ -4160,7 +4424,7 @@ __STATIC_INLINE void LL_ADC_ConfigOverSamplingRatioShift(ADC_TypeDef *ADCx, uint * @arg @ref LL_ADC_OVS_RATIO_128 * @arg @ref LL_ADC_OVS_RATIO_256 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSR)); } @@ -4180,7 +4444,7 @@ __STATIC_INLINE uint32_t LL_ADC_GetOverSamplingRatio(ADC_TypeDef *ADCx) * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_7 * @arg @ref LL_ADC_OVS_SHIFT_RIGHT_8 */ -__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_GetOverSamplingShift(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_OVSS)); } @@ -4245,7 +4509,7 @@ __STATIC_INLINE void LL_ADC_DisableInternalRegulator(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: internal regulator is disabled, 1: internal regulator is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsInternalRegulatorEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADVREGEN) == (ADC_CR_ADVREGEN)) ? 1UL : 0UL); } @@ -4305,7 +4569,7 @@ __STATIC_INLINE void LL_ADC_Disable(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: ADC is disabled, 1: ADC is enabled. */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)) ? 1UL : 0UL); } @@ -4316,7 +4580,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no ADC disable command on going. */ -__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsDisableOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADDIS) == (ADC_CR_ADDIS)) ? 1UL : 0UL); } @@ -4365,7 +4629,7 @@ __STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: calibration complete, 1: calibration in progress. */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)) ? 1UL : 0UL); } @@ -4410,7 +4674,7 @@ __STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) * @brief Stop ADC group regular conversion. * @note On this STM32 series, setting of this feature is conditioned to * ADC state: - * ADC must be enabled with conversion on going on group regular, + * ADC must be enabled (potentially with conversion on going on group regular), * without ADC disable command on going. * @rmtoll CR ADSTP LL_ADC_REG_StopConversion * @param ADCx ADC instance @@ -4432,7 +4696,7 @@ __STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no conversion is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)) ? 1UL : 0UL); } @@ -4443,7 +4707,7 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval 0: no command of conversion stop is on going on ADC group regular. */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)) ? 1UL : 0UL); } @@ -4451,13 +4715,12 @@ __STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) /** * @brief Get ADC group regular conversion data, range fit for * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). + * features extending data width (oversampling, data shift,...). * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 * @param ADCx ADC instance * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(const ADC_TypeDef *ADCx) { return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); } @@ -4472,9 +4735,9 @@ __STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0xFFF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(const ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x00000FFFUL); } /** @@ -4487,9 +4750,9 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x000 and Max_Data=0x3FF */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(const ADC_TypeDef *ADCx) { - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000003FFUL); } /** @@ -4502,9 +4765,9 @@ __STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0xFF */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(const ADC_TypeDef *ADCx) { - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x000000FFUL); } /** @@ -4517,9 +4780,9 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval Value between Min_Data=0x00 and Max_Data=0x3F */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(const ADC_TypeDef *ADCx) { - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA) & 0x0000003FUL); } /** @@ -4539,7 +4802,7 @@ __STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_ADRDY) == (LL_ADC_FLAG_ADRDY)) ? 1UL : 0UL); } @@ -4566,7 +4829,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); } @@ -4577,7 +4840,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_CCRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)) ? 1UL : 0UL); } @@ -4588,7 +4851,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)) ? 1UL : 0UL); } @@ -4599,7 +4862,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)) ? 1UL : 0UL); } @@ -4610,7 +4873,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)) ? 1UL : 0UL); } @@ -4621,7 +4884,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD1) == (LL_ADC_FLAG_AWD1)) ? 1UL : 0UL); } @@ -4632,7 +4895,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD2) == (LL_ADC_FLAG_AWD2)) ? 1UL : 0UL); } @@ -4643,7 +4906,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD3) == (LL_ADC_FLAG_AWD3)) ? 1UL : 0UL); } @@ -4654,7 +4917,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOCAL) == (LL_ADC_FLAG_EOCAL)) ? 1UL : 0UL); } @@ -5007,7 +5270,7 @@ __STATIC_INLINE void LL_ADC_DisableIT_EOCAL(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_ADRDY) == (LL_ADC_IT_ADRDY)) ? 1UL : 0UL); } @@ -5018,7 +5281,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_ADRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_FLAG_CCRDY) == (LL_ADC_FLAG_CCRDY)) ? 1UL : 0UL); } @@ -5030,7 +5293,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_CCRDY(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)) ? 1UL : 0UL); } @@ -5042,7 +5305,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)) ? 1UL : 0UL); } @@ -5054,7 +5317,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)) ? 1UL : 0UL); } @@ -5066,7 +5329,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)) ? 1UL : 0UL); } @@ -5078,7 +5341,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD1) == (LL_ADC_IT_AWD1)) ? 1UL : 0UL); } @@ -5090,7 +5353,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD1(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD2) == (LL_ADC_IT_AWD2)) ? 1UL : 0UL); } @@ -5102,7 +5365,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD2(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_AWD3) == (LL_ADC_IT_AWD3)) ? 1UL : 0UL); } @@ -5114,7 +5377,7 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD3(ADC_TypeDef *ADCx) * @param ADCx ADC instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(const ADC_TypeDef *ADCx) { return ((READ_BIT(ADCx->IER, LL_ADC_IT_EOCAL) == (LL_ADC_IT_EOCAL)) ? 1UL : 0UL); } @@ -5129,19 +5392,19 @@ __STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOCAL(ADC_TypeDef *ADCx) */ /* Initialization of some features of ADC common parameters and multimode */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); -ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); +ErrorStatus LL_ADC_CommonDeInit(const ADC_Common_TypeDef *ADCxy_COMMON); +ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, const LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *pADC_CommonInitStruct); /* De-initialization of ADC instance */ ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); /* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *pADC_InitStruct); +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, const LL_ADC_InitTypeDef *pADC_InitStruct); void LL_ADC_StructInit(LL_ADC_InitTypeDef *pADC_InitStruct); /* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, const LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *pADC_RegInitStruct); /** diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_comp.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_comp.h index bb679ab5b5..57d346ee8f 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_comp.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_comp.h @@ -73,33 +73,33 @@ typedef struct { uint32_t PowerMode; /*!< Set comparator operating mode to adjust power and speed. This parameter can be a value of @ref COMP_LL_EC_POWERMODE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetPowerMode(). */ + This feature can be modified afterwards using unitary + function @ref LL_COMP_SetPowerMode(). */ uint32_t InputPlus; /*!< Set comparator input plus (non-inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_PLUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputPlus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputPlus(). */ uint32_t InputMinus; /*!< Set comparator input minus (inverting input). This parameter can be a value of @ref COMP_LL_EC_INPUT_MINUS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputMinus(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputMinus(). */ uint32_t InputHysteresis; /*!< Set comparator hysteresis mode of the input minus. This parameter can be a value of @ref COMP_LL_EC_INPUT_HYSTERESIS - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetInputHysteresis(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetInputHysteresis(). */ uint32_t OutputPolarity; /*!< Set comparator output polarity. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputPolarity(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputPolarity(). */ uint32_t OutputBlankingSource; /*!< Set comparator blanking source. This parameter can be a value of @ref COMP_LL_EC_OUTPUT_BLANKING_SOURCE - - This feature can be modified afterwards using unitary function @ref LL_COMP_SetOutputBlankingSource(). */ + This feature can be modified afterwards using unitary function + @ref LL_COMP_SetOutputBlankingSource(). */ } LL_COMP_InitTypeDef; @@ -113,6 +113,7 @@ typedef struct * @{ */ + /** @defgroup COMP_LL_EC_COMMON_WINDOWMODE Comparator common modes - Window mode * @{ */ @@ -122,6 +123,8 @@ typedef struct * @} */ + + /** @defgroup COMP_LL_EC_POWERMODE Comparator modes - Power mode * @{ */ @@ -270,8 +273,7 @@ typedef struct * @param __COMPx__ COMP instance * @retval COMP common instance or value "0" if there is no COMP common instance. */ -#define __LL_COMP_COMMON_INSTANCE(__COMPx__) \ - (COMP12_COMMON) +#define __LL_COMP_COMMON_INSTANCE(__COMPx__) (COMP12_COMMON) /** * @} @@ -286,10 +288,12 @@ typedef struct * @{ */ -/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration of COMP hierarchical scope: common to several COMP instances +/** @defgroup COMP_LL_EF_Configuration_comparator_common Configuration + * of COMP hierarchical scope: common to several COMP instances * @{ */ + /** * @brief Set window mode of a pair of comparators instances * (2 consecutive COMP instances COMP and COMP). @@ -323,6 +327,8 @@ __STATIC_INLINE uint32_t LL_COMP_GetCommonWindowMode(const COMP_Common_TypeDef * return (uint32_t)(READ_BIT(COMPxy_COMMON->CSR, COMP_CSR_WINMODE)); } + + /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h index a69d406412..c4d839573f 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_cortex.h @@ -120,7 +120,7 @@ extern "C" { #define LL_MPU_REGION_SIZE_32B (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_64B (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_128B (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */ -#endif +#endif /* CORE_CM0PLUS */ #define LL_MPU_REGION_SIZE_256B (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_512B (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */ #define LL_MPU_REGION_SIZE_1KB (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */ @@ -166,9 +166,12 @@ extern "C" { /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level * @{ */ +#if defined(CORE_CM0PLUS) +#else #define LL_MPU_TEX_LEVEL0 (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */ #define LL_MPU_TEX_LEVEL1 (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */ #define LL_MPU_TEX_LEVEL2 (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */ +#endif /* CORE_CM0PLUS */ /** * @} @@ -583,7 +586,7 @@ __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region) * or @ref LL_MPU_REGION_SIZE_4GB * @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO * or @ref LL_MPU_REGION_FULL_ACCESS or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO - * @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 + * @arg @ref LL_MPU_TEX_LEVEL0 (*) or @ref LL_MPU_TEX_LEVEL1 (*) or @ref LL_MPU_TEX_LEVEL2 (*) * @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE * @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE * @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_crc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_crc.h index ec93655032..c5c75add9b 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_crc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_crc.h @@ -184,7 +184,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialSize(CRC_TypeDef *CRCx, uint32_t PolySi * @arg @ref LL_CRC_POLYLENGTH_8B * @arg @ref LL_CRC_POLYLENGTH_7B */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialSize(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_POLYSIZE)); } @@ -215,7 +215,7 @@ __STATIC_INLINE void LL_CRC_SetInputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_INDATA_REVERSE_HALFWORD * @arg @ref LL_CRC_INDATA_REVERSE_WORD */ -__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_IN)); } @@ -242,7 +242,7 @@ __STATIC_INLINE void LL_CRC_SetOutputDataReverseMode(CRC_TypeDef *CRCx, uint32_t * @arg @ref LL_CRC_OUTDATA_REVERSE_NONE * @arg @ref LL_CRC_OUTDATA_REVERSE_BIT */ -__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetOutputDataReverseMode(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_BIT(CRCx->CR, CRC_CR_REV_OUT)); } @@ -270,7 +270,7 @@ __STATIC_INLINE void LL_CRC_SetInitialData(CRC_TypeDef *CRCx, uint32_t InitCrc) * @param CRCx CRC Instance * @retval Value programmed in Programmable initial CRC value register */ -__STATIC_INLINE uint32_t LL_CRC_GetInitialData(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetInitialData(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->INIT)); } @@ -301,7 +301,7 @@ __STATIC_INLINE void LL_CRC_SetPolynomialCoef(CRC_TypeDef *CRCx, uint32_t Polyno * @param CRCx CRC Instance * @retval Value programmed in Programmable Polynomial value register */ -__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_GetPolynomialCoef(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->POL)); } @@ -359,7 +359,7 @@ __STATIC_INLINE void LL_CRC_FeedData8(CRC_TypeDef *CRCx, uint8_t InData) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_ReadData32(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->DR)); } @@ -371,7 +371,7 @@ __STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (16 bits). */ -__STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) +__STATIC_INLINE uint16_t LL_CRC_ReadData16(const CRC_TypeDef *CRCx) { return (uint16_t)READ_REG(CRCx->DR); } @@ -383,7 +383,7 @@ __STATIC_INLINE uint16_t LL_CRC_ReadData16(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (8 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData8(const CRC_TypeDef *CRCx) { return (uint8_t)READ_REG(CRCx->DR); } @@ -395,7 +395,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData8(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Current CRC calculation result as stored in CRC_DR register (7 bits). */ -__STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) +__STATIC_INLINE uint8_t LL_CRC_ReadData7(const CRC_TypeDef *CRCx) { return (uint8_t)(READ_REG(CRCx->DR) & 0x7FU); } @@ -407,7 +407,7 @@ __STATIC_INLINE uint8_t LL_CRC_ReadData7(CRC_TypeDef *CRCx) * @param CRCx CRC Instance * @retval Value stored in CRC_IDR register (General-purpose 32-bit data register). */ -__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(const CRC_TypeDef *CRCx) { return (uint32_t)(READ_REG(CRCx->IDR)); } @@ -433,7 +433,7 @@ __STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) * @{ */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); +ErrorStatus LL_CRC_DeInit(const CRC_TypeDef *CRCx); /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dac.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dac.h index 943184aca6..ddc3827c56 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dac.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dac.h @@ -450,15 +450,11 @@ typedef struct * @retval Returned value can be one of the following values: * @arg @ref LL_DAC_CHANNEL_1 */ -#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - (((__DECIMAL_NB__) == 1UL) \ - ? ( \ - LL_DAC_CHANNEL_1 \ - ) \ - : \ - ( \ - 0UL \ - ) \ +#define __LL_DAC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + (((__DECIMAL_NB__) == 1UL) \ + ? (LL_DAC_CHANNEL_1) \ + : \ + (0UL) \ ) /** @@ -493,12 +489,10 @@ typedef struct * @arg @ref LL_DAC_RESOLUTION_8B * @retval DAC conversion data (unit: digital value) */ -#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__,\ - __DAC_VOLTAGE__,\ - __DAC_RESOLUTION__) \ -((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ - / (__VREFANALOG_VOLTAGE__) \ -) +#define __LL_DAC_CALC_VOLTAGE_TO_DATA(__VREFANALOG_VOLTAGE__, __DAC_VOLTAGE__, __DAC_RESOLUTION__) \ + ((__DAC_VOLTAGE__) * __LL_DAC_DIGITAL_SCALE(__DAC_RESOLUTION__) \ + / (__VREFANALOG_VOLTAGE__) \ + ) /** * @} @@ -1502,7 +1496,7 @@ __STATIC_INLINE uint32_t LL_DAC_IsEnabledIT_DMAUDR1(const DAC_TypeDef *DACx) * @{ */ -ErrorStatus LL_DAC_DeInit(DAC_TypeDef *DACx); +ErrorStatus LL_DAC_DeInit(const DAC_TypeDef *DACx); ErrorStatus LL_DAC_Init(DAC_TypeDef *DACx, uint32_t DAC_Channel, const LL_DAC_InitTypeDef *DAC_InitStruct); void LL_DAC_StructInit(LL_DAC_InitTypeDef *DAC_InitStruct); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h index 92c6c9295a..f1214215a6 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dma.h @@ -72,7 +72,7 @@ static const uint8_t CHANNEL_OFFSET_TAB[] = * @retval Channel_Offset (LL_DMA_CHANNEL_7 or 0). */ #define __LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \ -(((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0 : LL_DMA_CHANNEL_7) /** * @} */ @@ -408,7 +408,7 @@ typedef struct * @retval DMAx */ #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) + (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1) /** * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y @@ -416,19 +416,19 @@ typedef struct * @retval LL_DMA_CHANNEL_y */ #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ - LL_DMA_CHANNEL_7) + (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \ + LL_DMA_CHANNEL_7) /** * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely @@ -437,20 +437,20 @@ typedef struct * @retval DMAx_Channely */ #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ - DMA2_Channel7) + ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \ + DMA2_Channel7) /** * @} @@ -462,8 +462,8 @@ typedef struct /* Exported functions --------------------------------------------------------*/ /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ + * @{ + */ /** @defgroup DMA_LL_EF_Configuration Configuration * @{ @@ -482,7 +482,7 @@ typedef struct * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); @@ -502,7 +502,7 @@ __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_EN); @@ -522,7 +522,7 @@ __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -551,7 +551,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + (uint32_t)(CHANNEL_OFFSET_TAB[Channel])))->CCR, @@ -578,7 +578,7 @@ __STATIC_INLINE void LL_DMA_ConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_DMA_CHANNEL_SRC_SEC or @ref LL_DMA_CHANNEL_SRC_NSEC * @arg @ref LL_DMA_CHANNEL_DEST_SEC or LL_DMA_CHANNEL_DEST_NSEC */ -__STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -600,7 +600,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32 * @retval Configuration This parameter must be a combination of all the following values: * @arg @ref LL_DMA_CHANNEL_SEC or @ref LL_DMA_CHANNEL_NSEC */ -__STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -638,7 +638,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetConfigChannelSecure(DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +__STATIC_INLINE void LL_DMA_ConfigTransfer(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -665,7 +665,7 @@ __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -690,7 +690,7 @@ __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -716,7 +716,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint * @arg @ref LL_DMA_MODE_CIRCULAR * @retval None */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +__STATIC_INLINE void LL_DMA_SetMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_CIRC, @@ -739,7 +739,7 @@ __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_ * @arg @ref LL_DMA_MODE_NORMAL * @arg @ref LL_DMA_MODE_CIRCULAR */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -763,7 +763,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_PERIPH_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PINC, @@ -786,7 +786,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_PERIPH_INCREMENT * @arg @ref LL_DMA_PERIPH_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -810,7 +810,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_MEMORY_NOINCREMENT * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MINC, @@ -833,7 +833,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_MEMORY_INCREMENT * @arg @ref LL_DMA_MEMORY_NOINCREMENT */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -858,7 +858,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_PDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +__STATIC_INLINE void LL_DMA_SetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PSIZE, @@ -882,7 +882,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_PDATAALIGN_HALFWORD * @arg @ref LL_DMA_PDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -907,7 +907,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_MDATAALIGN_WORD * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +__STATIC_INLINE void LL_DMA_SetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_MSIZE, @@ -931,7 +931,7 @@ __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_MDATAALIGN_HALFWORD * @arg @ref LL_DMA_MDATAALIGN_WORD */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -957,7 +957,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_PRIORITY_VERYHIGH * @retval None */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PL, @@ -982,7 +982,7 @@ __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_PRIORITY_HIGH * @arg @ref LL_DMA_PRIORITY_VERYHIGH */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -1005,7 +1005,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint3 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM); @@ -1025,7 +1025,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelSecure(DMA_TypeDef *DMAx, uint32_t Chan * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SECM); @@ -1046,7 +1046,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelSecure(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -1068,7 +1068,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSecure(DMA_TypeDef *DMAx, uint32 * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC); @@ -1088,7 +1088,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t C * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_SSEC); @@ -1108,7 +1108,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -1129,7 +1129,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelSrcSecure(DMA_TypeDef *DMAx, uin * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC); @@ -1149,7 +1149,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_DSEC); @@ -1169,7 +1169,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelDestSecure(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -1193,7 +1193,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelDestSecure(DMA_TypeDef *DMAx, ui * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV); @@ -1213,7 +1213,7 @@ __STATIC_INLINE void LL_DMA_EnableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t C * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_PRIV); @@ -1233,7 +1233,7 @@ __STATIC_INLINE void LL_DMA_DisableChannelPrivilege(DMA_TypeDef *DMAx, uint32_t * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -1258,7 +1258,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannelPrivilege(DMA_TypeDef *DMAx, uin * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +__STATIC_INLINE void LL_DMA_SetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) { uint32_t dma_base_addr = (uint32_t)DMAx; MODIFY_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, @@ -1281,7 +1281,7 @@ __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, u * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CNDTR, @@ -1311,7 +1311,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channe * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY * @retval None */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, +__STATIC_INLINE void LL_DMA_ConfigAddresses(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction) { uint32_t dma_base_addr = (uint32_t)DMAx; @@ -1346,7 +1346,7 @@ __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); @@ -1369,7 +1369,7 @@ __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +__STATIC_INLINE void LL_DMA_SetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, PeriphAddress); @@ -1390,7 +1390,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); @@ -1411,7 +1411,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); @@ -1434,7 +1434,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Cha * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR, MemoryAddress); @@ -1457,7 +1457,7 @@ __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) { uint32_t dma_base_addr = (uint32_t)DMAx; WRITE_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR, MemoryAddress); @@ -1478,7 +1478,7 @@ __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CPAR)); @@ -1499,7 +1499,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMA_CHANNEL_7 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return (READ_REG(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CMAR)); @@ -1565,7 +1565,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Cha * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX * @retval None */ -__STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMA_SetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Request) { uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); MODIFY_REG((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -1630,7 +1630,7 @@ __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 7U); return (READ_BIT((DMAMUX1_Channel0 + Channel + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -1650,7 +1650,7 @@ __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Cha * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL); } @@ -1661,7 +1661,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL); } @@ -1672,7 +1672,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL); } @@ -1683,7 +1683,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL); } @@ -1694,7 +1694,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL); } @@ -1705,7 +1705,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL); } @@ -1716,7 +1716,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL); } @@ -1727,7 +1727,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL); } @@ -1738,7 +1738,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL); } @@ -1749,7 +1749,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL); } @@ -1760,7 +1760,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL); } @@ -1771,7 +1771,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL); } @@ -1782,7 +1782,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL); } @@ -1793,7 +1793,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL); } @@ -1804,7 +1804,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL); } @@ -1815,7 +1815,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL); } @@ -1826,7 +1826,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL); } @@ -1837,7 +1837,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL); } @@ -1848,7 +1848,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL); } @@ -1859,7 +1859,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL); } @@ -1870,7 +1870,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL); } @@ -1881,7 +1881,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL); } @@ -1892,7 +1892,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL); } @@ -1903,7 +1903,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL); } @@ -1914,7 +1914,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL); } @@ -1925,7 +1925,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL); } @@ -1936,7 +1936,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL); } @@ -1947,7 +1947,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx) * @param DMAx DMAx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx) +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(const DMA_TypeDef *DMAx) { return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL); } @@ -2281,7 +2281,7 @@ __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); @@ -2301,7 +2301,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); @@ -2321,7 +2321,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_EnableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; SET_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); @@ -2341,7 +2341,7 @@ __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TCIE); @@ -2361,7 +2361,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_HTIE); @@ -2381,7 +2381,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval None */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE void LL_DMA_DisableIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; CLEAR_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, DMA_CCR_TEIE); @@ -2401,7 +2401,7 @@ __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -2422,7 +2422,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, @@ -2443,7 +2443,7 @@ __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Chann * @arg @ref LL_DMA_CHANNEL_7 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(const DMA_TypeDef *DMAx, uint32_t Channel) { uint32_t dma_base_addr = (uint32_t)DMAx; return ((READ_BIT(((DMA_Channel_TypeDef *)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel]))->CCR, diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h index 70eea14752..3c86b08ddc 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_dmamux.h @@ -320,8 +320,8 @@ extern "C" { /* Exported functions --------------------------------------------------------*/ /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions - * @{ - */ + * @{ + */ /** @defgroup DMAMUX_LL_EF_Configuration Configuration * @{ @@ -393,7 +393,7 @@ extern "C" { * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) +__STATIC_INLINE void LL_DMAMUX_SetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID, Request); @@ -465,7 +465,7 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_RX * @arg @ref LL_DMAMUX_REQ_SUBGHZSPI_TX */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_DMAREQ_ID)); @@ -495,7 +495,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ, ((RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos)); @@ -524,7 +524,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_NBREQ)) >> DMAMUX_CxCR_NBREQ_Pos) + 1U); @@ -558,7 +558,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAM * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL, Polarity); @@ -591,7 +591,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_SYNC_POL_FALLING * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SPOL)); @@ -620,7 +620,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); @@ -649,7 +649,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE); @@ -678,7 +678,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DM * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL); @@ -707,7 +707,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeD * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); @@ -736,7 +736,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint3 * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE); @@ -765,7 +765,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL); @@ -816,7 +816,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) +__STATIC_INLINE void LL_DMAMUX_SetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID) { (void)(DMAMUXx); MODIFY_REG((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID, SyncID); @@ -866,7 +866,7 @@ __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32 * @arg @ref LL_DMAMUX_SYNC_LPTIM2_OUT * @arg @ref LL_DMAMUX_SYNC_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (uint32_t)(READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SYNC_ID)); @@ -883,10 +883,11 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + SET_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -900,10 +901,11 @@ __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); + CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE); } /** @@ -917,10 +919,11 @@ __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); + return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL); } /** @@ -939,10 +942,12 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *D * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity) +__STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t Polarity) { (void)(DMAMUXx); - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL, Polarity); } /** @@ -960,10 +965,11 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMA * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GPOL)); } /** @@ -979,10 +985,12 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32. * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb) +__STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestNb) { (void)(DMAMUXx); - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos); } /** @@ -996,10 +1004,11 @@ __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval Between Min_Data = 1 and Max_Data = 32 */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); + return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U); } /** @@ -1035,10 +1044,12 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMU * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT * @retval None */ -__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID) +__STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, + uint32_t RequestSignalID) { (void)(DMAMUXx); - MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); + MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * + (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID); } /** @@ -1073,10 +1084,11 @@ __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM2_OUT * @arg @ref LL_DMAMUX_REQ_GEN_LPTIM3_OUT */ -__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); - return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); + return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_RequestGenerator0 + + (DMAMUX_RGCR_SIZE * (RequestGenChannel)))))->RGCR, DMAMUX_RGxCR_SIG_ID)); } /** @@ -1093,7 +1105,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL); @@ -1105,7 +1117,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL); @@ -1117,7 +1129,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL); @@ -1129,7 +1141,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL); @@ -1141,7 +1153,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL); @@ -1153,7 +1165,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL); @@ -1165,7 +1177,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL); @@ -1177,7 +1189,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL); @@ -1189,7 +1201,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL); @@ -1201,7 +1213,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL); @@ -1213,7 +1225,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAM * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL); @@ -1225,7 +1237,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL); @@ -1237,7 +1249,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL); @@ -1249,7 +1261,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_ChannelStatus->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL); @@ -1261,7 +1273,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL); @@ -1273,7 +1285,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL); @@ -1285,7 +1297,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL); @@ -1297,7 +1309,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); return ((READ_BIT(DMAMUX1_RequestGenStatus->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL); @@ -1309,7 +1321,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMA * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF0); @@ -1321,7 +1333,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF1); @@ -1333,7 +1345,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF2); @@ -1345,7 +1357,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF3); @@ -1357,7 +1369,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF4); @@ -1369,7 +1381,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF5); @@ -1381,7 +1393,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF6); @@ -1393,7 +1405,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF7); @@ -1405,7 +1417,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF8); @@ -1417,7 +1429,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF9); @@ -1429,7 +1441,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF10); @@ -1441,7 +1453,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF11); @@ -1453,7 +1465,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF12); @@ -1465,7 +1477,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_ChannelStatus->CFR, DMAMUX_CFR_CSOF13); @@ -1477,7 +1489,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF0); @@ -1489,7 +1501,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF1); @@ -1501,7 +1513,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF2); @@ -1513,7 +1525,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx) * @param DMAMUXx DMAMUXx DMAMUXx Instance * @retval None */ -__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) +__STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(const DMAMUX_Channel_TypeDef *DMAMUXx) { (void)(DMAMUXx); SET_BIT(DMAMUX1_RequestGenStatus->RGCFR, DMAMUX_RGCFR_COF3); @@ -1550,7 +1562,7 @@ __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx) * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); @@ -1579,7 +1591,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE); @@ -1608,7 +1620,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_CHANNEL_13 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel) { (void)(DMAMUXx); return (((READ_BIT((DMAMUX1_Channel0 + Channel)->CCR, DMAMUX_CxCR_SOIE)) == (DMAMUX_CxCR_SOIE)) ? 1UL : 0UL); @@ -1625,7 +1637,7 @@ __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUX * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); SET_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); @@ -1642,7 +1654,7 @@ __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uin * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval None */ -__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); CLEAR_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE); @@ -1659,7 +1671,7 @@ __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, ui * @arg @ref LL_DMAMUX_REQ_GEN_3 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) +__STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(const DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel) { (void)(DMAMUXx); return ((READ_BIT((DMAMUX1_RequestGenerator0 + RequestGenChannel)->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h index 2d240924e5..47e105fecc 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_gpio.h @@ -313,7 +313,7 @@ __STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_MODE_ALTERNATE * @arg @ref LL_GPIO_MODE_ANALOG */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(const GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); @@ -386,7 +386,7 @@ __STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinM * @arg @ref LL_GPIO_OUTPUT_PUSHPULL * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(const GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); @@ -468,7 +468,7 @@ __STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint * @arg @ref LL_GPIO_SPEED_FREQ_HIGH * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(const GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); @@ -542,7 +542,7 @@ __STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint3 * @arg @ref LL_GPIO_PULL_UP * @arg @ref LL_GPIO_PULL_DOWN */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(const GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); @@ -628,7 +628,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uin * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(const GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(GPIOx->AFR[0], @@ -716,7 +716,7 @@ __STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, ui * @arg @ref LL_GPIO_AF_14 * @arg @ref LL_GPIO_AF_15 */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(const GPIO_TypeDef *GPIOx, uint32_t Pin) { #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(GPIOx->AFR[1], @@ -793,7 +793,7 @@ __STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -804,7 +804,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMa * @param GPIOx GPIO Port * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(const GPIO_TypeDef *GPIOx) { return ((READ_BIT(GPIOx->LCKR, GPIO_LCKR_LCKK) == (GPIO_LCKR_LCKK)) ? 1UL : 0UL); } @@ -823,7 +823,7 @@ __STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) * @param GPIOx GPIO Port * @retval Input data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->IDR)); } @@ -852,7 +852,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->IDR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -875,7 +875,7 @@ __STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortV * @param GPIOx GPIO Port * @retval Output data register value of port */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(const GPIO_TypeDef *GPIOx) { return (uint32_t)(READ_REG(GPIOx->ODR)); } @@ -904,7 +904,7 @@ __STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) * @arg @ref LL_GPIO_PIN_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(const GPIO_TypeDef *GPIOx, uint32_t PinMask) { return ((READ_BIT(GPIOx->ODR, PinMask) == (PinMask)) ? 1UL : 0UL); } @@ -1006,7 +1006,7 @@ __STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) * @{ */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_DeInit(const GPIO_TypeDef *GPIOx); ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_hsem.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_hsem.h index 45eaadd77f..ac9ef45b9e 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_hsem.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_hsem.h @@ -84,23 +84,7 @@ extern "C" { #define LL_HSEM_SEMAPHORE_13 HSEM_C1IER_ISE13 #define LL_HSEM_SEMAPHORE_14 HSEM_C1IER_ISE14 #define LL_HSEM_SEMAPHORE_15 HSEM_C1IER_ISE15 -#define LL_HSEM_SEMAPHORE_16 HSEM_C1IER_ISE16 -#define LL_HSEM_SEMAPHORE_17 HSEM_C1IER_ISE17 -#define LL_HSEM_SEMAPHORE_18 HSEM_C1IER_ISE18 -#define LL_HSEM_SEMAPHORE_19 HSEM_C1IER_ISE19 -#define LL_HSEM_SEMAPHORE_20 HSEM_C1IER_ISE20 -#define LL_HSEM_SEMAPHORE_21 HSEM_C1IER_ISE21 -#define LL_HSEM_SEMAPHORE_22 HSEM_C1IER_ISE22 -#define LL_HSEM_SEMAPHORE_23 HSEM_C1IER_ISE23 -#define LL_HSEM_SEMAPHORE_24 HSEM_C1IER_ISE24 -#define LL_HSEM_SEMAPHORE_25 HSEM_C1IER_ISE25 -#define LL_HSEM_SEMAPHORE_26 HSEM_C1IER_ISE26 -#define LL_HSEM_SEMAPHORE_27 HSEM_C1IER_ISE27 -#define LL_HSEM_SEMAPHORE_28 HSEM_C1IER_ISE28 -#define LL_HSEM_SEMAPHORE_29 HSEM_C1IER_ISE29 -#define LL_HSEM_SEMAPHORE_30 HSEM_C1IER_ISE30 -#define LL_HSEM_SEMAPHORE_31 HSEM_C1IER_ISE31 -#define LL_HSEM_SEMAPHORE_ALL 0xFFFFFFFFU +#define LL_HSEM_SEMAPHORE_ALL 0x0000FFFFU /** * @} */ @@ -159,7 +143,7 @@ extern "C" { * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((READ_BIT(HSEMx->R[Semaphore], HSEM_R_LOCK) == (HSEM_R_LOCK_Msk)) ? 1UL : 0UL); } @@ -174,7 +158,7 @@ __STATIC_INLINE uint32_t LL_HSEM_IsSemaphoreLocked(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_COREID_CPU1 * @arg @ref LL_HSEM_COREID_CPU2 */ -__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetCoreId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_COREID_Msk)); } @@ -186,7 +170,7 @@ __STATIC_INLINE uint32_t LL_HSEM_GetCoreId(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval Process number. Value between Min_Data=0 and Max_Data=255 */ -__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetProcessId(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return (uint32_t)(READ_BIT(HSEMx->R[Semaphore], HSEM_R_PROCID_Msk)); } @@ -232,9 +216,9 @@ __STATIC_INLINE uint32_t LL_HSEM_2StepLock(HSEM_TypeDef *HSEMx, uint32_t Semapho * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 1 lock fail, 0 lock successful or already locked by same core */ -__STATIC_INLINE uint32_t LL_HSEM_1StepLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_1StepLock(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { - return ((HSEMx->RLR[Semaphore] != (HSEM_R_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); + return ((HSEMx->RLR[Semaphore] != (HSEM_RLR_LOCK | LL_HSEM_COREID)) ? 1UL : 0UL); } /** @@ -257,7 +241,7 @@ __STATIC_INLINE void LL_HSEM_ReleaseLock(HSEM_TypeDef *HSEMx, uint32_t Semaphore * @param HSEMx HSEM Instance. * @param Semaphore Semaphore number. Value between Min_Data=0 and Max_Data=31 * @retval 0 semaphore is free, 1 semaphore is locked */ -__STATIC_INLINE uint32_t LL_HSEM_GetStatus(HSEM_TypeDef *HSEMx, uint32_t Semaphore) +__STATIC_INLINE uint32_t LL_HSEM_GetStatus(const HSEM_TypeDef *HSEMx, uint32_t Semaphore) { return ((HSEMx->R[Semaphore] != 0U) ? 1UL : 0UL); } @@ -280,7 +264,7 @@ __STATIC_INLINE void LL_HSEM_SetKey(HSEM_TypeDef *HSEMx, uint32_t key) * @param HSEMx HSEM Instance. * @retval key to unlock all semaphore from the same core */ -__STATIC_INLINE uint32_t LL_HSEM_GetKey(HSEM_TypeDef *HSEMx) +__STATIC_INLINE uint32_t LL_HSEM_GetKey(const HSEM_TypeDef *HSEMx) { return (uint32_t)(READ_BIT(HSEMx->KEYR, HSEM_KEYR_KEY) >> HSEM_KEYR_KEY_Pos); } @@ -331,22 +315,6 @@ __STATIC_INLINE void LL_HSEM_ResetAllLock(HSEM_TypeDef *HSEMx, uint32_t key, uin * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -376,22 +344,6 @@ __STATIC_INLINE void LL_HSEM_EnableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semaph * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -421,26 +373,10 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -467,22 +403,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C1IER(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -512,22 +432,6 @@ __STATIC_INLINE void LL_HSEM_EnableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semaph * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -557,26 +461,10 @@ __STATIC_INLINE void LL_HSEM_DisableIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2IER, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -611,22 +499,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsEnabledIT_C2IER(HSEM_TypeDef *HSEMx, uint32_t * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -656,26 +528,10 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C1ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -701,26 +557,10 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C1MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -747,22 +587,6 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C1MISR(HSEM_TypeDef *HSEMx, uint32 * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval None */ @@ -792,26 +616,10 @@ __STATIC_INLINE void LL_HSEM_ClearFlag_C2ICR(HSEM_TypeDef *HSEMx, uint32_t Semap * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2ISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } @@ -837,26 +645,10 @@ __STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2ISR(HSEM_TypeDef *HSEMx, uint32_ * @arg @ref LL_HSEM_SEMAPHORE_13 * @arg @ref LL_HSEM_SEMAPHORE_14 * @arg @ref LL_HSEM_SEMAPHORE_15 - * @arg @ref LL_HSEM_SEMAPHORE_16 - * @arg @ref LL_HSEM_SEMAPHORE_17 - * @arg @ref LL_HSEM_SEMAPHORE_18 - * @arg @ref LL_HSEM_SEMAPHORE_19 - * @arg @ref LL_HSEM_SEMAPHORE_20 - * @arg @ref LL_HSEM_SEMAPHORE_21 - * @arg @ref LL_HSEM_SEMAPHORE_22 - * @arg @ref LL_HSEM_SEMAPHORE_23 - * @arg @ref LL_HSEM_SEMAPHORE_24 - * @arg @ref LL_HSEM_SEMAPHORE_25 - * @arg @ref LL_HSEM_SEMAPHORE_26 - * @arg @ref LL_HSEM_SEMAPHORE_27 - * @arg @ref LL_HSEM_SEMAPHORE_28 - * @arg @ref LL_HSEM_SEMAPHORE_29 - * @arg @ref LL_HSEM_SEMAPHORE_30 - * @arg @ref LL_HSEM_SEMAPHORE_31 * @arg @ref LL_HSEM_SEMAPHORE_ALL * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) +__STATIC_INLINE uint32_t LL_HSEM_IsActiveFlag_C2MISR(const HSEM_TypeDef *HSEMx, uint32_t SemaphoreMask) { return ((READ_BIT(HSEMx->C2MISR, SemaphoreMask) == (SemaphoreMask)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h index f9adda22f3..d35068e2de 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_i2c.h @@ -2248,8 +2248,8 @@ __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) * @{ */ -ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -ErrorStatus LL_I2C_DeInit(I2C_TypeDef *I2Cx); +ErrorStatus LL_I2C_Init(I2C_TypeDef *I2Cx, const LL_I2C_InitTypeDef *I2C_InitStruct); +ErrorStatus LL_I2C_DeInit(const I2C_TypeDef *I2Cx); void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_iwdg.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_iwdg.h index 620c97a7ea..b5d86c725a 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_iwdg.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_iwdg.h @@ -208,7 +208,7 @@ __STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescale * @arg @ref LL_IWDG_PRESCALER_128 * @arg @ref LL_IWDG_PRESCALER_256 */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->PR)); } @@ -231,7 +231,7 @@ __STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Coun * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->RLR)); } @@ -254,7 +254,7 @@ __STATIC_INLINE void LL_IWDG_SetWindow(IWDG_TypeDef *IWDGx, uint32_t Window) * @param IWDGx IWDG Instance * @retval Value between Min_Data=0 and Max_Data=0x0FFF */ -__STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_GetWindow(const IWDG_TypeDef *IWDGx) { return (READ_REG(IWDGx->WINR)); } @@ -273,7 +273,7 @@ __STATIC_INLINE uint32_t LL_IWDG_GetWindow(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)) ? 1UL : 0UL); } @@ -284,7 +284,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)) ? 1UL : 0UL); } @@ -295,7 +295,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_WVU) == (IWDG_SR_WVU)) ? 1UL : 0UL); } @@ -308,7 +308,7 @@ __STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_WVU(IWDG_TypeDef *IWDGx) * @param IWDGx IWDG Instance * @retval State of bits (1 or 0). */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +__STATIC_INLINE uint32_t LL_IWDG_IsReady(const IWDG_TypeDef *IWDGx) { return ((READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU | IWDG_SR_WVU) == 0U) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lptim.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lptim.h index d695f945bf..d350f510af 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lptim.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lptim.h @@ -350,7 +350,7 @@ typedef struct * @{ */ -ErrorStatus LL_LPTIM_DeInit(LPTIM_TypeDef *LPTIMx); +ErrorStatus LL_LPTIM_DeInit(const LPTIM_TypeDef *LPTIMx); void LL_LPTIM_StructInit(LL_LPTIM_InitTypeDef *LPTIM_InitStruct); ErrorStatus LL_LPTIM_Init(LPTIM_TypeDef *LPTIMx, const LL_LPTIM_InitTypeDef *LPTIM_InitStruct); void LL_LPTIM_Disable(LPTIM_TypeDef *LPTIMx); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h index 1e952b4c70..c76640c981 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_lpuart.h @@ -56,6 +56,10 @@ static const uint16_t LPUART_PRESCALER_TAB[] = (uint16_t)32, (uint16_t)64, (uint16_t)128, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, + (uint16_t)256, (uint16_t)256 }; /** @@ -1637,8 +1641,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_IDLE(const USART_TypeDef *LPUART return ((READ_BIT(LPUARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE +#define LL_LPUART_IsActiveFlag_RXNE LL_LPUART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Read Data Register or LPUART RX FIFO Not Empty Flag is set or not @@ -1662,8 +1665,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsActiveFlag_TC(const USART_TypeDef *LPUARTx) return ((READ_BIT(LPUARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF +#define LL_LPUART_IsActiveFlag_TXE LL_LPUART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART Transmit Data Register Empty or LPUART TX FIFO Not Full Flag is set or not @@ -1937,8 +1939,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE +#define LL_LPUART_EnableIT_RXNE LL_LPUART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt @@ -1962,8 +1963,7 @@ __STATIC_INLINE void LL_LPUART_EnableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_SET_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF +#define LL_LPUART_EnableIT_TXE LL_LPUART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt @@ -2090,8 +2090,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_IDLE(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE +#define LL_LPUART_DisableIT_RXNE LL_LPUART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt @@ -2115,8 +2114,7 @@ __STATIC_INLINE void LL_LPUART_DisableIT_TC(USART_TypeDef *LPUARTx) ATOMIC_CLEAR_BIT(LPUARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF +#define LL_LPUART_DisableIT_TXE LL_LPUART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt @@ -2243,8 +2241,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_IDLE(const USART_TypeDef *LPUARTx return ((READ_BIT(LPUARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE +#define LL_LPUART_IsEnabledIT_RXNE LL_LPUART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART RX Not Empty and LPUART RX FIFO Not Empty Interrupt is enabled or disabled. @@ -2268,8 +2265,7 @@ __STATIC_INLINE uint32_t LL_LPUART_IsEnabledIT_TC(const USART_TypeDef *LPUARTx) return ((READ_BIT(LPUARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF +#define LL_LPUART_IsEnabledIT_TXE LL_LPUART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the LPUART TX Empty and LPUART TX FIFO Not Full Interrupt is enabled or disabled @@ -2613,6 +2609,21 @@ __STATIC_INLINE void LL_LPUART_RequestRxDataFlush(USART_TypeDef *LPUARTx) SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_RXFRQ); } +/** + * @brief Request a Transmit data FIFO flush + * @note TXFRQ bit is set to flush the whole FIFO when FIFO mode is enabled. This + * also sets the flag TXFE (TXFIFO empty bit in the LPUART_ISR register). + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * FIFO mode feature is supported by the USARTx instance. + * @rmtoll RQR TXFRQ LL_LPUART_RequestTxDataFlush + * @param LPUARTx LPUART Instance + * @retval None + */ +__STATIC_INLINE void LL_LPUART_RequestTxDataFlush(USART_TypeDef *LPUARTx) +{ + SET_BIT(LPUARTx->RQR, (uint16_t)USART_RQR_TXFRQ); +} + /** * @} */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pka.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pka.h index 77a56909b7..4f88670ca3 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pka.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pka.h @@ -223,7 +223,7 @@ __STATIC_INLINE void LL_PKA_Disable(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabled(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabled(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_EN) == (PKA_CR_EN)) ? 1UL : 0UL); } @@ -282,7 +282,7 @@ __STATIC_INLINE void LL_PKA_SetMode(PKA_TypeDef *PKAx, uint32_t Mode) * @arg @ref LL_PKA_MODE_MODULAR_SUB * @arg @ref LL_PKA_MODE_MONTGOMERY_MUL */ -__STATIC_INLINE uint32_t LL_PKA_GetMode(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_GetMode(const PKA_TypeDef *PKAx) { return (uint32_t)(READ_BIT(PKAx->CR, PKA_CR_MODE) >> PKA_CR_MODE_Pos); } @@ -379,7 +379,7 @@ __STATIC_INLINE void LL_PKA_DisableIT_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_ADDRERRIE) == (PKA_CR_ADDRERRIE)) ? 1UL : 0UL); } @@ -390,7 +390,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_ADDRERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_RAMERRIE) == (PKA_CR_RAMERRIE)) ? 1UL : 0UL); } @@ -402,7 +402,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_RAMERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->CR, PKA_CR_PROCENDIE) == (PKA_CR_PROCENDIE)) ? 1UL : 0UL); } @@ -421,7 +421,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsEnabledIT_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_ADDRERRF) == (PKA_SR_ADDRERRF)) ? 1UL : 0UL); } @@ -432,7 +432,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_ADDRERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_RAMERRF) == (PKA_SR_RAMERRF)) ? 1UL : 0UL); } @@ -444,7 +444,7 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_RAMERR(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_PROCENDF) == (PKA_SR_PROCENDF)) ? 1UL : 0UL); } @@ -455,11 +455,22 @@ __STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_PROCEND(PKA_TypeDef *PKAx) * @param PKAx PKA Instance. * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(PKA_TypeDef *PKAx) +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_BUSY(const PKA_TypeDef *PKAx) { return ((READ_BIT(PKAx->SR, PKA_SR_BUSY) == (PKA_SR_BUSY)) ? 1UL : 0UL); } - +#if defined(PKA_SR_INITOK) +/** + * @brief Get PKA init ok flag. + * @rmtoll SR INITOK LL_PKA_IsActiveFlag_INITOK + * @param PKAx PKA Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_PKA_IsActiveFlag_INITOK(const PKA_TypeDef *PKAx) +{ + return ((READ_BIT(PKAx->SR, PKA_SR_INITOK) == (PKA_SR_INITOK)) ? 1UL : 0UL); +} +#endif /* PKA_SR_INITOK */ /** * @brief Clear PKA address error flag. * @rmtoll CLRFR ADDRERRFC LL_PKA_ClearFlag_ADDERR @@ -504,7 +515,7 @@ __STATIC_INLINE void LL_PKA_ClearFlag_PROCEND(PKA_TypeDef *PKAx) * @{ */ -ErrorStatus LL_PKA_DeInit(PKA_TypeDef *PKAx); +ErrorStatus LL_PKA_DeInit(const PKA_TypeDef *PKAx); ErrorStatus LL_PKA_Init(PKA_TypeDef *PKAx, LL_PKA_InitTypeDef *PKA_InitStruct); void LL_PKA_StructInit(LL_PKA_InitTypeDef *PKA_InitStruct); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h index e287bd7988..b21706e4f4 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_pwr.h @@ -113,7 +113,7 @@ extern "C" { #define LL_PWR_EXTSCR_C2DS PWR_EXTSCR_C2DS /* CPU2 deepsleep mode */ #define LL_PWR_SR2_C2BOOTS PWR_SR2_C2BOOTS /* CPU2 boot request source information flag */ #define LL_PWR_SR1_C2HF PWR_SR1_C2HF /* CPU2 hold interrupt flag */ -#endif +#endif /* DUAL_CORE */ /** * @} */ @@ -1776,7 +1776,7 @@ __STATIC_INLINE uint32_t LL_PWR_C2_IsEnabledWakeUp_ILAC(void) { return ((READ_BIT(PWR->SECCFGR, PWR_SECCFGR_C2EWILA) == (PWR_SECCFGR_C2EWILA)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @} @@ -2094,7 +2094,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_C2BOOTS(void) { return ((READ_BIT(PWR->SR2, PWR_SR2_C2BOOTS) == (PWR_SR2_C2BOOTS)) ? 1UL : 0UL); } -#endif +#endif /* DUAL_CORE */ /** * @brief Get system Stop 0 or Stop 1 flag for CPU1 @@ -2186,7 +2186,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_C2H(void) { WRITE_REG(PWR->SCR, PWR_SCR_CC2HF); } -#endif +#endif /* DUAL_CORE */ /** * @brief Clear standby and stop flags for CPU1 @@ -2208,7 +2208,7 @@ __STATIC_INLINE void LL_PWR_ClearFlag_C2STOP_C2STB(void) { WRITE_REG(PWR->EXTSCR, PWR_EXTSCR_C2CSSF); } -#endif +#endif /* DUAL_CORE */ /** * @} @@ -2252,7 +2252,7 @@ __STATIC_INLINE uint32_t LL_PWR_IsEnabledIT_HoldCPU2(void) /** * @} */ -#endif +#endif /* DUAL_CORE */ #if defined(USE_FULL_LL_DRIVER) /** @defgroup PWR_LL_EF_Init De-initialization function @@ -2272,7 +2272,7 @@ ErrorStatus LL_PWR_DeInit(void); * @} */ -#endif /* defined(PWR) */ +#endif /* PWR */ /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rng.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rng.h index 33e0cbe57b..c0e6aa5964 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rng.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rng.h @@ -38,6 +38,15 @@ extern "C" { */ /* Private types -------------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/** @defgroup RNG_LL_Private_Defines RNG Private Defines + * @{ + */ +/* Health test control register information to use in CCM algorithm */ +#define LL_RNG_HTCFG 0x17590ABCU /*!< Magic number */ +/** + * @} + */ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ /* Private macros ------------------------------------------------------------*/ @@ -208,7 +217,7 @@ __STATIC_INLINE void LL_RNG_Disable(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabled(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_RNGEN) == (RNG_CR_RNGEN)) ? 1UL : 0UL); } @@ -221,7 +230,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabled(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_ENABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -232,7 +242,8 @@ __STATIC_INLINE void LL_RNG_EnableClkErrorDetect(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_CED); + MODIFY_REG(RNGx->CR, RNG_CR_CED | RNG_CR_CONDRST, LL_RNG_CED_DISABLE | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -241,7 +252,7 @@ __STATIC_INLINE void LL_RNG_DisableClkErrorDetect(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledClkErrorDetect(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CED) != (RNG_CR_CED)) ? 1UL : 0UL); } @@ -274,7 +285,7 @@ __STATIC_INLINE void LL_RNG_DisableCondReset(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledCondReset(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CONDRST) == (RNG_CR_CONDRST)) ? 1UL : 0UL); } @@ -296,7 +307,7 @@ __STATIC_INLINE void LL_RNG_ConfigLock(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_CONFIGLOCK) == (RNG_CR_CONFIGLOCK)) ? 1UL : 0UL); } @@ -309,7 +320,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsConfigLocked(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) { - CLEAR_BIT(RNGx->CR, RNG_CR_NISTC); + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_NIST_COMPLIANT | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -320,7 +332,8 @@ __STATIC_INLINE void LL_RNG_EnableNistCompliance(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) { - SET_BIT(RNGx->CR, RNG_CR_NISTC); + MODIFY_REG(RNGx->CR, RNG_CR_NISTC | RNG_CR_CONDRST, LL_RNG_CUSTOM_NIST | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -329,7 +342,7 @@ __STATIC_INLINE void LL_RNG_DisableNistCompliance(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_NISTC) != (RNG_CR_NISTC)) ? 1UL : 0UL); } @@ -343,7 +356,8 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledNistCompliance(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) { - MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1, Config1 << RNG_CR_RNG_CONFIG1_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG1 | RNG_CR_CONDRST, (Config1 << RNG_CR_RNG_CONFIG1_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -352,7 +366,7 @@ __STATIC_INLINE void LL_RNG_SetConfig1(RNG_TypeDef *RNGx, uint32_t Config1) * @param RNGx RNG Instance * @retval Returned Value expressed on 6 bits : Value between 0 and 0x3F */ -__STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetConfig1(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG1) >> RNG_CR_RNG_CONFIG1_Pos); } @@ -366,7 +380,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig1(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) { - MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2, Config2 << RNG_CR_RNG_CONFIG2_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG2 | RNG_CR_CONDRST, (Config2 << RNG_CR_RNG_CONFIG2_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -375,7 +390,7 @@ __STATIC_INLINE void LL_RNG_SetConfig2(RNG_TypeDef *RNGx, uint32_t Config2) * @param RNGx RNG Instance * @retval Returned Value expressed on 3 bits : Value between 0 and 0x7 */ -__STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetConfig2(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG2) >> RNG_CR_RNG_CONFIG2_Pos); } @@ -389,7 +404,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig2(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) { - MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3, Config3 << RNG_CR_RNG_CONFIG3_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_RNG_CONFIG3 | RNG_CR_CONDRST, (Config3 << RNG_CR_RNG_CONFIG3_Pos) | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -398,7 +414,7 @@ __STATIC_INLINE void LL_RNG_SetConfig3(RNG_TypeDef *RNGx, uint32_t Config3) * @param RNGx RNG Instance * @retval Returned Value expressed on 4 bits : Value between 0 and 0xF */ -__STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetConfig3(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_BIT(RNGx->CR, RNG_CR_RNG_CONFIG3) >> RNG_CR_RNG_CONFIG3_Pos); } @@ -428,7 +444,8 @@ __STATIC_INLINE uint32_t LL_RNG_GetConfig3(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) { - MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV, Divider << RNG_CR_CLKDIV_Pos); + MODIFY_REG(RNGx->CR, RNG_CR_CLKDIV | RNG_CR_CONDRST, Divider | RNG_CR_CONDRST); + CLEAR_BIT(RNGx->CR, RNG_CR_CONDRST); } /** @@ -453,7 +470,7 @@ __STATIC_INLINE void LL_RNG_SetClockDivider(RNG_TypeDef *RNGx, uint32_t Divider) * @arg @ref LL_RNG_CLKDIV_BY_16384 * @arg @ref LL_RNG_CLKDIV_BY_32768 */ -__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_GetClockDivider(const RNG_TypeDef *RNGx) { return (uint32_t)READ_BIT(RNGx->CR, RNG_CR_CLKDIV); } @@ -471,7 +488,7 @@ __STATIC_INLINE uint32_t LL_RNG_GetClockDivider(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_DRDY) == (RNG_SR_DRDY)) ? 1UL : 0UL); } @@ -482,7 +499,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_DRDY(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CECS) == (RNG_SR_CECS)) ? 1UL : 0UL); } @@ -493,7 +510,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SECS) == (RNG_SR_SECS)) ? 1UL : 0UL); } @@ -504,7 +521,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SECS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_CEIS) == (RNG_SR_CEIS)) ? 1UL : 0UL); } @@ -515,7 +532,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_CEIS(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsActiveFlag_SEIS(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->SR, RNG_SR_SEIS) == (RNG_SR_SEIS)) ? 1UL : 0UL); } @@ -581,7 +598,7 @@ __STATIC_INLINE void LL_RNG_DisableIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(const RNG_TypeDef *RNGx) { return ((READ_BIT(RNGx->CR, RNG_CR_IE) == (RNG_CR_IE)) ? 1UL : 0UL); } @@ -600,7 +617,7 @@ __STATIC_INLINE uint32_t LL_RNG_IsEnabledIT(RNG_TypeDef *RNGx) * @param RNGx RNG Instance * @retval Generated 32-bit random value */ -__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) +__STATIC_INLINE uint32_t LL_RNG_ReadRandData32(const RNG_TypeDef *RNGx) { return (uint32_t)(READ_REG(RNGx->DR)); } @@ -623,6 +640,9 @@ __STATIC_INLINE uint32_t LL_RNG_ReadRandData32(RNG_TypeDef *RNGx) */ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) { + /*!< magic number must be written immediately before to RNG_HTCRG */ + WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG); + WRITE_REG(RNGx->HTCR, HTCFG); } @@ -634,6 +654,9 @@ __STATIC_INLINE void LL_RNG_SetHealthConfig(RNG_TypeDef *RNGx, uint32_t HTCFG) */ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) { + /*!< magic number must be written immediately before reading RNG_HTCRG */ + WRITE_REG(RNGx->HTCR, LL_RNG_HTCFG); + return (uint32_t)READ_REG(RNGx->HTCR); } @@ -645,9 +668,9 @@ __STATIC_INLINE uint32_t LL_RNG_GetHealthConfig(RNG_TypeDef *RNGx) /** @defgroup RNG_LL_EF_Init Initialization and de-initialization functions * @{ */ -ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, LL_RNG_InitTypeDef *RNG_InitStruct); +ErrorStatus LL_RNG_Init(RNG_TypeDef *RNGx, const LL_RNG_InitTypeDef *RNG_InitStruct); void LL_RNG_StructInit(LL_RNG_InitTypeDef *RNG_InitStruct); -ErrorStatus LL_RNG_DeInit(RNG_TypeDef *RNGx); +ErrorStatus LL_RNG_DeInit(const RNG_TypeDef *RNGx); /** * @} diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h index f03a4d1df1..a5157c3cf9 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_rtc.h @@ -71,11 +71,11 @@ extern "C" { /** * @} */ -#endif /*USE_FULL_LL_DRIVER*/ +#endif /* USE_FULL_LL_DRIVER */ #if !defined (UNUSED) #define UNUSED(x) ((void)(x)) -#endif +#endif /* !UNUSED */ /* Exported types ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) @@ -326,8 +326,8 @@ typedef struct #define LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN RTC_CR_TAMPALRM_TYPE /*!< RTC_ALARM is open-drain output */ #define LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL 0x00000000U /*!< RTC_ALARM is push-pull output */ /** -* @} -*/ + * @} + */ /** @defgroup RTC_LL_EC_OUTPUTPOLARITY_PIN OUTPUT POLARITY PIN * @{ @@ -692,7 +692,8 @@ typedef struct * @param __VALUE__ BCD value to be converted * @retval Converted byte */ -#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU))) +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) ((uint8_t)((((uint8_t)((__VALUE__) &\ + (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U) + ((__VALUE__) & (uint8_t)0x0FU))) /** * @} @@ -819,7 +820,7 @@ __STATIC_INLINE void LL_RTC_SetHourFormat(RTC_TypeDef *RTCx, uint32_t HourFormat * @arg @ref LL_RTC_HOURFORMAT_24HOUR * @arg @ref LL_RTC_HOURFORMAT_AMPM */ -__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetHourFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_FMT)); } @@ -851,7 +852,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutEvent(RTC_TypeDef *RTCx, uint32_t AlarmOu * @arg @ref LL_RTC_ALARMOUT_ALMB * @arg @ref LL_RTC_ALARMOUT_WAKEUP */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutEvent(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_OSEL)); } @@ -878,7 +879,7 @@ __STATIC_INLINE void LL_RTC_SetAlarmOutputType(RTC_TypeDef *RTCx, uint32_t Outpu * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_OPENDRAIN * @arg @ref LL_RTC_ALARM_OUTPUTTYPE_PUSHPULL */ -__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAlarmOutputType(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_TYPE)); } @@ -937,7 +938,7 @@ __STATIC_INLINE void LL_RTC_SetBinaryMode(RTC_TypeDef *RTCx, uint32_t BinaryMode * @arg @ref LL_RTC_BINARY_MIX * @retval None */ -__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBinaryMode(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BIN)); } @@ -979,7 +980,7 @@ __STATIC_INLINE void LL_RTC_SetBinMixBCDU(RTC_TypeDef *RTCx, uint32_t BinMixBcdU * @arg @ref LL_RTC_BINARY_MIX_BCDU_7 * @retval None */ -__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetBinMixBCDU(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ICSR, RTC_ICSR_BCDU)); } @@ -1007,7 +1008,7 @@ __STATIC_INLINE void LL_RTC_SetOutputPolarity(RTC_TypeDef *RTCx, uint32_t Polari * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_HIGH * @arg @ref LL_RTC_OUTPUTPOLARITY_PIN_LOW */ -__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetOutputPolarity(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_POL)); } @@ -1041,7 +1042,7 @@ __STATIC_INLINE void LL_RTC_DisableShadowRegBypass(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsShadowRegBypassEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BYPSHAD) == (RTC_CR_BYPSHAD)) ? 1U : 0U); } @@ -1102,7 +1103,7 @@ __STATIC_INLINE void LL_RTC_SetSynchPrescaler(RTC_TypeDef *RTCx, uint32_t SynchP * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7F */ -__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_A) >> RTC_PRER_PREDIV_A_Pos); } @@ -1113,7 +1114,7 @@ __STATIC_INLINE uint32_t LL_RTC_GetAsynchPrescaler(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data = 0 and Max_Data = 0x7FFF */ -__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetSynchPrescaler(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->PRER, RTC_PRER_PREDIV_S)); } @@ -1171,7 +1172,7 @@ __STATIC_INLINE void LL_RTC_DisableTamperOutput(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsTamperOutputEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPOE) == (RTC_CR_TAMPOE)) ? 1U : 0U); } @@ -1204,7 +1205,7 @@ __STATIC_INLINE void LL_RTC_DisableAlarmPullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsAlarmPullUpEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TAMPALRM_PU) == (RTC_CR_TAMPALRM_PU)) ? 1U : 0U); } @@ -1240,7 +1241,7 @@ __STATIC_INLINE void LL_RTC_DisableOutput2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsOutput2Enabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_OUT2EN) == (RTC_CR_OUT2EN)) ? 1U : 0U); } @@ -1281,7 +1282,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetFormat(RTC_TypeDef *RTCx, uint32_t TimeForma * @arg @ref LL_RTC_TIME_FORMAT_AM_OR_24 * @arg @ref LL_RTC_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, RTC_TR_PM)); } @@ -1316,7 +1317,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->TR, (RTC_TR_HT | RTC_TR_HU))) >> RTC_TR_HU_Pos); } @@ -1351,7 +1352,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_MNT | RTC_TR_MNU)) >> RTC_TR_MNU_Pos); } @@ -1386,7 +1387,7 @@ __STATIC_INLINE void LL_RTC_TIME_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TR, (RTC_TR_ST | RTC_TR_SU)) >> RTC_TR_SU_Pos); } @@ -1412,7 +1413,8 @@ __STATIC_INLINE uint32_t LL_RTC_TIME_GetSecond(RTC_TypeDef *RTCx) * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None */ -__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +__STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) { uint32_t temp; @@ -1440,7 +1442,7 @@ __STATIC_INLINE void LL_RTC_TIME_Config(RTC_TypeDef *RTCx, uint32_t Format12_24, * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds (Format: 0x00HHMMSS). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1480,7 +1482,7 @@ __STATIC_INLINE void LL_RTC_TIME_DisableDayLightStore(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_IsDayLightStoreEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_BKP) == (RTC_CR_BKP)) ? 1U : 0U); } @@ -1523,7 +1525,7 @@ __STATIC_INLINE void LL_RTC_TIME_IncHour(RTC_TypeDef *RTCx) * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TIME_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->SSR, RTC_SSR_SS)); } @@ -1580,7 +1582,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetYear(RTC_TypeDef *RTCx, uint32_t Year) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x99 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetYear(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_YT | RTC_DR_YU))) >> RTC_DR_YU_Pos); } @@ -1619,7 +1621,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->DR, RTC_DR_WDU) >> RTC_DR_WDU_Pos); } @@ -1673,7 +1675,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetMonth(RTC_TypeDef *RTCx, uint32_t Month) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_MT | RTC_DR_MU))) >> RTC_DR_MU_Pos); } @@ -1703,7 +1705,7 @@ __STATIC_INLINE void LL_RTC_DATE_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->DR, (RTC_DR_DT | RTC_DR_DU))) >> RTC_DR_DU_Pos); } @@ -1743,7 +1745,8 @@ __STATIC_INLINE uint32_t LL_RTC_DATE_GetDay(RTC_TypeDef *RTCx) * @param Year Value between Min_Data=0x00 and Max_Data=0x99 * @retval None */ -__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, uint32_t Year) +__STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uint32_t Day, uint32_t Month, + uint32_t Year) { uint32_t temp; @@ -1771,7 +1774,7 @@ __STATIC_INLINE void LL_RTC_DATE_Config(RTC_TypeDef *RTCx, uint32_t WeekDay, uin * @param RTCx RTC Instance * @retval Combination of WeekDay, Day, Month and Year (Format: 0xWWDDMMYY). */ -__STATIC_INLINE uint32_t LL_RTC_DATE_Get(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_DATE_Get(const RTC_TypeDef *RTCx) { uint32_t temp; @@ -1850,7 +1853,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMA_MASK_SECONDS * @arg @ref LL_RTC_ALMA_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_MSK4 | RTC_ALRMAR_MSK3 | RTC_ALRMAR_MSK2 | RTC_ALRMAR_MSK1)); } @@ -1900,7 +1903,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_DT | RTC_ALRMAR_DU))) >> RTC_ALRMAR_DU_Pos); } @@ -1937,7 +1940,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_DU) >> RTC_ALRMAR_DU_Pos); } @@ -1964,7 +1967,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMA_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMA_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMAR, RTC_ALRMAR_PM)); } @@ -1992,7 +1995,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_HT | RTC_ALRMAR_HU))) >> RTC_ALRMAR_HU_Pos); } @@ -2020,7 +2023,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU))) >> RTC_ALRMAR_MNU_Pos); } @@ -2048,7 +2051,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMAR, (RTC_ALRMAR_ST | RTC_ALRMAR_SU))) >> RTC_ALRMAR_SU_Pos); } @@ -2071,7 +2074,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMA_GetSecond(RTC_TypeDef *RTCx) * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None */ -__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +__STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) { uint32_t temp; @@ -2079,7 +2083,9 @@ __STATIC_INLINE void LL_RTC_ALMA_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 (((Minutes & 0xF0U) << (RTC_ALRMAR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMAR_MNU_Pos)) | \ (((Seconds & 0xF0U) << (RTC_ALRMAR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMAR_SU_Pos)); - MODIFY_REG(RTCx->ALRMAR, RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, temp); + MODIFY_REG(RTCx->ALRMAR, + RTC_ALRMAR_PM | RTC_ALRMAR_HT | RTC_ALRMAR_HU | RTC_ALRMAR_MNT | RTC_ALRMAR_MNU | RTC_ALRMAR_ST | RTC_ALRMAR_SU, + temp); } /** @@ -2122,7 +2128,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF * else Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_MASKSS) >> RTC_ALRMASSR_MASKSS_Pos); } @@ -2151,7 +2157,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t Binar * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_NO * @arg @ref LL_RTC_ALMA_SUBSECONDBIN_AUTOCLR_YES */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetBinAutoClr(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMASSR, RTC_ALRMASSR_SSCLR)); } @@ -2176,7 +2182,7 @@ __STATIC_INLINE void LL_RTC_ALMA_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMA_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRABINR, RTC_ALRABINR_SS)); } @@ -2249,7 +2255,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMask(RTC_TypeDef *RTCx, uint32_t Mask) * @arg @ref LL_RTC_ALMB_MASK_SECONDS * @arg @ref LL_RTC_ALMB_MASK_ALL */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_MSK4 | RTC_ALRMBR_MSK3 | RTC_ALRMBR_MSK2 | RTC_ALRMBR_MSK1)); } @@ -2299,7 +2305,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetDay(RTC_TypeDef *RTCx, uint32_t Day) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_DT | RTC_ALRMBR_DU))) >> RTC_ALRMBR_DU_Pos); } @@ -2336,7 +2342,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetWeekDay(RTC_TypeDef *RTCx, uint32_t WeekDay) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_DU) >> RTC_ALRMBR_DU_Pos); } @@ -2363,7 +2369,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetTimeFormat(RTC_TypeDef *RTCx, uint32_t TimeF * @arg @ref LL_RTC_ALMB_TIME_FORMAT_AM * @arg @ref LL_RTC_ALMB_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBR, RTC_ALRMBR_PM)); } @@ -2391,7 +2397,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetHour(RTC_TypeDef *RTCx, uint32_t Hours) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_HT | RTC_ALRMBR_HU))) >> RTC_ALRMBR_HU_Pos); } @@ -2419,7 +2425,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetMinute(RTC_TypeDef *RTCx, uint32_t Minutes) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_MNT | RTC_ALRMBR_MNU))) >> RTC_ALRMBR_MNU_Pos); } @@ -2447,7 +2453,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSecond(RTC_TypeDef *RTCx, uint32_t Seconds) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)((READ_BIT(RTCx->ALRMBR, (RTC_ALRMBR_ST | RTC_ALRMBR_SU))) >> RTC_ALRMBR_SU_Pos); } @@ -2470,7 +2476,8 @@ __STATIC_INLINE uint32_t LL_RTC_ALMB_GetSecond(RTC_TypeDef *RTCx) * @param Seconds Value between Min_Data=0x00 and Max_Data=0x59 * @retval None */ -__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, uint32_t Seconds) +__STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12_24, uint32_t Hours, uint32_t Minutes, + uint32_t Seconds) { uint32_t temp; @@ -2478,7 +2485,8 @@ __STATIC_INLINE void LL_RTC_ALMB_ConfigTime(RTC_TypeDef *RTCx, uint32_t Format12 (((Minutes & 0xF0U) << (RTC_ALRMBR_MNT_Pos - 4U)) | ((Minutes & 0x0FU) << RTC_ALRMBR_MNU_Pos)) | \ (((Seconds & 0xF0U) << (RTC_ALRMBR_ST_Pos - 4U)) | ((Seconds & 0x0FU) << RTC_ALRMBR_SU_Pos)); - MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST | RTC_ALRMBR_SU, temp); + MODIFY_REG(RTCx->ALRMBR, RTC_ALRMBR_PM | RTC_ALRMBR_HT | RTC_ALRMBR_HU | RTC_ALRMBR_MNT | RTC_ALRMBR_MNU | RTC_ALRMBR_ST + | RTC_ALRMBR_SU, temp); } /** @@ -2521,7 +2529,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecondMask(RTC_TypeDef *RTCx, uint32_t Ma * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0xF * else Value between Min_Data=0x0 and Max_Data=0x3F */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecondMask(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_MASKSS) >> RTC_ALRMBSSR_MASKSS_Pos); } @@ -2550,7 +2558,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetBinAutoClr(RTC_TypeDef *RTCx, uint32_t Binar * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_NO * @arg @ref LL_RTC_ALMB_SUBSECONDBIN_AUTOCLR_YES */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetBinAutoClr(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRMBSSR, RTC_ALRMBSSR_SSCLR)); } @@ -2575,7 +2583,7 @@ __STATIC_INLINE void LL_RTC_ALMB_SetSubSecond(RTC_TypeDef *RTCx, uint32_t Subsec * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_ALMB_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->ALRBBINR, RTC_ALRBBINR_SS)); } @@ -2661,7 +2669,7 @@ __STATIC_INLINE void LL_RTC_TS_SetActiveEdge(RTC_TypeDef *RTCx, uint32_t Edge) * @arg @ref LL_RTC_TIMESTAMP_EDGE_RISING * @arg @ref LL_RTC_TIMESTAMP_EDGE_FALLING */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_TSEDGE)); } @@ -2674,7 +2682,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetActiveEdge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TS_TIME_FORMAT_AM * @arg @ref LL_RTC_TS_TIME_FORMAT_PM */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_PM)); } @@ -2687,7 +2695,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTimeFormat(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x12 or between Min_Data=0x00 and Max_Data=0x23 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetHour(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU) >> RTC_TSTR_HU_Pos); } @@ -2700,7 +2708,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetHour(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_MNT | RTC_TSTR_MNU) >> RTC_TSTR_MNU_Pos); } @@ -2713,7 +2721,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMinute(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0x59 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_ST | RTC_TSTR_SU)); } @@ -2731,7 +2739,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetSecond(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of hours, minutes and seconds. */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetTime(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSTR, RTC_TSTR_HT | RTC_TSTR_HU | RTC_TSTR_MNT | RTC_TSTR_MNU | RTC_TSTR_ST | RTC_TSTR_SU)); @@ -2750,7 +2758,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetTime(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_WEEKDAY_SATURDAY * @arg @ref LL_RTC_WEEKDAY_SUNDAY */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU) >> RTC_TSDR_WDU_Pos); } @@ -2775,7 +2783,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetWeekDay(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_MONTH_NOVEMBER * @arg @ref LL_RTC_MONTH_DECEMBER */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_MT | RTC_TSDR_MU) >> RTC_TSDR_MU_Pos); } @@ -2788,7 +2796,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetMonth(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Value between Min_Data=0x01 and Max_Data=0x31 */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDay(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2805,7 +2813,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDay(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Combination of Weekday, Day and Month */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetDate(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSDR, RTC_TSDR_WDU | RTC_TSDR_MT | RTC_TSDR_MU | RTC_TSDR_DT | RTC_TSDR_DU)); } @@ -2817,7 +2825,7 @@ __STATIC_INLINE uint32_t LL_RTC_TS_GetDate(RTC_TypeDef *RTCx) * @retval If binary mode is none, Value between Min_Data=0x0 and Max_Data=0x7FFF * else Value between Min_Data=0x0 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TS_GetSubSecond(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->TSSSR, RTC_TSSSR_SS)); } @@ -2864,7 +2872,7 @@ __STATIC_INLINE void LL_RTC_TS_DisableOnTamper(RTC_TypeDef *RTCx) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_Enable(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR1, Tamper); @@ -2881,7 +2889,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Enable(RTC_TypeDef *RTCx, uint32_t Tamper) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_Disable(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR1, Tamper); @@ -2899,7 +2907,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_Disable(RTC_TypeDef *RTCx, uint32_t Tamper) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_TAMPER_EnableMask(const RTC_TypeDef *RTCx, uint32_t Mask) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Mask); @@ -2916,7 +2924,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableMask(RTC_TypeDef *RTCx, uint32_t Mask) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) +__STATIC_INLINE void LL_RTC_TAMPER_DisableMask(const RTC_TypeDef *RTCx, uint32_t Mask) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Mask); @@ -2933,7 +2941,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableMask(RTC_TypeDef *RTCx, uint32_t Mask) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Tamper); @@ -2950,7 +2958,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableEraseBKP(RTC_TypeDef *RTCx, uint32_t Ta * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Tamper); @@ -2962,7 +2970,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableEraseBKP(RTC_TypeDef *RTCx, uint32_t T * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); @@ -2974,7 +2982,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisablePullUp(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPUDIS); @@ -2991,7 +2999,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnablePullUp(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Duration) +__STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(const RTC_TypeDef *RTCx, uint32_t Duration) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH, Duration); @@ -3007,7 +3015,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetPrecharge(RTC_TypeDef *RTCx, uint32_t Dura * @arg @ref LL_RTC_TAMPER_DURATION_4RTCCLK * @arg @ref LL_RTC_TAMPER_DURATION_8RTCCLK */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPPRCH)); @@ -3024,7 +3032,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetPrecharge(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t FilterCount) +__STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(const RTC_TypeDef *RTCx, uint32_t FilterCount) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT, FilterCount); @@ -3040,7 +3048,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetFilterCount(RTC_TypeDef *RTCx, uint32_t Fi * @arg @ref LL_RTC_TAMPER_FILTER_4SAMPLE * @arg @ref LL_RTC_TAMPER_FILTER_8SAMPLE */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFLT)); @@ -3061,7 +3069,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetFilterCount(RTC_TypeDef *RTCx) * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t SamplingFreq) +__STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(const RTC_TypeDef *RTCx, uint32_t SamplingFreq) { UNUSED(RTCx); MODIFY_REG(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ, SamplingFreq); @@ -3081,7 +3089,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_SetSamplingFreq(RTC_TypeDef *RTCx, uint32_t S * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_512 * @arg @ref LL_RTC_TAMPER_SAMPLFREQDIV_256 */ -__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return (uint32_t)(READ_BIT(TAMP->FLTCR, TAMP_FLTCR_TAMPFREQ)); @@ -3098,7 +3106,7 @@ __STATIC_INLINE uint32_t LL_RTC_TAMPER_GetSamplingFreq(RTC_TypeDef *RTCx) * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); SET_BIT(TAMP->CR2, Tamper); @@ -3115,7 +3123,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_EnableActiveLevel(RTC_TypeDef *RTCx, uint32_t * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_t Tamper) +__STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(const RTC_TypeDef *RTCx, uint32_t Tamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR2, Tamper); @@ -3143,7 +3151,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_DisableActiveLevel(RTC_TypeDef *RTCx, uint32_ * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) { UNUSED(RTCx); SET_BIT(TAMP->CR1, InternalTamper); @@ -3163,7 +3171,7 @@ __STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Enable(RTC_TypeDef *RTCx, uint32_t Inte * * @retval None */ -__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(RTC_TypeDef *RTCx, uint32_t InternalTamper) +__STATIC_INLINE void LL_RTC_TAMPER_ITAMP_Disable(const RTC_TypeDef *RTCx, uint32_t InternalTamper) { UNUSED(RTCx); CLEAR_BIT(TAMP->CR1, InternalTamper); @@ -3207,7 +3215,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTE) == (RTC_CR_WUTE)) ? 1U : 0U); } @@ -3244,7 +3252,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetClock(RTC_TypeDef *RTCx, uint32_t WakeupCl * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE * @arg @ref LL_RTC_WAKEUPCLOCK_CKSPRE_WUT */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetClock(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_WUCKSEL)); } @@ -3268,7 +3276,7 @@ __STATIC_INLINE void LL_RTC_WAKEUP_SetAutoReload(RTC_TypeDef *RTCx, uint32_t Val * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data=0xFFFF */ -__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->WUTR, RTC_WUTR_WUT)); } @@ -3309,7 +3317,7 @@ __STATIC_INLINE uint32_t LL_RTC_WAKEUP_GetAutoReload(RTC_TypeDef *RTCx) * @param Data Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF * @retval None */ -__STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) +__STATIC_INLINE void LL_RTC_BKP_SetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister, uint32_t Data) { uint32_t tmp; @@ -3349,7 +3357,7 @@ __STATIC_INLINE void LL_RTC_BKP_SetRegister(RTC_TypeDef *RTCx, uint32_t BackupRe * @arg @ref LL_RTC_BKP_DR19 * @retval Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF */ -__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(RTC_TypeDef *RTCx, uint32_t BackupRegister) +__STATIC_INLINE uint32_t LL_RTC_BKP_GetRegister(const RTC_TypeDef *RTCx, uint32_t BackupRegister) { uint32_t tmp; @@ -3397,7 +3405,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetOutputFreq(RTC_TypeDef *RTCx, uint32_t Freque * @arg @ref LL_RTC_CALIB_OUTPUT_1HZ * @arg @ref LL_RTC_CALIB_OUTPUT_512HZ */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetOutputFreq(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CR, RTC_CR_COE | RTC_CR_COSEL)); } @@ -3424,7 +3432,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPulse(RTC_TypeDef *RTCx, uint32_t Pulse) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_IsPulseInserted(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_CALP) == (RTC_CALR_CALP)) ? 1U : 0U); } @@ -3457,7 +3465,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetPeriod(RTC_TypeDef *RTCx, uint32_t Period) * @arg @ref LL_RTC_CALIB_PERIOD_16SEC * @arg @ref LL_RTC_CALIB_PERIOD_8SEC */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetPeriod(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALW8 | RTC_CALR_CALW16)); } @@ -3482,7 +3490,7 @@ __STATIC_INLINE void LL_RTC_CAL_SetMinus(RTC_TypeDef *RTCx, uint32_t CalibMinus) * @param RTCx RTC Instance * @retval Value between Min_Data=0x00 and Max_Data= 0x1FF */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_GetMinus(const RTC_TypeDef *RTCx) { return (uint32_t)(READ_BIT(RTCx->CALR, RTC_CALR_CALM)); } @@ -3519,7 +3527,7 @@ __STATIC_INLINE void LL_RTC_CAL_LowPower_Disable(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CALR, RTC_CALR_LPCAL) == (RTC_CALR_LPCAL)) ? 1U : 0U); } @@ -3538,7 +3546,7 @@ __STATIC_INLINE uint32_t LL_RTC_CAL_LowPower_IsEnabled(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ITSF) == (RTC_SR_ITSF)) ? 1U : 0U); } @@ -3549,7 +3557,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RECALPF) == (RTC_ICSR_RECALPF)) ? 1U : 0U); } @@ -3560,7 +3568,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RECALP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSOVF) == (RTC_SR_TSOVF)) ? 1U : 0U); } @@ -3571,7 +3579,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOV(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_TSF) == (RTC_SR_TSF)) ? 1U : 0U); } @@ -3582,7 +3590,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_WUTF) == (RTC_SR_WUTF)) ? 1U : 0U); } @@ -3593,7 +3601,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRBF) == (RTC_SR_ALRBF)) ? 1U : 0U); } @@ -3604,7 +3612,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_ALRAF) == (RTC_SR_ALRAF)) ? 1U : 0U); } @@ -3615,7 +3623,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRU(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->SR, RTC_SR_SSRUF) == (RTC_SR_SSRUF)) ? 1U : 0U); } @@ -3703,7 +3711,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_SSRU(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITF) == (RTC_ICSR_INITF)) ? 1U : 0U); } @@ -3714,7 +3722,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INIT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_RSF) == (RTC_ICSR_RSF)) ? 1U : 0U); } @@ -3736,7 +3744,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_INITS) == (RTC_ICSR_INITS)) ? 1U : 0U); } @@ -3747,7 +3755,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_INITS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_SHPF) == (RTC_ICSR_SHPF)) ? 1U : 0U); } @@ -3758,7 +3766,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SHP(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->ICSR, RTC_ICSR_WUTWF) == (RTC_ICSR_WUTWF)) ? 1U : 0U); } @@ -3769,7 +3777,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTW(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRAMF) == (RTC_MISR_ALRAMF)) ? 1U : 0U); } @@ -3780,7 +3788,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRAM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_SSRUMF) == (RTC_MISR_SSRUMF)) ? 1U : 0U); } @@ -3791,7 +3799,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SSRUM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ALRBMF) == (RTC_MISR_ALRBMF)) ? 1U : 0U); } @@ -3802,7 +3810,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALRBM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_WUTMF) == (RTC_MISR_WUTMF)) ? 1U : 0U); } @@ -3813,7 +3821,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_WUTM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSMF) == (RTC_MISR_TSMF)) ? 1U : 0U); } @@ -3824,7 +3832,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_TSOVMF) == (RTC_MISR_TSOVMF)) ? 1U : 0U); } @@ -3835,7 +3843,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TSOVM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->MISR, RTC_MISR_ITSMF) == (RTC_MISR_ITSMF)) ? 1U : 0U); } @@ -3846,7 +3854,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITSM(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP1F) == (TAMP_SR_TAMP1F)) ? 1U : 0U); @@ -3858,7 +3866,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP2F) == (TAMP_SR_TAMP2F)) ? 1U : 0U); @@ -3870,7 +3878,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_TAMP3F) == (TAMP_SR_TAMP3F)) ? 1U : 0U); @@ -3881,7 +3889,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP3F) == (TAMP_SR_ITAMP3F)) ? 1U : 0U); @@ -3894,7 +3902,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP5F) == (TAMP_SR_ITAMP5F)) ? 1U : 0U); @@ -3906,7 +3914,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP6F) == (TAMP_SR_ITAMP6F)) ? 1U : 0U); @@ -3918,7 +3926,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->SR, TAMP_SR_ITAMP8F) == (TAMP_SR_ITAMP8F)) ? 1U : 0U); @@ -3930,7 +3938,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP1MF) == (TAMP_MISR_TAMP1MF)) ? 1U : 0U); @@ -3942,7 +3950,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP1M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP2MF) == (TAMP_MISR_TAMP2MF)) ? 1U : 0U); @@ -3954,7 +3962,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP2M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_TAMP3MF) == (TAMP_MISR_TAMP3MF)) ? 1U : 0U); @@ -3966,7 +3974,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_TAMP3M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP3MF) == (TAMP_MISR_ITAMP3MF)) ? 1U : 0U); @@ -3978,7 +3986,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP3M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP5MF) == (TAMP_MISR_ITAMP5MF)) ? 1U : 0U); @@ -3990,7 +3998,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP5M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP6MF) == (TAMP_MISR_ITAMP6MF)) ? 1U : 0U); @@ -4002,7 +4010,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP6M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->MISR, TAMP_MISR_ITAMP8MF) == (TAMP_MISR_ITAMP8MF)) ? 1U : 0U); @@ -4014,7 +4022,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ITAMP8M(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP1F); @@ -4026,7 +4034,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP2F); @@ -4038,7 +4046,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CTAMP3F); @@ -4051,7 +4059,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP3F); @@ -4063,7 +4071,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP5F); @@ -4075,7 +4083,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP6F); @@ -4087,7 +4095,7 @@ __STATIC_INLINE void LL_RTC_ClearFlag_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_ClearFlag_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->SCR, TAMP_SCR_CITAMP8F); @@ -4227,7 +4235,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_SSRU(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_TSIE) == (RTC_CR_TSIE)) ? 1U : 0U); } @@ -4238,7 +4246,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TS(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_WUTIE) == (RTC_CR_WUTIE)) ? 1U : 0U); } @@ -4249,7 +4257,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_WUT(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRBIE) == (RTC_CR_ALRBIE)) ? 1U : 0U); } @@ -4260,7 +4268,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRB(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_ALRAIE) == (RTC_CR_ALRAIE)) ? 1U : 0U); } @@ -4271,7 +4279,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALRA(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(const RTC_TypeDef *RTCx) { return ((READ_BIT(RTCx->CR, RTC_CR_SSRUIE) == (RTC_CR_SSRUIE)) ? 1U : 0U); } @@ -4282,7 +4290,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SSRU(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP1IE); @@ -4294,7 +4302,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP1IE); @@ -4306,7 +4314,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP2IE); @@ -4318,7 +4326,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP2IE); @@ -4330,7 +4338,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_TAMP3IE); @@ -4341,7 +4349,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_TAMP3IE); @@ -4353,7 +4361,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); @@ -4364,7 +4372,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP3IE); @@ -4376,7 +4384,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); @@ -4387,7 +4395,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP5IE); @@ -4399,7 +4407,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); @@ -4411,7 +4419,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP6IE); @@ -4423,7 +4431,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); SET_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); @@ -4435,7 +4443,7 @@ __STATIC_INLINE void LL_RTC_EnableIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None */ -__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); CLEAR_BIT(TAMP->IER, TAMP_IER_ITAMP8IE); @@ -4447,7 +4455,7 @@ __STATIC_INLINE void LL_RTC_DisableIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP1IE) == (TAMP_IER_TAMP1IE)) ? 1U : 0U); @@ -4459,7 +4467,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP1(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP2IE) == (TAMP_IER_TAMP2IE)) ? 1U : 0U); @@ -4471,7 +4479,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP2(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_TAMP3IE) == (TAMP_IER_TAMP3IE)) ? 1U : 0U); @@ -4483,7 +4491,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_TAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP3IE) == (TAMP_IER_ITAMP3IE)) ? 1U : 0U); @@ -4495,7 +4503,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP3(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP5IE) == (TAMP_IER_ITAMP5IE)) ? 1U : 0U); @@ -4507,7 +4515,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP5(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP6IE) == (TAMP_IER_ITAMP6IE)) ? 1U : 0U); @@ -4519,7 +4527,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP6(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return ((READ_BIT(TAMP->IER, TAMP_IER_ITAMP8IE) == (TAMP_IER_ITAMP8IE)) ? 1U : 0U); @@ -4532,7 +4540,7 @@ __STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ITAMP8(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval None. */ -__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) +__STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(const RTC_TypeDef *RTCx) { UNUSED(RTCx); WRITE_REG(TAMP->COUNTR, 0u); @@ -4544,7 +4552,7 @@ __STATIC_INLINE void LL_RTC_IncrementMonotonicCounter(RTC_TypeDef *RTCx) * @param RTCx RTC Instance * @retval Monotonic counter value. */ -__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(RTC_TypeDef *RTCx) +__STATIC_INLINE uint32_t LL_RTC_GetMonotonicCounter(const RTC_TypeDef *RTCx) { UNUSED(RTCx); return READ_REG(TAMP->COUNTR); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h index 61560af5e6..f943cc04df 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_spi.h @@ -55,53 +55,66 @@ typedef struct uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferDirection().*/ uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). This parameter can be a value of @ref SPI_LL_EC_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetMode().*/ uint32_t DataWidth; /*!< Specifies the SPI data width. This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetDataWidth().*/ uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. This parameter can be a value of @ref SPI_LL_EC_POLARITY. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPolarity().*/ uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. This parameter can be a value of @ref SPI_LL_EC_PHASE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetClockPhase().*/ - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) + or by software using the SSI bit. This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetNSSMode().*/ - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used + to configure the transmit and receive SCK clock. This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. + @note The communication clock is derived from the master clock. + The slave clock does not need to be set. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetBaudRatePrescaler().*/ uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetTransferBitOrder().*/ uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not. This parameter can be a value of @ref SPI_LL_EC_CRC_CALCULATION. - This feature can be modified afterwards using unitary functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ + This feature can be modified afterwards using unitary + functions @ref LL_SPI_EnableCRC() and @ref LL_SPI_DisableCRC().*/ uint32_t CRCPoly; /*!< Specifies the polynomial used for the CRC calculation. This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFF. - This feature can be modified afterwards using unitary function @ref LL_SPI_SetCRCPolynomial().*/ + This feature can be modified afterwards using unitary + function @ref LL_SPI_SetCRCPolynomial().*/ } LL_SPI_InitTypeDef; @@ -378,7 +391,7 @@ __STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); } @@ -408,7 +421,7 @@ __STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_SPI_MODE_MASTER * @arg @ref LL_SPI_MODE_SLAVE */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); } @@ -436,7 +449,7 @@ __STATIC_INLINE void LL_SPI_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_SPI_PROTOCOL_MOTOROLA * @arg @ref LL_SPI_PROTOCOL_TI */ -__STATIC_INLINE uint32_t LL_SPI_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRF)); } @@ -465,7 +478,7 @@ __STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase * @arg @ref LL_SPI_PHASE_1EDGE * @arg @ref LL_SPI_PHASE_2EDGE */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); } @@ -494,7 +507,7 @@ __STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_SPI_POLARITY_LOW * @arg @ref LL_SPI_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); } @@ -534,7 +547,7 @@ __STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t Bau * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); } @@ -562,7 +575,7 @@ __STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitO * @arg @ref LL_SPI_LSB_FIRST * @arg @ref LL_SPI_MSB_FIRST */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); } @@ -599,7 +612,7 @@ __STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t Tra * @arg @ref LL_SPI_HALF_DUPLEX_RX * @arg @ref LL_SPI_HALF_DUPLEX_TX */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); } @@ -648,7 +661,7 @@ __STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) * @arg @ref LL_SPI_DATAWIDTH_15BIT * @arg @ref LL_SPI_DATAWIDTH_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); } @@ -675,7 +688,7 @@ __STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Thres * @arg @ref LL_SPI_RX_FIFO_TH_HALF * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); } @@ -719,7 +732,7 @@ __STATIC_INLINE void LL_SPI_DisableCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledCRC(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR1, SPI_CR1_CRCEN) == (SPI_CR1_CRCEN)) ? 1UL : 0UL); } @@ -747,7 +760,7 @@ __STATIC_INLINE void LL_SPI_SetCRCWidth(SPI_TypeDef *SPIx, uint32_t CRCLength) * @arg @ref LL_SPI_CRC_8BIT * @arg @ref LL_SPI_CRC_16BIT */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCWidth(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CRCL)); } @@ -782,7 +795,7 @@ __STATIC_INLINE void LL_SPI_SetCRCPolynomial(SPI_TypeDef *SPIx, uint32_t CRCPoly * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->CRCPR)); } @@ -793,7 +806,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetCRCPolynomial(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->RXCRCR)); } @@ -804,7 +817,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxCRC(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Returned value is a number between Min_Data = 0x00 and Max_Data = 0xFFFF */ -__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxCRC(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_REG(SPIx->TXCRCR)); } @@ -845,7 +858,7 @@ __STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) * @arg @ref LL_SPI_NSS_HARD_INPUT * @arg @ref LL_SPI_NSS_HARD_OUTPUT */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(const SPI_TypeDef *SPIx) { uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); @@ -883,7 +896,7 @@ __STATIC_INLINE void LL_SPI_DisableNSSPulseMgt(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_NSSP) == (SPI_CR2_NSSP)) ? 1UL : 0UL); } @@ -902,7 +915,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledNSSPulse(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); } @@ -913,7 +926,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); } @@ -924,7 +937,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CRCERR) == (SPI_SR_CRCERR)) ? 1UL : 0UL); } @@ -935,7 +948,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_CRCERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); } @@ -946,7 +959,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); } @@ -964,7 +977,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); } @@ -975,7 +988,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_FRE) == (SPI_SR_FRE)) ? 1UL : 0UL); } @@ -990,7 +1003,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_RX_FIFO_HALF_FULL * @arg @ref LL_SPI_RX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); } @@ -1005,7 +1018,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) * @arg @ref LL_SPI_TX_FIFO_HALF_FULL * @arg @ref LL_SPI_TX_FIFO_FULL */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); } @@ -1045,7 +1058,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->DR; @@ -1061,7 +1074,7 @@ __STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_SPI_ClearFlag_FRE(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -1078,7 +1091,8 @@ __STATIC_INLINE void LL_SPI_ClearFlag_FRE(SPI_TypeDef *SPIx) /** * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1112,7 +1126,8 @@ __STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) /** * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @note This bit controls the generation of an interrupt when an error condition + * occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR * @param SPIx SPI Instance * @retval None @@ -1150,7 +1165,7 @@ __STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); } @@ -1161,7 +1176,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); } @@ -1172,7 +1187,7 @@ __STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); } @@ -1213,7 +1228,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); } @@ -1246,7 +1261,7 @@ __STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); } @@ -1273,7 +1288,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMARX) >> SPI_CR2_LDMARX_Pos); } @@ -1300,7 +1315,7 @@ __STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) * @arg @ref LL_SPI_DMA_PARITY_ODD * @arg @ref LL_SPI_DMA_PARITY_EVEN */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMATX) >> SPI_CR2_LDMATX_Pos); } @@ -1311,7 +1326,7 @@ __STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval Address of data register */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(const SPI_TypeDef *SPIx) { return (uint32_t) &(SPIx->DR); } @@ -1388,7 +1403,7 @@ __STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); @@ -1655,7 +1670,7 @@ __STATIC_INLINE void LL_I2S_Disable(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabled(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabled(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SE) == (SPI_I2SCFGR_I2SE)) ? 1UL : 0UL); } @@ -1688,7 +1703,7 @@ __STATIC_INLINE void LL_I2S_SetDataFormat(SPI_TypeDef *SPIx, uint32_t DataFormat * @arg @ref LL_I2S_DATAFORMAT_24B * @arg @ref LL_I2S_DATAFORMAT_32B */ -__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetDataFormat(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)); } @@ -1715,7 +1730,7 @@ __STATIC_INLINE void LL_I2S_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPo * @arg @ref LL_I2S_POLARITY_LOW * @arg @ref LL_I2S_POLARITY_HIGH */ -__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetClockPolarity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_CKPOL)); } @@ -1750,7 +1765,7 @@ __STATIC_INLINE void LL_I2S_SetStandard(SPI_TypeDef *SPIx, uint32_t Standard) * @arg @ref LL_I2S_STANDARD_PCM_SHORT * @arg @ref LL_I2S_STANDARD_PCM_LONG */ -__STATIC_INLINE uint32_t LL_I2S_GetStandard(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetStandard(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SSTD | SPI_I2SCFGR_PCMSYNC)); } @@ -1781,7 +1796,7 @@ __STATIC_INLINE void LL_I2S_SetTransferMode(SPI_TypeDef *SPIx, uint32_t Mode) * @arg @ref LL_I2S_MODE_MASTER_TX * @arg @ref LL_I2S_MODE_MASTER_RX */ -__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetTransferMode(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_I2SCFG)); } @@ -1804,7 +1819,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerLinear(SPI_TypeDef *SPIx, uint8_t Presca * @param SPIx SPI Instance * @retval PrescalerLinear Value between Min_Data=0x02 and Max_Data=0xFF */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerLinear(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_I2SDIV)); } @@ -1831,7 +1846,7 @@ __STATIC_INLINE void LL_I2S_SetPrescalerParity(SPI_TypeDef *SPIx, uint32_t Presc * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD */ -__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_GetPrescalerParity(const SPI_TypeDef *SPIx) { return (uint32_t)(READ_BIT(SPIx->I2SPR, SPI_I2SPR_ODD) >> 8U); } @@ -1864,7 +1879,7 @@ __STATIC_INLINE void LL_I2S_DisableMasterClock(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledMasterClock(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SPR, SPI_I2SPR_MCKOE) == (SPI_I2SPR_MCKOE)) ? 1UL : 0UL); } @@ -1898,7 +1913,7 @@ __STATIC_INLINE void LL_I2S_DisableAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->I2SCFGR, SPI_I2SCFGR_ASTRTEN) == (SPI_I2SCFGR_ASTRTEN)) ? 1UL : 0UL); } @@ -1918,7 +1933,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledAsyncStart(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_RXNE(SPIx); } @@ -1929,7 +1944,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_TXE(SPIx); } @@ -1940,7 +1955,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_BSY(SPIx); } @@ -1951,7 +1966,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_BSY(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_OVR(SPIx); } @@ -1962,7 +1977,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_UDR) == (SPI_SR_UDR)) ? 1UL : 0UL); } @@ -1973,7 +1988,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(const SPI_TypeDef *SPIx) { return LL_SPI_IsActiveFlag_FRE(SPIx); } @@ -1987,7 +2002,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_FRE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsActiveFlag_CHSIDE(const SPI_TypeDef *SPIx) { return ((READ_BIT(SPIx->SR, SPI_SR_CHSIDE) == (SPI_SR_CHSIDE)) ? 1UL : 0UL); } @@ -2009,7 +2024,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_OVR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_UDR(const SPI_TypeDef *SPIx) { __IO uint32_t tmpreg; tmpreg = SPIx->SR; @@ -2022,7 +2037,7 @@ __STATIC_INLINE void LL_I2S_ClearFlag_UDR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval None */ -__STATIC_INLINE void LL_I2S_ClearFlag_FRE(SPI_TypeDef *SPIx) +__STATIC_INLINE void LL_I2S_ClearFlag_FRE(const SPI_TypeDef *SPIx) { LL_SPI_ClearFlag_FRE(SPIx); } @@ -2109,7 +2124,7 @@ __STATIC_INLINE void LL_I2S_DisableIT_TXE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_ERR(SPIx); } @@ -2120,7 +2135,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_ERR(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_RXNE(SPIx); } @@ -2131,7 +2146,7 @@ __STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledIT_TXE(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledIT_TXE(SPIx); } @@ -2172,7 +2187,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_RX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_RX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_RX(SPIx); } @@ -2205,7 +2220,7 @@ __STATIC_INLINE void LL_I2S_DisableDMAReq_TX(SPI_TypeDef *SPIx) * @param SPIx SPI Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +__STATIC_INLINE uint32_t LL_I2S_IsEnabledDMAReq_TX(const SPI_TypeDef *SPIx) { return LL_SPI_IsEnabledDMAReq_TX(SPIx); } @@ -2250,7 +2265,7 @@ __STATIC_INLINE void LL_I2S_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) * @{ */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_I2S_DeInit(const SPI_TypeDef *SPIx); ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct); void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h index d67e3de51c..9fcd9a56ef 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_system.h @@ -62,8 +62,8 @@ extern "C" { #define LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT 16U /*!< Define used to shift pin position in EXTICR register */ /** - * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values - */ + * @brief VREFBUF VREF_SC0 & VREF_SC1 calibration values + */ #define VREFBUF_SC0_CAL_ADDR ((uint8_t*) (0x1FFF75F0UL)) /*!< Address of VREFBUF trimming value for VRS=0, VREF_SC0 in STM32WL datasheet */ #define VREFBUF_SC1_CAL_ADDR ((uint8_t*) (0x1FFF7530UL)) /*!< Address of VREFBUF trimming value for VRS=1, @@ -81,8 +81,8 @@ extern "C" { */ /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP -* @{ -*/ + * @{ + */ #define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ @@ -591,7 +591,8 @@ __STATIC_INLINE uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line) #if defined(CORE_CM0PLUS) return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (SYSCFG_EXTICR1_EXTI0 << ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL))) >> ((Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT) & 12UL)); #else - return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)); + return (uint32_t)(READ_BIT(SYSCFG->EXTICR[Line & 0x03U], + (Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)) >> POSITION_VAL(Line >> LL_SYSCFG_EXTI_REGISTER_PINPOS_SHFT)); #endif } diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_tim.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_tim.h index f9cea59480..94f7cfd8fb 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_tim.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_tim.h @@ -664,10 +664,10 @@ typedef struct /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode * @{ */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!> 16U) >> TIM_CCMR1_IC1PSC_Pos))) -/** - * @} - */ - - /** * @} */ @@ -1853,6 +1867,17 @@ __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); } +/** + * @brief Indicates whether the capture/compare control bits (CCxE, CCxNE and OCxM) preload is enabled. + * @rmtoll CR2 CCPC LL_TIM_CC_IsEnabledPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledPreload(const TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_CCPC) == (TIM_CR2_CCPC)) ? 1UL : 0UL); +} + /** * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check @@ -1997,7 +2022,7 @@ __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(const TIM_TypeDef *TIMx, uint32_t Channels) { return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); } @@ -2083,8 +2108,8 @@ __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 * @retval None */ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) @@ -2123,8 +2148,8 @@ __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1 - * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM1 + * @arg @ref LL_TIM_OCMODE_ASYMMETRIC_PWM2 */ __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(const TIM_TypeDef *TIMx, uint32_t Channel) { @@ -2338,7 +2363,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2414,7 +2439,7 @@ __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channe * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -2499,7 +2524,7 @@ __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) * @arg @ref LL_TIM_CHANNEL_CH6 * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(const TIM_TypeDef *TIMx, uint32_t Channel) { uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); @@ -3048,7 +3073,7 @@ __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) * @param TIMx Timer instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(const TIM_TypeDef *TIMx) { return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); } @@ -3498,18 +3523,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); } -/** - * @brief Re-arm the break input (when it operates in bidirectional mode). - * @note The Break input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BKDSRM LL_TIM_ReArmBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKDSRM); -} - /** * @brief Enable the break 2 function. * @note Macro IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not @@ -3599,18 +3612,6 @@ __STATIC_INLINE void LL_TIM_DisarmBRK2(TIM_TypeDef *TIMx) SET_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); } -/** - * @brief Re-arm the break 2 input (when it operates in bidirectional mode). - * @note The Break 2 input is automatically armed as soon as MOE bit is set. - * @rmtoll BDTR BK2DSRM LL_TIM_ReArmBRK2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ReArmBRK2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2DSRM); -} - /** * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not @@ -4936,7 +4937,7 @@ __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx) * @{ */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +ErrorStatus LL_TIM_DeInit(const TIM_TypeDef *TIMx); void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, const LL_TIM_InitTypeDef *TIM_InitStruct); void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h index 977fec880e..766dad6dd7 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_usart.h @@ -31,7 +31,7 @@ extern "C" { * @{ */ -#if defined (USART1) || defined (USART2) +#if defined(USART1) || defined(USART2) /** @defgroup USART_LL USART * @{ @@ -63,6 +63,12 @@ static const uint32_t USART_PRESCALER_TAB[] = */ /* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ +/** + * @} + */ /* Private macros ------------------------------------------------------------*/ #if defined(USE_FULL_LL_DRIVER) /** @defgroup USART_LL_Private_Macros USART Private Macros @@ -183,21 +189,21 @@ typedef struct * @brief Flags defines which can be used with LL_USART_WriteReg function * @{ */ -#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error flag */ -#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error flag */ -#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected flag */ -#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error flag */ -#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected flag */ -#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty Clear flag */ -#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete flag */ -#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time flag */ -#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection flag */ -#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS flag */ -#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout flag */ -#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block flag */ -#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun Clear flag */ -#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match flag */ -#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode flag */ +#define LL_USART_ICR_PECF USART_ICR_PECF /*!< Parity error clear flag */ +#define LL_USART_ICR_FECF USART_ICR_FECF /*!< Framing error clear flag */ +#define LL_USART_ICR_NECF USART_ICR_NECF /*!< Noise error detected clear flag */ +#define LL_USART_ICR_ORECF USART_ICR_ORECF /*!< Overrun error clear flag */ +#define LL_USART_ICR_IDLECF USART_ICR_IDLECF /*!< Idle line detected clear flag */ +#define LL_USART_ICR_TXFECF USART_ICR_TXFECF /*!< TX FIFO Empty clear flag */ +#define LL_USART_ICR_TCCF USART_ICR_TCCF /*!< Transmission complete clear flag */ +#define LL_USART_ICR_TCBGTCF USART_ICR_TCBGTCF /*!< Transmission completed before guard time clear flag */ +#define LL_USART_ICR_LBDCF USART_ICR_LBDCF /*!< LIN break detection clear flag */ +#define LL_USART_ICR_CTSCF USART_ICR_CTSCF /*!< CTS clear flag */ +#define LL_USART_ICR_RTOCF USART_ICR_RTOCF /*!< Receiver timeout clear flag */ +#define LL_USART_ICR_EOBCF USART_ICR_EOBCF /*!< End of block clear flag */ +#define LL_USART_ICR_UDRCF USART_ICR_UDRCF /*!< SPI Slave Underrun clear flag */ +#define LL_USART_ICR_CMCF USART_ICR_CMCF /*!< Character match clear flag */ +#define LL_USART_ICR_WUCF USART_ICR_WUCF /*!< Wakeup from Stop mode clear flag */ /** * @} */ @@ -573,8 +579,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + (((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))*2U)\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @brief Compute USARTDIV value according to Peripheral Clock and @@ -596,8 +603,9 @@ typedef struct * @param __BAUDRATE__ Baud rate value to achieve * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ - + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __PRESCALER__, __BAUDRATE__) \ + ((((__PERIPHCLK__)/(USART_PRESCALER_TAB[(__PRESCALER__)]))\ + + ((__BAUDRATE__)/2U))/(__BAUDRATE__)) /** * @} @@ -655,7 +663,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabled(const USART_TypeDef *USARTx) /** * @brief FIFO Mode Enable - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 FIFOEN LL_USART_EnableFIFO * @param USARTx USART Instance @@ -668,7 +676,7 @@ __STATIC_INLINE void LL_USART_EnableFIFO(USART_TypeDef *USARTx) /** * @brief FIFO Mode Disable - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 FIFOEN LL_USART_DisableFIFO * @param USARTx USART Instance @@ -681,7 +689,7 @@ __STATIC_INLINE void LL_USART_DisableFIFO(USART_TypeDef *USARTx) /** * @brief Indicate if FIFO Mode is enabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 FIFOEN LL_USART_IsEnabledFIFO * @param USARTx USART Instance @@ -694,7 +702,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledFIFO(const USART_TypeDef *USARTx) /** * @brief Configure TX FIFO Threshold - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTCFG LL_USART_SetTXFIFOThreshold * @param USARTx USART Instance @@ -714,7 +722,7 @@ __STATIC_INLINE void LL_USART_SetTXFIFOThreshold(USART_TypeDef *USARTx, uint32_t /** * @brief Return TX FIFO Threshold Configuration - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTCFG LL_USART_GetTXFIFOThreshold * @param USARTx USART Instance @@ -733,7 +741,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTXFIFOThreshold(const USART_TypeDef *USARTx /** * @brief Configure RX FIFO Threshold - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTCFG LL_USART_SetRXFIFOThreshold * @param USARTx USART Instance @@ -753,7 +761,7 @@ __STATIC_INLINE void LL_USART_SetRXFIFOThreshold(USART_TypeDef *USARTx, uint32_t /** * @brief Return RX FIFO Threshold Configuration - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTCFG LL_USART_GetRXFIFOThreshold * @param USARTx USART Instance @@ -772,7 +780,7 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx /** * @brief Configure TX and RX FIFOs Threshold - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTCFG LL_USART_ConfigFIFOsThreshold\n * CR3 RXFTCFG LL_USART_ConfigFIFOsThreshold @@ -795,15 +803,15 @@ __STATIC_INLINE uint32_t LL_USART_GetRXFIFOThreshold(const USART_TypeDef *USARTx */ __STATIC_INLINE void LL_USART_ConfigFIFOsThreshold(USART_TypeDef *USARTx, uint32_t TXThreshold, uint32_t RXThreshold) { - ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, - (TXThreshold << USART_CR3_TXFTCFG_Pos) | (RXThreshold << USART_CR3_RXFTCFG_Pos)); + ATOMIC_MODIFY_REG(USARTx->CR3, USART_CR3_TXFTCFG | USART_CR3_RXFTCFG, (TXThreshold << USART_CR3_TXFTCFG_Pos) | + (RXThreshold << USART_CR3_RXFTCFG_Pos)); } /** * @brief USART enabled in STOP Mode. * @note When this function is enabled, USART is able to wake up the MCU from Stop mode, provided that * USART clock selection is HSI or LSE in RCC. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_EnableInStopMode * @param USARTx USART Instance @@ -817,7 +825,7 @@ __STATIC_INLINE void LL_USART_EnableInStopMode(USART_TypeDef *USARTx) /** * @brief USART disabled in STOP Mode. * @note When this function is disabled, USART is not able to wake up the MCU from Stop mode - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_DisableInStopMode * @param USARTx USART Instance @@ -830,7 +838,7 @@ __STATIC_INLINE void LL_USART_DisableInStopMode(USART_TypeDef *USARTx) /** * @brief Indicate if USART is enabled in STOP Mode (able to wake up MCU from Stop mode or not) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR1 UESM LL_USART_IsEnabledInStopMode * @param USARTx USART Instance @@ -1073,7 +1081,7 @@ __STATIC_INLINE uint32_t LL_USART_GetOverSampling(const USART_TypeDef *USARTx) /** * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput * @param USARTx USART Instance @@ -1090,7 +1098,7 @@ __STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint3 /** * @brief Retrieve Clock pulse of the last data bit output configuration * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput * @param USARTx USART Instance @@ -1105,7 +1113,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(const USART_TypeDef *USA /** * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_SetClockPhase * @param USARTx USART Instance @@ -1121,7 +1129,7 @@ __STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t Cloc /** * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPHA LL_USART_GetClockPhase * @param USARTx USART Instance @@ -1136,7 +1144,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPhase(const USART_TypeDef *USARTx) /** * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_SetClockPolarity * @param USARTx USART Instance @@ -1152,7 +1160,7 @@ __STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t C /** * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CPOL LL_USART_GetClockPolarity * @param USARTx USART Instance @@ -1167,7 +1175,7 @@ __STATIC_INLINE uint32_t LL_USART_GetClockPolarity(const USART_TypeDef *USARTx) /** * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function @@ -1195,7 +1203,7 @@ __STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, /** * @brief Configure Clock source prescaler for baudrate generator and oversampling - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll PRESC PRESCALER LL_USART_SetPrescaler * @param USARTx USART Instance @@ -1221,7 +1229,7 @@ __STATIC_INLINE void LL_USART_SetPrescaler(USART_TypeDef *USARTx, uint32_t Presc /** * @brief Retrieve the Clock source prescaler for baudrate generator and oversampling - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll PRESC PRESCALER LL_USART_GetPrescaler * @param USARTx USART Instance @@ -1246,7 +1254,7 @@ __STATIC_INLINE uint32_t LL_USART_GetPrescaler(const USART_TypeDef *USARTx) /** * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput * @param USARTx USART Instance @@ -1259,7 +1267,7 @@ __STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput * @param USARTx USART Instance @@ -1272,7 +1280,7 @@ __STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) /** * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput * @param USARTx USART Instance @@ -1491,7 +1499,7 @@ __STATIC_INLINE uint32_t LL_USART_GetTransferBitOrder(const USART_TypeDef *USART /** * @brief Enable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_EnableAutoBaudRate * @param USARTx USART Instance @@ -1504,7 +1512,7 @@ __STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Disable Auto Baud-Rate Detection - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_DisableAutoBaudRate * @param USARTx USART Instance @@ -1517,7 +1525,7 @@ __STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) /** * @brief Indicate if Auto Baud-Rate Detection mechanism is enabled - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABREN LL_USART_IsEnabledAutoBaud * @param USARTx USART Instance @@ -1530,7 +1538,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaud(const USART_TypeDef *USARTx) /** * @brief Set Auto Baud-Rate mode bits - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_SetAutoBaudRateMode * @param USARTx USART Instance @@ -1548,7 +1556,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ /** * @brief Return Auto Baud-Rate mode - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll CR2 ABRMODE LL_USART_GetAutoBaudRateMode * @param USARTx USART Instance @@ -1558,7 +1566,7 @@ __STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_ * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_7F_FRAME * @arg @ref LL_USART_AUTOBAUD_DETECT_ON_55_FRAME */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(const USART_TypeDef *USARTx) { return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ABRMODE)); } @@ -1655,7 +1663,7 @@ __STATIC_INLINE uint32_t LL_USART_GetNodeAddressLen(const USART_TypeDef *USARTx) /** * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1668,7 +1676,7 @@ __STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl * @param USARTx USART Instance @@ -1681,7 +1689,7 @@ __STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1694,7 +1702,7 @@ __STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl * @param USARTx USART Instance @@ -1707,7 +1715,7 @@ __STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) /** * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n * CR3 CTSE LL_USART_SetHWFlowCtrl @@ -1726,7 +1734,7 @@ __STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t Hard /** * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n * CR3 CTSE LL_USART_GetHWFlowCtrl @@ -1810,7 +1818,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledOverrunDetect(const USART_TypeDef *US /** * @brief Select event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_SetWKUPType * @param USARTx USART Instance @@ -1827,7 +1835,7 @@ __STATIC_INLINE void LL_USART_SetWKUPType(USART_TypeDef *USARTx, uint32_t Type) /** * @brief Return event type for Wake UP Interrupt Flag (WUS[1:0] bits) - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUS LL_USART_GetWKUPType * @param USARTx USART Instance @@ -2011,7 +2019,7 @@ __STATIC_INLINE uint32_t LL_USART_GetBlockLength(const USART_TypeDef *USARTx) /** * @brief Enable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_EnableIrda * @param USARTx USART Instance @@ -2024,7 +2032,7 @@ __STATIC_INLINE void LL_USART_EnableIrda(USART_TypeDef *USARTx) /** * @brief Disable IrDA mode - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_DisableIrda * @param USARTx USART Instance @@ -2037,7 +2045,7 @@ __STATIC_INLINE void LL_USART_DisableIrda(USART_TypeDef *USARTx) /** * @brief Indicate if IrDA mode is enabled - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IREN LL_USART_IsEnabledIrda * @param USARTx USART Instance @@ -2050,7 +2058,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIrda(const USART_TypeDef *USARTx) /** * @brief Configure IrDA Power Mode (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_SetIrdaPowerMode * @param USARTx USART Instance @@ -2066,7 +2074,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPowerMode(USART_TypeDef *USARTx, uint32_t P /** * @brief Retrieve IrDA Power Mode configuration (Normal or Low Power) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll CR3 IRLP LL_USART_GetIrdaPowerMode * @param USARTx USART Instance @@ -2082,7 +2090,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPowerMode(const USART_TypeDef *USARTx) /** * @brief Set Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetIrdaPrescaler * @param USARTx USART Instance @@ -2097,7 +2105,7 @@ __STATIC_INLINE void LL_USART_SetIrdaPrescaler(USART_TypeDef *USARTx, uint32_t P /** * @brief Return Irda prescaler value, used for dividing the USART clock source * to achieve the Irda Low Power frequency (8 bits value) - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetIrdaPrescaler * @param USARTx USART Instance @@ -2118,7 +2126,7 @@ __STATIC_INLINE uint32_t LL_USART_GetIrdaPrescaler(const USART_TypeDef *USARTx) /** * @brief Enable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_EnableSmartcardNACK * @param USARTx USART Instance @@ -2131,7 +2139,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Disable Smartcard NACK transmission - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_DisableSmartcardNACK * @param USARTx USART Instance @@ -2144,7 +2152,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcardNACK(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard NACK transmission is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 NACK LL_USART_IsEnabledSmartcardNACK * @param USARTx USART Instance @@ -2157,7 +2165,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcardNACK(const USART_TypeDef *US /** * @brief Enable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_EnableSmartcard * @param USARTx USART Instance @@ -2170,7 +2178,7 @@ __STATIC_INLINE void LL_USART_EnableSmartcard(USART_TypeDef *USARTx) /** * @brief Disable Smartcard mode - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_DisableSmartcard * @param USARTx USART Instance @@ -2183,7 +2191,7 @@ __STATIC_INLINE void LL_USART_DisableSmartcard(USART_TypeDef *USARTx) /** * @brief Indicate if Smartcard mode is enabled - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCEN LL_USART_IsEnabledSmartcard * @param USARTx USART Instance @@ -2196,7 +2204,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSmartcard(const USART_TypeDef *USARTx /** * @brief Set Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note This bit-field specifies the number of retries in transmit and receive, in Smartcard mode. * In transmission mode, it specifies the number of automatic retransmission retries, before @@ -2215,7 +2223,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardAutoRetryCount(USART_TypeDef *USARTx, /** * @brief Return Smartcard Auto-Retry Count value (SCARCNT[2:0] bits) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 SCARCNT LL_USART_GetSmartcardAutoRetryCount * @param USARTx USART Instance @@ -2229,7 +2237,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardAutoRetryCount(const USART_TypeDef /** * @brief Set Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_SetSmartcardPrescaler * @param USARTx USART Instance @@ -2244,7 +2252,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardPrescaler(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard prescaler value, used for dividing the USART clock * source to provide the SMARTCARD Clock (5 bits value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR PSC LL_USART_GetSmartcardPrescaler * @param USARTx USART Instance @@ -2258,7 +2266,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardPrescaler(const USART_TypeDef *USA /** * @brief Set Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_SetSmartcardGuardTime * @param USARTx USART Instance @@ -2273,7 +2281,7 @@ __STATIC_INLINE void LL_USART_SetSmartcardGuardTime(USART_TypeDef *USARTx, uint3 /** * @brief Return Smartcard Guard time value, expressed in nb of baud clocks periods * (GT[7:0] bits : Guard time value) - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll GTPR GT LL_USART_GetSmartcardGuardTime * @param USARTx USART Instance @@ -2294,7 +2302,7 @@ __STATIC_INLINE uint32_t LL_USART_GetSmartcardGuardTime(const USART_TypeDef *USA /** * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex * @param USARTx USART Instance @@ -2307,7 +2315,7 @@ __STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex * @param USARTx USART Instance @@ -2320,7 +2328,7 @@ __STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) /** * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex * @param USARTx USART Instance @@ -2340,7 +2348,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(const USART_TypeDef *USART */ /** * @brief Enable SPI Synchronous Slave mode - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 SLVEN LL_USART_EnableSPISlave * @param USARTx USART Instance @@ -2353,7 +2361,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlave(USART_TypeDef *USARTx) /** * @brief Disable SPI Synchronous Slave mode - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 SLVEN LL_USART_DisableSPISlave * @param USARTx USART Instance @@ -2366,7 +2374,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlave(USART_TypeDef *USARTx) /** * @brief Indicate if SPI Synchronous Slave mode is enabled - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 SLVEN LL_USART_IsEnabledSPISlave * @param USARTx USART Instance @@ -2379,7 +2387,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlave(const USART_TypeDef *USARTx) /** * @brief Enable SPI Slave Selection using NSS input pin - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @note SPI Slave Selection depends on NSS input pin * (The slave is selected when NSS is low and deselected when NSS is high). @@ -2394,7 +2402,7 @@ __STATIC_INLINE void LL_USART_EnableSPISlaveSelect(USART_TypeDef *USARTx) /** * @brief Disable SPI Slave Selection using NSS input pin - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @note SPI Slave will be always selected and NSS input pin will be ignored. * @rmtoll CR2 DIS_NSS LL_USART_DisableSPISlaveSelect @@ -2408,7 +2416,7 @@ __STATIC_INLINE void LL_USART_DisableSPISlaveSelect(USART_TypeDef *USARTx) /** * @brief Indicate if SPI Slave Selection depends on NSS input pin - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll CR2 DIS_NSS LL_USART_IsEnabledSPISlaveSelect * @param USARTx USART Instance @@ -2429,7 +2437,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledSPISlaveSelect(const USART_TypeDef *U /** * @brief Set LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_SetLINBrkDetectionLen * @param USARTx USART Instance @@ -2445,7 +2453,7 @@ __STATIC_INLINE void LL_USART_SetLINBrkDetectionLen(USART_TypeDef *USARTx, uint3 /** * @brief Return LIN Break Detection Length - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDL LL_USART_GetLINBrkDetectionLen * @param USARTx USART Instance @@ -2460,7 +2468,7 @@ __STATIC_INLINE uint32_t LL_USART_GetLINBrkDetectionLen(const USART_TypeDef *USA /** * @brief Enable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_EnableLIN * @param USARTx USART Instance @@ -2473,7 +2481,7 @@ __STATIC_INLINE void LL_USART_EnableLIN(USART_TypeDef *USARTx) /** * @brief Disable LIN mode - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_DisableLIN * @param USARTx USART Instance @@ -2486,7 +2494,7 @@ __STATIC_INLINE void LL_USART_DisableLIN(USART_TypeDef *USARTx) /** * @brief Indicate if LIN mode is enabled - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LINEN LL_USART_IsEnabledLIN * @param USARTx USART Instance @@ -2507,7 +2515,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledLIN(const USART_TypeDef *USARTx) /** * @brief Set DEDT (Driver Enable De-Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_SetDEDeassertionTime * @param USARTx USART Instance @@ -2521,7 +2529,7 @@ __STATIC_INLINE void LL_USART_SetDEDeassertionTime(USART_TypeDef *USARTx, uint32 /** * @brief Return DEDT (Driver Enable De-Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEDT LL_USART_GetDEDeassertionTime * @param USARTx USART Instance @@ -2534,7 +2542,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEDeassertionTime(const USART_TypeDef *USAR /** * @brief Set DEAT (Driver Enable Assertion Time), Time value expressed on 5 bits ([4:0] bits). - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_SetDEAssertionTime * @param USARTx USART Instance @@ -2548,7 +2556,7 @@ __STATIC_INLINE void LL_USART_SetDEAssertionTime(USART_TypeDef *USARTx, uint32_t /** * @brief Return DEAT (Driver Enable Assertion Time) - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR1 DEAT LL_USART_GetDEAssertionTime * @param USARTx USART Instance @@ -2561,7 +2569,7 @@ __STATIC_INLINE uint32_t LL_USART_GetDEAssertionTime(const USART_TypeDef *USARTx /** * @brief Enable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_EnableDEMode * @param USARTx USART Instance @@ -2574,7 +2582,7 @@ __STATIC_INLINE void LL_USART_EnableDEMode(USART_TypeDef *USARTx) /** * @brief Disable Driver Enable (DE) Mode - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_DisableDEMode * @param USARTx USART Instance @@ -2587,7 +2595,7 @@ __STATIC_INLINE void LL_USART_DisableDEMode(USART_TypeDef *USARTx) /** * @brief Indicate if Driver Enable (DE) Mode is enabled - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEM LL_USART_IsEnabledDEMode * @param USARTx USART Instance @@ -2600,7 +2608,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledDEMode(const USART_TypeDef *USARTx) /** * @brief Select Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_SetDESignalPolarity * @param USARTx USART Instance @@ -2616,7 +2624,7 @@ __STATIC_INLINE void LL_USART_SetDESignalPolarity(USART_TypeDef *USARTx, uint32_ /** * @brief Return Driver Enable Polarity - * @note Macro @ref IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_DRIVER_ENABLE_INSTANCE(USARTx) can be used to check whether or not * Driver Enable feature is supported by the USARTx instance. * @rmtoll CR3 DEP LL_USART_GetDESignalPolarity * @param USARTx USART Instance @@ -2666,7 +2674,8 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) { /* In Asynchronous mode, the following bits must be kept cleared: - LINEN, CLKEN bits in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); } @@ -2679,7 +2688,7 @@ __STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_INSTANCE(USARTx) can be used to check whether or not * Synchronous mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2702,7 +2711,8 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) { /* In Synchronous mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - SCEN, IREN and HDSEL bits in the USART_CR3 register.*/ + - SCEN, IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN | USART_CR3_HDSEL)); /* set the UART/USART in Synchronous mode */ @@ -2717,7 +2727,7 @@ __STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) * - IREN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also set the UART/USART in LIN mode. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function @@ -2742,7 +2752,8 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) { /* In LIN mode, the following bits must be kept cleared: - STOP and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL)); /* Set the UART/USART in LIN mode */ @@ -2757,7 +2768,7 @@ __STATIC_INLINE void LL_USART_ConfigLINMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - IREN bit in the USART_CR3 register, * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not * Half-Duplex mode is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2780,7 +2791,8 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) { /* In Half Duplex mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - SCEN and IREN bits in the USART_CR3 register.*/ + - SCEN and IREN bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_IREN)); /* set the UART/USART in Half Duplex mode */ @@ -2796,7 +2808,7 @@ __STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) * This function also configures Stop bits to 1.5 bits and * sets the USART in Smartcard mode (SCEN bit). * Clock Output is also enabled (CLKEN). - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2820,7 +2832,8 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) { /* In Smartcard mode, the following bits must be kept cleared: - LINEN bit in the USART_CR2 register, - - IREN and HDSEL bits in the USART_CR3 register.*/ + - IREN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_IREN | USART_CR3_HDSEL)); /* Configure Stop bits to 1.5 bits */ @@ -2838,7 +2851,7 @@ __STATIC_INLINE void LL_USART_ConfigSmartcardMode(USART_TypeDef *USARTx) * - SCEN bit in the USART_CR3 register, * - HDSEL bit in the USART_CR3 register. * This function also sets the UART/USART in IRDA mode (IREN bit). - * @note Macro @ref IS_IRDA_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_IRDA_INSTANCE(USARTx) can be used to check whether or not * IrDA feature is supported by the USARTx instance. * @note Call of this function is equivalent to following function call sequence : * - Clear LINEN in CR2 using @ref LL_USART_DisableLIN() function @@ -2863,7 +2876,8 @@ __STATIC_INLINE void LL_USART_ConfigIrdaMode(USART_TypeDef *USARTx) { /* In IRDA mode, the following bits must be kept cleared: - LINEN, STOP and CLKEN bits in the USART_CR2 register, - - SCEN and HDSEL bits in the USART_CR3 register.*/ + - SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN | USART_CR2_STOP)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL)); /* set the UART/USART in IRDA mode */ @@ -2901,7 +2915,8 @@ __STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) { /* In Multi Processor mode, the following bits must be kept cleared: - LINEN and CLKEN bits in the USART_CR2 register, - - IREN, SCEN and HDSEL bits in the USART_CR3 register.*/ + - IREN, SCEN and HDSEL bits in the USART_CR3 register. + */ CLEAR_BIT(USARTx->CR2, (USART_CR2_LINEN | USART_CR2_CLKEN)); CLEAR_BIT(USARTx->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN)); } @@ -2969,12 +2984,11 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_IDLE) == (USART_ISR_IDLE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE +#define LL_USART_IsActiveFlag_RXNE LL_USART_IsActiveFlag_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART Read Data Register or USART RX FIFO Not Empty Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR RXNE_RXFNE LL_USART_IsActiveFlag_RXNE_RXFNE * @param USARTx USART Instance @@ -2996,12 +3010,11 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->ISR, USART_ISR_TC) == (USART_ISR_TC)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF +#define LL_USART_IsActiveFlag_TXE LL_USART_IsActiveFlag_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART Transmit Data Register Empty or USART TX FIFO Not Full Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR TXE_TXFNF LL_USART_IsActiveFlag_TXE_TXFNF * @param USARTx USART Instance @@ -3014,7 +3027,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE_TXFNF(const USART_TypeDef *US /** * @brief Check if the USART LIN Break Detection Flag is set or not - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ISR LBDF LL_USART_IsActiveFlag_LBD * @param USARTx USART Instance @@ -3027,7 +3040,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_LBD(const USART_TypeDef *USARTx) /** * @brief Check if the USART CTS interrupt Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTSIF LL_USART_IsActiveFlag_nCTS * @param USARTx USART Instance @@ -3040,7 +3053,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(const USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ISR CTS LL_USART_IsActiveFlag_CTS * @param USARTx USART Instance @@ -3064,7 +3077,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RTO(const USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Flag is set or not - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ISR EOBF LL_USART_IsActiveFlag_EOB * @param USARTx USART Instance @@ -3077,7 +3090,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_EOB(const USART_TypeDef *USARTx) /** * @brief Check if the SPI Slave Underrun error flag is set or not - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll ISR UDR LL_USART_IsActiveFlag_UDR * @param USARTx USART Instance @@ -3090,7 +3103,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_UDR(const USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Error Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRE LL_USART_IsActiveFlag_ABRE * @param USARTx USART Instance @@ -3103,7 +3116,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(const USART_TypeDef *USARTx) /** * @brief Check if the USART Auto-Baud Rate Flag is set or not - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll ISR ABRF LL_USART_IsActiveFlag_ABR * @param USARTx USART Instance @@ -3160,7 +3173,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(const USART_TypeDef *USARTx) /** * @brief Check if the USART Wake Up from stop mode Flag is set or not - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ISR WUF LL_USART_IsActiveFlag_WKUP * @param USARTx USART Instance @@ -3195,7 +3208,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_REACK(const USART_TypeDef *USARTx /** * @brief Check if the USART TX FIFO Empty Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR TXFE LL_USART_IsActiveFlag_TXFE * @param USARTx USART Instance @@ -3208,7 +3221,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFE(const USART_TypeDef *USARTx) /** * @brief Check if the USART RX FIFO Full Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR RXFF LL_USART_IsActiveFlag_RXFF * @param USARTx USART Instance @@ -3232,7 +3245,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TCBGT(const USART_TypeDef *USARTx /** * @brief Check if the USART TX FIFO Threshold Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR TXFT LL_USART_IsActiveFlag_TXFT * @param USARTx USART Instance @@ -3245,7 +3258,7 @@ __STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXFT(const USART_TypeDef *USARTx) /** * @brief Check if the USART RX FIFO Threshold Flag is set or not - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ISR RXFT LL_USART_IsActiveFlag_RXFT * @param USARTx USART Instance @@ -3313,7 +3326,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) /** * @brief Clear TX FIFO Empty Flag - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll ICR TXFECF LL_USART_ClearFlag_TXFE * @param USARTx USART Instance @@ -3348,7 +3361,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_TCBGT(USART_TypeDef *USARTx) /** * @brief Clear LIN Break Detection Flag - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll ICR LBDCF LL_USART_ClearFlag_LBD * @param USARTx USART Instance @@ -3361,7 +3374,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_LBD(USART_TypeDef *USARTx) /** * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll ICR CTSCF LL_USART_ClearFlag_nCTS * @param USARTx USART Instance @@ -3385,7 +3398,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_RTO(USART_TypeDef *USARTx) /** * @brief Clear End Of Block Flag - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll ICR EOBCF LL_USART_ClearFlag_EOB * @param USARTx USART Instance @@ -3398,7 +3411,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_EOB(USART_TypeDef *USARTx) /** * @brief Clear SPI Slave Underrun Flag - * @note Macro @ref IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_SPI_SLAVE_INSTANCE(USARTx) can be used to check whether or not * SPI Slave mode feature is supported by the USARTx instance. * @rmtoll ICR UDRCF LL_USART_ClearFlag_UDR * @param USARTx USART Instance @@ -3422,7 +3435,7 @@ __STATIC_INLINE void LL_USART_ClearFlag_CM(USART_TypeDef *USARTx) /** * @brief Clear Wake Up from stop mode Flag - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll ICR WUCF LL_USART_ClearFlag_WKUP * @param USARTx USART Instance @@ -3452,12 +3465,11 @@ __STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE +#define LL_USART_EnableIT_RXNE LL_USART_EnableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Enable RX Not Empty and RX FIFO Not Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_EnableIT_RXNE_RXFNE * @param USARTx USART Instance @@ -3479,12 +3491,11 @@ __STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) ATOMIC_SET_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF +#define LL_USART_EnableIT_TXE LL_USART_EnableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Enable TX Empty and TX FIFO Not Full Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_EnableIT_TXE_TXFNF * @param USARTx USART Instance @@ -3530,7 +3541,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RTO(USART_TypeDef *USARTx) /** * @brief Enable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_EnableIT_EOB * @param USARTx USART Instance @@ -3543,7 +3554,7 @@ __STATIC_INLINE void LL_USART_EnableIT_EOB(USART_TypeDef *USARTx) /** * @brief Enable TX FIFO Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXFEIE LL_USART_EnableIT_TXFE * @param USARTx USART Instance @@ -3567,7 +3578,7 @@ __STATIC_INLINE void LL_USART_EnableIT_RXFF(USART_TypeDef *USARTx) /** * @brief Enable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_EnableIT_LBD * @param USARTx USART Instance @@ -3595,7 +3606,7 @@ __STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS * @param USARTx USART Instance @@ -3608,7 +3619,7 @@ __STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) /** * @brief Enable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_EnableIT_WKUP * @param USARTx USART Instance @@ -3621,7 +3632,7 @@ __STATIC_INLINE void LL_USART_EnableIT_WKUP(USART_TypeDef *USARTx) /** * @brief Enable TX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTIE LL_USART_EnableIT_TXFT * @param USARTx USART Instance @@ -3634,7 +3645,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TXFT(USART_TypeDef *USARTx) /** * @brief Enable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_EnableIT_TCBGT * @param USARTx USART Instance @@ -3647,7 +3658,7 @@ __STATIC_INLINE void LL_USART_EnableIT_TCBGT(USART_TypeDef *USARTx) /** * @brief Enable RX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTIE LL_USART_EnableIT_RXFT * @param USARTx USART Instance @@ -3669,12 +3680,11 @@ __STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); } -/* Legacy define */ -#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE +#define LL_USART_DisableIT_RXNE LL_USART_DisableIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Disable RX Not Empty and RX FIFO Not Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_DisableIT_RXNE_RXFNE * @param USARTx USART Instance @@ -3696,12 +3706,11 @@ __STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) ATOMIC_CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); } -/* Legacy define */ -#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF +#define LL_USART_DisableIT_TXE LL_USART_DisableIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Disable TX Empty and TX FIFO Not Full Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_DisableIT_TXE_TXFNF * @param USARTx USART Instance @@ -3747,7 +3756,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RTO(USART_TypeDef *USARTx) /** * @brief Disable End Of Block Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_DisableIT_EOB * @param USARTx USART Instance @@ -3760,7 +3769,7 @@ __STATIC_INLINE void LL_USART_DisableIT_EOB(USART_TypeDef *USARTx) /** * @brief Disable TX FIFO Empty Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXFEIE LL_USART_DisableIT_TXFE * @param USARTx USART Instance @@ -3773,7 +3782,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFE(USART_TypeDef *USARTx) /** * @brief Disable RX FIFO Full Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXFFIE LL_USART_DisableIT_RXFF * @param USARTx USART Instance @@ -3786,7 +3795,7 @@ __STATIC_INLINE void LL_USART_DisableIT_RXFF(USART_TypeDef *USARTx) /** * @brief Disable LIN Break Detection Interrupt - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_DisableIT_LBD * @param USARTx USART Instance @@ -3814,7 +3823,7 @@ __STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) /** * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS * @param USARTx USART Instance @@ -3827,7 +3836,7 @@ __STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) /** * @brief Disable Wake Up from Stop Mode Interrupt - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_DisableIT_WKUP * @param USARTx USART Instance @@ -3840,7 +3849,7 @@ __STATIC_INLINE void LL_USART_DisableIT_WKUP(USART_TypeDef *USARTx) /** * @brief Disable TX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTIE LL_USART_DisableIT_TXFT * @param USARTx USART Instance @@ -3853,7 +3862,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TXFT(USART_TypeDef *USARTx) /** * @brief Disable Smartcard Transmission Complete Before Guard Time Interrupt - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_DisableIT_TCBGT * @param USARTx USART Instance @@ -3866,7 +3875,7 @@ __STATIC_INLINE void LL_USART_DisableIT_TCBGT(USART_TypeDef *USARTx) /** * @brief Disable RX FIFO Threshold Interrupt - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTIE LL_USART_DisableIT_RXFT * @param USARTx USART Instance @@ -3888,12 +3897,11 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE +#define LL_USART_IsEnabledIT_RXNE LL_USART_IsEnabledIT_RXNE_RXFNE /* Redefinition for legacy purpose */ /** * @brief Check if the USART RX Not Empty and USART RX FIFO Not Empty Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXNEIE_RXFNEIE LL_USART_IsEnabledIT_RXNE_RXFNE * @param USARTx USART Instance @@ -3915,12 +3923,11 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(const USART_TypeDef *USARTx) return ((READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)) ? 1UL : 0UL); } -/* Legacy define */ -#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF +#define LL_USART_IsEnabledIT_TXE LL_USART_IsEnabledIT_TXE_TXFNF /* Redefinition for legacy purpose */ /** * @brief Check if the USART TX Empty and USART TX FIFO Not Full Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXEIE_TXFNFIE LL_USART_IsEnabledIT_TXE_TXFNF * @param USARTx USART Instance @@ -3966,7 +3973,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RTO(const USART_TypeDef *USARTx) /** * @brief Check if the USART End Of Block Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR1 EOBIE LL_USART_IsEnabledIT_EOB * @param USARTx USART Instance @@ -3979,7 +3986,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_EOB(const USART_TypeDef *USARTx) /** * @brief Check if the USART TX FIFO Empty Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 TXFEIE LL_USART_IsEnabledIT_TXFE * @param USARTx USART Instance @@ -3992,7 +3999,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFE(const USART_TypeDef *USARTx) /** * @brief Check if the USART RX FIFO Full Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR1 RXFFIE LL_USART_IsEnabledIT_RXFF * @param USARTx USART Instance @@ -4005,7 +4012,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXFF(const USART_TypeDef *USARTx) /** * @brief Check if the USART LIN Break Detection Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_LIN_INSTANCE(USARTx) can be used to check whether or not * LIN feature is supported by the USARTx instance. * @rmtoll CR2 LBDIE LL_USART_IsEnabledIT_LBD * @param USARTx USART Instance @@ -4029,7 +4036,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(const USART_TypeDef *USARTx) /** * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not * Hardware Flow control feature is supported by the USARTx instance. * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS * @param USARTx USART Instance @@ -4042,7 +4049,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(const USART_TypeDef *USARTx) /** * @brief Check if the USART Wake Up from Stop Mode Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_WAKEUP_FROMSTOP_INSTANCE(USARTx) can be used to check whether or not * Wake-up from Stop mode feature is supported by the USARTx instance. * @rmtoll CR3 WUFIE LL_USART_IsEnabledIT_WKUP * @param USARTx USART Instance @@ -4055,7 +4062,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_WKUP(const USART_TypeDef *USARTx) /** * @brief Check if USART TX FIFO Threshold Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 TXFTIE LL_USART_IsEnabledIT_TXFT * @param USARTx USART Instance @@ -4068,7 +4075,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXFT(const USART_TypeDef *USARTx) /** * @brief Check if the Smartcard Transmission Complete Before Guard Time Interrupt is enabled or disabled. - * @note Macro @ref IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_SMARTCARD_INSTANCE(USARTx) can be used to check whether or not * Smartcard feature is supported by the USARTx instance. * @rmtoll CR3 TCBGTIE LL_USART_IsEnabledIT_TCBGT * @param USARTx USART Instance @@ -4081,7 +4088,7 @@ __STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TCBGT(const USART_TypeDef *USARTx) /** * @brief Check if USART RX FIFO Threshold Interrupt is enabled or disabled - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll CR3 RXFTIE LL_USART_IsEnabledIT_RXFT * @param USARTx USART Instance @@ -4291,7 +4298,7 @@ __STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Valu /** * @brief Request an Automatic Baud Rate measurement on next received data frame - * @note Macro @ref IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(USARTx) can be used to check whether or not * Auto Baud Rate detection feature is supported by the USARTx instance. * @rmtoll RQR ABRRQ LL_USART_RequestAutoBaudRate * @param USARTx USART Instance @@ -4326,7 +4333,7 @@ __STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) /** * @brief Request a Receive Data and FIFO flush - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @note Allows to discard the received data without reading them, and avoid an overrun * condition. @@ -4341,7 +4348,7 @@ __STATIC_INLINE void LL_USART_RequestRxDataFlush(USART_TypeDef *USARTx) /** * @brief Request a Transmit data and FIFO flush - * @note Macro @ref IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not + * @note Macro IS_UART_FIFO_INSTANCE(USARTx) can be used to check whether or not * FIFO mode feature is supported by the USARTx instance. * @rmtoll RQR TXFRQ LL_USART_RequestTxDataFlush * @param USARTx USART Instance diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h index cea51bf1c2..6e4f59b687 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_utils.h @@ -262,7 +262,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) * @ref LL_RCC_GetSystemClocksFreq (HCLK2_Frequency field)) * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks + * @param Ticks Frequency of Ticks (Hz) * @retval None */ #else @@ -272,7 +272,7 @@ __STATIC_INLINE uint32_t LL_GetPackageType(void) * @ref LL_RCC_GetSystemClocksFreq (HCLK1_Frequency field)) * @note When a RTOS is used, it is recommended to avoid changing the SysTick * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param Ticks Number of ticks + * @param Ticks Frequency of Ticks (Hz) * @retval None */ #endif /* CORE_CM0PLUS */ diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_wwdg.h b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_wwdg.h index d981c1763a..18a300c55c 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_wwdg.h +++ b/system/Drivers/STM32WLxx_HAL_Driver/Inc/stm32wlxx_ll_wwdg.h @@ -135,7 +135,7 @@ __STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)) ? 1UL : 0UL); } @@ -162,7 +162,7 @@ __STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Counter value */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CR, WWDG_CR_T)); } @@ -203,7 +203,7 @@ __STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescale * @arg @ref LL_WWDG_PRESCALER_64 * @arg @ref LL_WWDG_PRESCALER_128 */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); } @@ -235,7 +235,7 @@ __STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) * @param WWDGx WWDG Instance * @retval 7 bit Watchdog Window value */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(const WWDG_TypeDef *WWDGx) { return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); } @@ -256,7 +256,7 @@ __STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)) ? 1UL : 0UL); } @@ -298,7 +298,7 @@ __STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) * @param WWDGx WWDG Instance * @retval State of bit (1 or 0). */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(const WWDG_TypeDef *WWDGx) { return ((READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)) ? 1UL : 0UL); } diff --git a/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html b/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html index 749fa01818..00a3151f73 100644 --- a/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html +++ b/system/Drivers/STM32WLxx_HAL_Driver/Release_Notes.html @@ -5,24 +5,16 @@ Release Notes for STM32WLxx HAL Drivers Package - + @@ -32,80 +24,205 @@

    Release Notes for

    STM32WLxx HAL Drivers

    Copyright © 2020 STMicroelectronics

    - +

    Purpose

    -

    The STM32Cube HAL and LL, an STM32 abstraction layer embedded -software, ensure maximized portability across STM32 portfolio.

    -

    The Portable APIs layer provides a generic, multi instanced and -simple set of APIs to interact with the upper layer (application, -libraries and stacks). It is composed of native and extended APIs set. -It is directly built around a generic architecture and allows the -build-upon layers, like the middleware layer, to implement its functions -without knowing in-depth the used STM32 device. This improves the -library code reusability and guarantees an easy portability on other -devices and STM32 families.

    -

    The Low Layer (LL) drivers are part of the STM32Cube firmware HAL -that provide basic set of optimized and one shot services. The Low layer -drivers, contrary to the HAL ones are not Fully Portable across the -STM32 families; the availability of some functions depend on the -physical availability of the relative features on the product. The Low -Layer (LL) drivers are designed to offer the following features:

    -
      -
    • New set of inline function for direct and atomic register -access
      • -
    • One-shot operations that can be used by the HAL drivers or from -application level.
      • -
    • Fully Independent from HAL and can be used in standalone usage -(without HAL drivers)
      • +

      The STM32Cube HAL and LL, an STM32 abstraction layer embedded software, ensure maximized portability across STM32 portfolio.

      +

      The Portable APIs layer provides a generic, multi instanced and simple set of APIs to interact with the upper layer (application, libraries and stacks). It is composed of native and extended APIs set. It is directly built around a generic architecture and allows the build-upon layers, like the middleware layer, to implement its functions without knowing in-depth the used STM32 device. This improves the library code reusability and guarantees an easy portability on other devices and STM32 families.

      +

      The Low Layer (LL) drivers are part of the STM32Cube firmware HAL that provide basic set of optimized and one shot services. The Low layer drivers, contrary to the HAL ones are not Fully Portable across the STM32 families; the availability of some functions depend on the physical availability of the relative features on the product. The Low Layer (LL) drivers are designed to offer the following features:

      +
        +
      • New set of inline function for direct and atomic register access
        • +
      • One-shot operations that can be used by the HAL drivers or from application level.
        • +
      • Fully Independent from HAL and can be used in standalone usage (without HAL drivers)
      • Full features coverage of the all the supported peripherals.
-
-

Update History

+
+

Update History

- - +

Main Changes

    -
  • Patch release of HAL and Low Layer drivers to -include latest corrections
    • -
  • Update the following IPs Drivers: ADC, CORTEX, CRYP, DAC, GENERIC, -GPIO, I2C, SMBUS, SPIU, SUBGHZ, TIM, UART, UTILS
    • +
  • Maintenance release of HAL and Low Layer drivers to include latest corrections
    • +

  • Update the following IPs Drivers: ADC, CRYP, DMA, EXTI, FLASH, GENERIC, GPIO, GTZC, HSEM, I2C, IPCC, IWDG, LPTIM, PWR, RCC, RTC, SPI, SUBGHZ, TIM, UART, USART, UTILS, WWDG

    • +

  • Fixes for MISRAC2012 Rules 13.4_b, 12.3, 10.4 and 8.13 violations

Contents

HAL Drivers updates

  • HAL ADC driver
      +
    • Add const qualifier for calibrated values (read only, in system flash)
      +
      • +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL CRYP driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      +
      • +
    • Fixed MISRA C2012 Rule 10.4_a violations
      • +
    • +
  • HAL DMA driver +
      +
    • Rebase wl code against the most recent c7amba_dma1 reference branch
      +
      • +
    • Fix MISRA PC Lint issue against rule-11.9
      • +
    • +
  • HAL EXTI driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL FLASH driver +
      +
    • Fix bitwise comparison that otherwise always evaluates to false
      +
      • +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL GENERIC driver +
      +
    • Fixed timer timebase initialization sequence by registering the callback before starting the timer to ensure correct callback handling in FreeRTOS projects
      • +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL GPIO driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL GTZC driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL HSEM driver +
      +
    • Fix an issue where LL_HSEM_1StepLock uses HSEM_R_LOCK instead of HSEM_RLR_LOCK while checking the RLR register
      +
      • +
    • Macro update to be aligned with register name in CMSIS
      +
      • +
    • Update LL HSEM description and define to be aligned with the correct number of semaphores
      • +
    • +
  • HAL I2C driver +
      +
    • Update HAL I2C driver to disable all interrupts after end of transaction.
      • +
    • +
  • HAL IPCC driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL IWDG driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL LPTIM driver +
      +
    • Removed redundant IS_LPTIM_AUTORELOAD macro
      • +
    • +
  • HAL PWR driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL RCC driver +
      +
    • Correct LSE config macro regarding LSESYS handling
      • +
    • +
  • HAL RTC driver +
      +
    • Update STM32CubeIDE projects to fix the location of .size directive in startup code to allow proper size information of vector table
      +
      • +
    • Fixed MISRA C2012 Rule 13.4_b violations
      +
      • +
    • Fixed MISRA C2012 Rule 12.3 violations
      • +
    • +
  • HAL SPI driver +
      +
    • Rebase wl code against the most recent c7amba_spi2s1 reference branch
      +
      • +
    • Fix compilation error in SPI validation code
      • +
    • +
  • HAL SUBGHZ driver +
      +
    • Pass CRC status info in upper layer
      +
      • +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL TIM driver +
      +
    • Assert check for the right channels
      +
      • +
    • Fixed typo in PWM symmetric mode related constants names
      • +
    • +
  • HAL UART driver +
      +
    • Rework of UART_WaitOnFlagUntilTimeout() API to avoid being stuck forever when UART overrun error occurs and to enhance behavior
      • +
    • +
  • HAL USART driver +
      +
    • __HAL_LOCK() removal from HAL_xxx_RegisterCallback()/HAL_xxx_UnRegisterCallback()
      • +
    • +
  • HAL UTILS driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
  • HAL WWDG driver +
      +
    • Fixed MISRA C2012 Rule 8.13 violations
      • +
    • +
+


+

+

Known Limitations

+

None

+

Development Toolchains and Compilers

+
    +
  • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch EWARM
    • +
  • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + Keil DFP V1.1.1 Pack
    • +
  • STM32CubeIDE 1.11.0 (GNU Tools for STM32 10.3-2021.10)
    • +
+

Supported Devices and boards

+

Supported Devices:

+
    +
  • STM32WL55xx
    • +
  • STM32WL54xx
    • +
  • STM32WLE5xx
    • +
  • STM32WLE4xx
    • +
  • STM32WL5Mxx
    • +
+

Backward Compatibility

+

Not applicable

+

Dependencies

+

None

+


+

+
+
+
+ +
+

Main Changes

+
    +
  • Patch release of HAL and Low Layer drivers to include latest corrections
    • +
  • Update the following IPs Drivers: ADC, CORTEX, CRYP, DAC, GENERIC, GPIO, I2C, SMBUS, SPIU, SUBGHZ, TIM, UART, UTILS
    • +
+

Contents

+

HAL Drivers updates

+
    +
  • HAL ADC driver +
    • Fix MISRA-C 2012 Rule 15.7 issue
      • -
    • Improve de-init sequence by reset clock configuration on last step -(otherwise, under specific clock source selection, some parameters can -be not reset)
      • +
    • Improve de-init sequence by reset clock configuration on last step (otherwise, under specific clock source selection, some parameters can be not reset)
    • Add CFGR1_CHSELRMOD bit to be reset by LL_ADC_DeInit() function
  • HAL CORTEX driver
      -
    • Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU -registers independently of the value of Enable/Disable field and add new -APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion()
      • +
    • Update HAL_MPU_ConfigRegion() to allow the configuration of the MPU registers independently of the value of Enable/Disable field and add new APIs HAL_MPU_EnableRegion() / HAL_MPU_DisableRegion()
  • HAL CRYP driver
      -
    • Update AES GCM in interrupt mode to avoid Computation Completed IRQ -fires before the DINR pointer increment
      • -
    • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ -fires before the DINR pointer increment
      • +
    • Update AES GCM in interrupt mode to avoid Computation Completed IRQ fires before the DINR pointer increment
      • +
    • Update Crypt/Decrypt IT processes to avoid Computation Completed IRQ fires before the DINR pointer increment
  • HAL DAC driver
      -
    • Fix HAL DAC calibration procedure (function -HAL_DACEx_SelfCalibrate() ) to manage case of calibration factor equal -to range maximum value (previously, in this case calibration factor was -reset, leading to voltage accuracy not optimal)
      • +
    • Fix HAL DAC calibration procedure (function HAL_DACEx_SelfCalibrate() ) to manage case of calibration factor equal to range maximum value (previously, in this case calibration factor was reset, leading to voltage accuracy not optimal)
    • Update DAC buffer calibration according to Reference Manual
  • HAL Generic driver @@ -114,69 +231,46 @@

    HAL Drivers updates

  • HAL I2C driver
      -
    • Remove HAL DMA dependency thanks to the HAL_DMA_MODULE_ENABLED -define
      • -
    • Solve Slave No stretch not functional by using HAL Slave -interface
      • +
    • Remove HAL DMA dependency thanks to the HAL_DMA_MODULE_ENABLED define
      • +
    • Solve Slave No stretch not functional by using HAL Slave interface
    • Update I2C_WaitOnFlagUntilTimeout() API to handle error case
      • -
    • Update HAL_I2C_Slave_Transmit() to check if the received NACK is the -good one
      • -
    • Update HAL_I2C_Init() API to clear ADD10 bit in 7 bit addressing -mode
      • -
    • Update I2C_GENERATE_START() macro to generate stop automatically in -10 bit addressing mode
      • +
    • Update HAL_I2C_Slave_Transmit() to check if the received NACK is the good one
      • +
    • Update HAL_I2C_Init() API to clear ADD10 bit in 7 bit addressing mode
      • +
    • Update I2C_GENERATE_START() macro to generate stop automatically in 10 bit addressing mode
    • Remove the unusable code in function HAL_I2C_IsDeviceReady
      • -
    • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const -qualifiers
      • -
    • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF -independently from I2C_FLAG_RXNE
      • -
    • Update HAL I2C driver to prefetch data before starting the -transmission: implementation of errata sheet workaround I2C2-190208 : -Transmission stalled after first byte
      • -
    • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to -prevent the call of HAL_I2C_ListenCpltCallback twice
      • +
    • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers
      • +
    • Update I2C_WaitOnRXNEFlagUntilTimeout to check I2C_FLAG_AF independently from I2C_FLAG_RXNE
      • +
    • Update HAL I2C driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte
      • +
    • Update I2C_Slave_ISR_IT, I2C_Slave_ISR_DMA and I2C_ITSlaveCplt to prevent the call of HAL_I2C_ListenCpltCallback twice
    • Update HAL_I2C_Mem_Write_IT API to initialize XferSize at 0
    • Enhance HAL I2C to be thread safe
  • HAL SMBUS driver
    • Update SMBUS_ITErrorHandler to flush TXDR just in case of error
      • -
    • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const -qualifiers
      • -
    • Update HAL SMBUS driver to prefetch data before starting the -transmission: implementation of errata sheet workaround I2C2-190208 : -Transmission stalled after first byte
      • +
    • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers
      • +
    • Update HAL SMBUS driver to prefetch data before starting the transmission: implementation of errata sheet workaround I2C2-190208 : Transmission stalled after first byte
  • HAL SPI driver
      -
    • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of -one byte transaction
      • +
    • Update HAL_SPI_TransmitReceive API to set the bit CRCNEXT in case of one byte transaction
    • Update IT API to enable interrupts after process unlock
      • -
    • Fix driver to don’t update state in case of error -(HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT)
      • +
    • Fix driver to don’t update state in case of error (HAL_SPI_STATE_READY will be set only in case of HAL_TIMEOUT)
  • HAL SUBGHZ driver
      -
    • Change macro from ‘CM0PLUS’ to ‘CORE_CM0PLUS’ as in preprocessor -directives
      • +
    • Change macro from ‘CM0PLUS’ to ‘CORE_CM0PLUS’ as in preprocessor directives
  • HAL TIM driver
      -
    • Update interrupt flag is cleared when the update event is generated -by software
      • -
    • Remove multiple volatile reads or writes in interrupt handler for -better performance
      • +
    • Update interrupt flag is cleared when the update event is generated by software
      • +
    • Remove multiple volatile reads or writes in interrupt handler for better performance
  • HAL UART driver
      -
    • Avoid RTOF flag to be cleared by a transmit process in polling -mode
      • -
    • Fix incorrect gState check in -HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to -allow user Rx Event Callback registration when a transmit is -ongoing
      • -
    • Update initialisation sequence for TXINV, RXINV and TXRXSWAP -settings
      • +
    • Avoid RTOF flag to be cleared by a transmit process in polling mode
      • +
    • Fix incorrect gState check in HAL_UART_RegisterRxEventCallback/HAL_UART_UnRegisterRxEventCallback to allow user Rx Event Callback registration when a transmit is ongoing
      • +
    • Update initialisation sequence for TXINV, RXINV and TXRXSWAP settings
  • HAL UTILS driver
      @@ -188,33 +282,24 @@

      LL Drivers updates

      • LL GPIO driver
          -
        • Remove a redundant call to LL_GPIO_SetPinMode() within the -LL_GPIO_Init() API
          • +
        • Remove a redundant call to LL_GPIO_SetPinMode() within the LL_GPIO_Init() API
      • LL I2C driver
          -
        • Update LL_I2C_HandleTranfer function to prevent undefined behavior -of volatile usage before updating the CR2 register
          • -
        • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const -qualifiers
          +
        • Update LL_I2C_HandleTranfer function to prevent undefined behavior of volatile usage before updating the CR2 register
          • +
        • Enhance HAL code quality for MISRA-C Rule-8.13 by adding const qualifiers
      -

      Known Limitations

      +

      Known Limitations

      None

      -

      Development Toolchains and -Compilers

      -
        -
      • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch -EWARM
        • -
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + -Keil -DFP V1.1.1 Pack
        • +

        Development Toolchains and Compilers

        +
          +
        • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch EWARM
          • +
        • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + Keil DFP V1.1.1 Pack
        • STM32CubeIDE 1.11.0 (GNU Tools for STM32 10.3-2021.10)
        -

        Supported Devices and boards

        +

        Supported Devices and boards

        Supported Devices:

        • STM32WL55xx
          • @@ -223,47 +308,38 @@

          Supported Devices and boards

        • STM32WLE4xx
        • STM32WL5Mxx
        -

        Backward Compatibility

        +

        Backward Compatibility

        Not applicable

        -

        Dependencies

        +

        Dependencies

        None


    • - - +
    -

    Main Changes

    +

    Main Changes

      -
    • Maintenance release of HAL and Low Layer drivers to -include latest corrections
      • -
    • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & -HAL_xxxx_UnregisterCallback for IPs (DAC, IRDA, LPTIM, SMARTCARD, TIM, -UART, USART)
      • -
    • Enhance code quality (MISRA-C rules 8.13, 11.9) for some drivers: -ADC, COMP, DMA, IRDA, LPTIM, SMARTCARD, TIM, UART, USART
      • +
    • Maintenance release of HAL and Low Layer drivers to include latest corrections
      • +
    • Remove HAL_LOCK/HAL_UNLOCK calls in HAL_xxxx_RegisterCallback & HAL_xxxx_UnregisterCallback for IPs (DAC, IRDA, LPTIM, SMARTCARD, TIM, UART, USART)
      • +
    • Enhance code quality (MISRA-C rules 8.13, 11.9) for some drivers: ADC, COMP, DMA, IRDA, LPTIM, SMARTCARD, TIM, UART, USART
    -

    Contents

    -

    HAL Drivers updates

    +

    Contents

    +

    HAL Drivers updates

    • HAL ADC driver
      • Disable AutoPowerOff when performing calibration
        • -
      • Rename ADC_TRx registers to AWDxTR to be in accordance with the -Reference Manual
        • +
      • Rename ADC_TRx registers to AWDxTR to be in accordance with the Reference Manual
    • HAL CORTEX driver
        -
      • Remove #define LL_MPU_TEX_LEVEL4 (no Level 2 cache for STM32 SoC -with Armv7-M cortex)
        • +
      • Remove #define LL_MPU_TEX_LEVEL4 (no Level 2 cache for STM32 SoC with Armv7-M cortex)
    • HAL CRC driver
        -
      • Add filter in HAL_CRCEx_Polynomial_Set() function to exclude even -polynomials
        • +
      • Add filter in HAL_CRCEx_Polynomial_Set() function to exclude even polynomials
    • HAL CRYP driver
        @@ -276,75 +352,59 @@

        HAL Drivers updates

    • HAL EXTI driver
        -
      • Fix computation of pExtiConfig->GPIOSel in -HAL_EXTI_GetConfigLine()
        • +
      • Fix computation of pExtiConfig->GPIOSel in HAL_EXTI_GetConfigLine()
    • HAL Generic driver
        -
      • Add HAL_RADIO APIs to handle Radio services (only for -STM32WL5M)
        • +
      • Add HAL_RADIO APIs to handle Radio services (only for STM32WL5M)
    • HAL I2C driver
      • Fix Timeout issue using HAL MEM interface through FreeRTOS
      • Fix I2C_IsErrorOccurred returning error if timeout is detected
        • -
      • Fix ADDRF flag cleared too early when the restart is received but -the direction has changed
        • +
      • Fix ADDRF flag cleared too early when the restart is received but the direction has changed
    • HAL IRDA driver
        -
      • Fix wrong cast when computing the USARTDIV value in -IRDA_SetConfig()
        • +
      • Fix wrong cast when computing the USARTDIV value in IRDA_SetConfig()
    • HAL LPTIM driver
      • Enhance LPTIM state management
        • -
      • Fix IS_LPTIM_AUTORELOAD & IS_LPTIM_PERIOD macros to check that -AutoReload value must be strictly greater than 0
        • +
      • Fix IS_LPTIM_AUTORELOAD & IS_LPTIM_PERIOD macros to check that AutoReload value must be strictly greater than 0
    • HAL RCC driver
        -
      • Optimize HAL_RCC_OscConfig function when checking if oscillator is -ready
        • +
      • Optimize HAL_RCC_OscConfig function when checking if oscillator is ready
      • Optimize HAL_RCC_GetOscConfig function
        • -
      • Remove GPIO configuration in HAL_RCCEx_EnableLSCO & -HAL_RCCEx_DisableLSCO functions
        • +
      • Remove GPIO configuration in HAL_RCCEx_EnableLSCO & HAL_RCCEx_DisableLSCO functions
    • HAL RTC driver
        -
      • Improve HAL_RTC_Init function to avoid initialization if already -done
        • +
      • Improve HAL_RTC_Init function to avoid initialization if already done
    • HAL SMARTCARD driver
        -
      • Fix wrong cast when computing the USARTDIV value in -SMARTCARD_SetConfig() function
        • +
      • Fix wrong cast when computing the USARTDIV value in SMARTCARD_SetConfig() function
    • HAL SUBGHZ driver
      • Clear the interrupt CR register just after having read it
        • -
      • Support new feature LoraFHSS (Lora Frequency Hopping Spread -Spectrum)
        • -
      • Add new state HAL_SUBGHZ_STATE_RESET_RF_READY to avoid to -reinitialize RF on existing from Standby mode
        • +
      • Support new feature LoraFHSS (Lora Frequency Hopping Spread Spectrum)
        • +
      • Add new state HAL_SUBGHZ_STATE_RESET_RF_READY to avoid to reinitialize RF on existing from Standby mode
    • HAL TIM driver
      • Improve driver robustness against wrong period values
      • Improve driver robustness against wrong DMA related parameters
        • -
      • Add new __HAL_TIM_SELECT_CCDMAREQUEST() macro to select CCx DMA -source
        • +
      • Add new __HAL_TIM_SELECT_CCDMAREQUEST() macro to select CCx DMA source
    • HAL UART driver
        -
      • Fix wrong cast when computing the USARTDIV value in UART_SetConfig() -function
        • -
      • Add HAL_UARTEx_GetRxEventType function to retrieve the type of event -that has led the RxEventCallback execution
        • -
      • Remove HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs to fix a -concurrent access issue
        • -
      • Disable the Receiver Timeout Interrupt when data reception is -completed
        • +
      • Fix wrong cast when computing the USARTDIV value in UART_SetConfig() function
        • +
      • Add HAL_UARTEx_GetRxEventType function to retrieve the type of event that has led the RxEventCallback execution
        • +
      • Remove HAL_LOCK/HAL_UNLOCK calls in HAL UART Tx and Rx APIs to fix a concurrent access issue
        • +
      • Disable the Receiver Timeout Interrupt when data reception is completed


    @@ -353,13 +413,11 @@

    LL Drivers updates

    • LL LPTIM driver
        -
      • Enhance code quality by renaming all functions -LL_LPTIM_ClearFLAG_Xxxxx with LL_LPTIM_ClearFlag_Xxxxx
        • +
      • Enhance code quality by renaming all functions LL_LPTIM_ClearFLAG_Xxxxx with LL_LPTIM_ClearFlag_Xxxxx
    • LL System driver
        -
      • Fix LL_SYSCFG_GetEXTISource function which returned wrong result on -M4 core
        • +
      • Fix LL_SYSCFG_GetEXTISource function which returned wrong result on M4 core
    • LL USART driver
        @@ -367,28 +425,20 @@

        LL Drivers updates

    • LL Utils driver
        -
      • Fix a wrong parameter of __LL_RCC_CALC_MSI_FREQ given erroneous PLL -frequency
        • +
      • Fix a wrong parameter of __LL_RCC_CALC_MSI_FREQ given erroneous PLL frequency


    -

    Known Limitations

    +

    Known Limitations

    None

    -

    Development Toolchains -and Compilers

    -
      -
    • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch -EWARM
      • -
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + -Keil -DFP V1.1.1 Pack
      • +

      Development Toolchains and Compilers

      +
        +
      • IAR Embedded Workbench for ARM (EWARM) toolchain V9.20.1 + Patch EWARM
        • +
      • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.36 + Keil DFP V1.1.1 Pack
      • STM32CubeIDE 1.11.0 (GNU Tools for STM32 10.3-2021.10)
      -

      Supported Devices and -boards

      +

      Supported Devices and boards

      Supported Devices:

      • STM32WL55xx
        • @@ -397,74 +447,60 @@

        Supported Devices and
      • STM32WLE4xx
      • STM32WL5Mxx

      -

      Backward Compatibility

      +

      Backward Compatibility

      Not applicable

      -

      Dependencies

      +

      Dependencies

      None


    - - +
    -

    Main Changes

    +

    Main Changes

      -
    • Maintenance release of HAL and Low Layer drivers to -include latest corrections
      • -
    • All source files: update disclaimer to add reference to the new -license agreement
      • +
    • Maintenance release of HAL and Low Layer drivers to include latest corrections
      • +
    • All source files: update disclaimer to add reference to the new license agreement
    • Correct English spelling errors and typos
    -

    Contents

    -

    HAL Drivers updates

    +

    Contents

    +

    HAL Drivers updates

    • HAL ADC driver
      • Enhance ADC calibration to reduce noise effect
        • -
      • Fix write access to registers ADC_CFGR1 and ADC_CFGR2 in -HAL_ADC_Init() and HAL_ADC_AnalogWDGConfig() functions
        • +
      • Fix write access to registers ADC_CFGR1 and ADC_CFGR2 in HAL_ADC_Init() and HAL_ADC_AnalogWDGConfig() functions
    • HAL GPIO driver
        -
      • Reorder EXTI config in HAL_GPIO_Init/HAL_GPIO_DeInit to avoid -unexpected level detection
        • -
      • Add new HAL_GPIO_WriteMultipleStatePin() API for multiple pin access -in same cycle
        • +
      • Reorder EXTI config in HAL_GPIO_Init/HAL_GPIO_DeInit to avoid unexpected level detection
        • +
      • Add new HAL_GPIO_WriteMultipleStatePin() API for multiple pin access in same cycle
    • HAL I2C driver
      • Fix written reserved bit 28 in I2C_CR2 register
      • Improve I2C_WaitOnFlagUntilTimeout() description to match code
      • Update to handle errors in polling mode
        • -
      • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and -correctly manage when error occurs
        • -
      • Fix some communication issue due to low system frequency execution -(HSI)
        • +
      • Rename I2C_IsAcknowledgeFailed() to I2C_IsErrorOccurred() and correctly manage when error occurs
        • +
      • Fix some communication issue due to low system frequency execution (HSI)
    • HAL IRDA driver
        -
      • Improve header description of IRDA_WaitOnFlagUntilTimeout() -function
        • -
      • Add a check on the IRDA parity before enabling the parity error -interrupt
        • +
      • Improve header description of IRDA_WaitOnFlagUntilTimeout() function
        • +
      • Add a check on the IRDA parity before enabling the parity error interrupt
    • HAL LPTIM driver
        -
      • Add check on PRIMASK register to prevent from enabling unwanted -global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
        • +
      • Add check on PRIMASK register to prevent from enabling unwanted global interrupts within LPTIM_Disable() and LL_LPTIM_Disable()
    • HAL RCC driver
        -
      • Enhance RCC_MCOx in order to support both MCO number and AF -mapping
        • +
      • Enhance RCC_MCOx in order to support both MCO number and AF mapping
    • HAL SMARTCARD driver
        -
      • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() -function
        • +
      • Improve header description of SMARTCARD_WaitOnFlagUntilTimeout() function
    • HAL SMBUS driver
        @@ -473,29 +509,22 @@

        HAL Drivers updates

      • HAL_SMBUSEx_EnableWakeUp()
      • HAL_SMBUSEx_DisableWakeUp()
      • -
    • Update to fix issue of mismatched data received by master in case of -data size to be transmitted by the slave is greater than the data size -to be received by the master
      • +
    • Update to fix issue of mismatched data received by master in case of data size to be transmitted by the slave is greater than the data size to be received by the master
    • Add flush on TX register
  • HAL TIM driver
      -
    • Fix incorrect behavior of the timer if input signal changes before -the end of timer configuration
      • +
    • Fix incorrect behavior of the timer if input signal changes before the end of timer configuration
  • HAL UART driver
      -
    • Improve header description of UART_WaitOnFlagUntilTimeout() -function
      • -
    • Add a check on the UART parity before enabling the parity error -interruption
      • +
    • Improve header description of UART_WaitOnFlagUntilTimeout() function
      • +
    • Add a check on the UART parity before enabling the parity error interruption
  • HAL USART driver
      -
    • Improve header description of USART_WaitOnFlagUntilTimeout() -function
      • -
    • Add a check on the USART parity before enabling the parity error -interruption
      • +
    • Improve header description of USART_WaitOnFlagUntilTimeout() function
      • +
    • Add a check on the USART parity before enabling the parity error interruption


    • @@ -512,8 +541,7 @@

    LL Drivers updates

  • LL CRC driver
      -
    • Rectified @brief of -LL_CRC_GetOutputDataReverseMode() API
      • +
    • Rectified @brief of LL_CRC_GetOutputDataReverseMode() API
  • LL LPUART driver
      @@ -521,11 +549,8 @@

      LL Drivers updates

  • LL RCC driver
      -
    • Add missing API: LL_RCC_PLL_IsEnabledDomain_ADC, -LL_RCC_PLL_IsEnabledDomain_RNG, LL_RCC_PLL_IsEnabledDomain_I2S, -LL_RCC_PLL_IsEnabledDomain_SYS
      • -
    • Add check of PLL enable bit when a peripheral using PPL P or PLL -Q
      • +
    • Add missing API: LL_RCC_PLL_IsEnabledDomain_ADC, LL_RCC_PLL_IsEnabledDomain_RNG, LL_RCC_PLL_IsEnabledDomain_I2S, LL_RCC_PLL_IsEnabledDomain_SYS
      • +
    • Add check of PLL enable bit when a peripheral using PPL P or PLL Q
  • LL RNG driver
      @@ -533,24 +558,19 @@

      LL Drivers updates

  • Utils driver
      -
    • Fix LL_PLL_ConfigSystemClock_HSE to take into account the setting of -RCC_CR_HSEPRE when computing pllrfreq
      +
    • Fix LL_PLL_ConfigSystemClock_HSE to take into account the setting of RCC_CR_HSEPRE when computing pllrfreq
    • -

    Known Limitations

    +

    Known Limitations

    None

    -

    Development Toolchains -and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
      • -
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain -V5.31
      • -
    • STM32CubeIDE 1.9.0 (native GNU ARM 10.3-2021-10 or optional GNU ARM -9-2020-q2-update)
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
      • +
    • STM32CubeIDE 1.9.0 (native GNU ARM 10.3-2021-10 or optional GNU ARM 9-2020-q2-update)
    -

    Supported Devices and -boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32WL55xx
      • @@ -558,23 +578,20 @@

      Supported Devices and
    • STM32WLE5xx
    • STM32WLE4xx

    -

    Backward Compatibility

    +

    Backward Compatibility

    Not applicable

    -

    Dependencies

    +

    Dependencies

    None


    - - +
    -

    Main Changes

    +

    Main Changes

      -
    • Maintenance release of HAL and Low Layer drivers to -include latest corrections
      • +
    • Maintenance release of HAL and Low Layer drivers to include latest corrections
    • Update of HAL SMBUS driver to introduce fast mode and fast mode plus
      • Add extension files stm32wlxx_hal_smbus_ex.h/.c for new APIs: @@ -584,48 +601,37 @@

        Main Changes

    -

    Contents

    -

    HAL Drivers updates

    +

    Contents

    +

    HAL Drivers updates

    • HAL ADC driver
        -
      • Update CFGR2 oversampling bitfields conditionally to oversampling -enable
        • -
      • Update timeout mechanism to avoid false timeout detection in case of -preemption
        • -
      • Update wait_loop_index computation so delay in us is always -multiplicated by at least value “1”
        • +
      • Update CFGR2 oversampling bitfields conditionally to oversampling enable
        • +
      • Update timeout mechanism to avoid false timeout detection in case of preemption
        • +
      • Update wait_loop_index computation so delay in us is always multiplicated by at least value “1”
    • HAL COMP driver
        -
      • Update wait_loop_index computation so delay in us is always -multiplicated by at least value “1”
        • +
      • Update wait_loop_index computation so delay in us is always multiplicated by at least value “1”
    • HAL CORTEX driver
        -
      • Disable the smallest MPU region sizes (32B, 64B, 128B) in the M0+ -context
        • +
      • Disable the smallest MPU region sizes (32B, 64B, 128B) in the M0+ context
    • HAL CRYP driver
        -
      • Update HAL_CRYP_SetConfig() and HAL_CRYP_GetConfig() APIs to set/get -the continent of KeyIVConfigSkip correctly
        • -
      • Resolve interrupt mode related GCM decryption issue causing wrong -computation of decryption size
        • -
      • Update HAL_CRYP_InCpltCallback() API to fix an incorrect condition -call at resumption time
        • -
      • Update CRYP_AESCCM_Process_IT() to fix incorrect CCM header length -management when data are fed to the peripheral under interrupt
        • +
      • Update HAL_CRYP_SetConfig() and HAL_CRYP_GetConfig() APIs to set/get the continent of KeyIVConfigSkip correctly
        • +
      • Resolve interrupt mode related GCM decryption issue causing wrong computation of decryption size
        • +
      • Update HAL_CRYP_InCpltCallback() API to fix an incorrect condition call at resumption time
        • +
      • Update CRYP_AESCCM_Process_IT() to fix incorrect CCM header length management when data are fed to the peripheral under interrupt
    • HAL EXTI driver
        -
      • Update HAL_EXTI_GetConfigLine() to set default configuration value -of Trigger and GPIOSel before checking each corresponding register
        • +
      • Update HAL_EXTI_GetConfigLine() to set default configuration value of Trigger and GPIOSel before checking each corresponding register
    • HAL GPIO driver
        -
      • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR -register when Analog mode is selected
        • +
      • Update HAL_GPIO_Init() API to avoid the configuration of PUPDR register when Analog mode is selected
    • HAL HSEM driver
        @@ -633,8 +639,7 @@

        HAL Drivers updates

    • HAL I2C driver
        -
      • Updated I2C_IsAcknowledgeFailed() to avoid keeping I2C in busy state -if NACK is received after transmitting register address
        • +
      • Updated I2C_IsAcknowledgeFailed() to avoid keeping I2C in busy state if NACK is received after transmitting register address
    • HAL IRDA driver
        @@ -642,50 +647,38 @@

        HAL Drivers updates

    • HAL IWDG driver
        -
      • Updated HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout -vulnerability issue
        • +
      • Updated HAL_IWDG_Init() API in order to fix HAL_GetTick() timeout vulnerability issue
    • HAL LPTIM driver
        -
      • Update HAL_LPTIM_Init() API implementation to configure digital -filter for external clock when LPTIM is clocked by an internal clock -source
        • +
      • Update HAL_LPTIM_Init() API implementation to configure digital filter for external clock when LPTIM is clocked by an internal clock source
    • HAL PWR driver
        -
      • Correct HAL_PWREx_DisableInternalWakeUpLine() to update CM0+ -register
        • +
      • Correct HAL_PWREx_DisableInternalWakeUpLine() to update CM0+ register
    • HAL RCC driver
      • Update definition of IS_RCC_OSCILLATORTYPE() macro
        • -
      • Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted -derivative
        • -
      • Add new API HAL_RCC_GetResetSource() to get all reset sources and -clear flags for next reset
        • +
      • Update IS_RCC_PERIPHCLOCK() macro definition depending on targeted derivative
        • +
      • Add new API HAL_RCC_GetResetSource() to get all reset sources and clear flags for next reset
    • HAL RNG driver
        -
      • Update timeout mechanism to avoid false timeout detection in case of -preemption
        • +
      • Update timeout mechanism to avoid false timeout detection in case of preemption
    • HAL RTC driver
        -
      • Update HAL_RTC_DeactivateAlarm() to fix issue where Alarm Autoclear -remained activated after deactivating alarm
        • -
      • Update HAL_RTCEx_SetTimeStamp_IT() to avoid the call of TimeStamp -callback during the setting of the TimeStamp
        • -
      • Update assertions in HAL_RTC_SetAlarm() and HAL_RTC_SetAlarm_IT() to -allow user to unset some Alarm parameters when AlarmMask is set
        • +
      • Update HAL_RTC_DeactivateAlarm() to fix issue where Alarm Autoclear remained activated after deactivating alarm
        • +
      • Update HAL_RTCEx_SetTimeStamp_IT() to avoid the call of TimeStamp callback during the setting of the TimeStamp
        • +
      • Update assertions in HAL_RTC_SetAlarm() and HAL_RTC_SetAlarm_IT() to allow user to unset some Alarm parameters when AlarmMask is set
      • Update HAL_RTC_DeactivateAlarm() to clear Alarm Flag
      • Update HAL_RTCEx_DeactivateTimeStamp() to clear TimeStamp flag
        • -
      • Update HAL_RTCEx_DeactivateInternalTimeStamp() to clear Internal -TimeStamp flag +
      • Update HAL_RTCEx_DeactivateInternalTimeStamp() to clear Internal TimeStamp flag
        • The flag is cleared only if TSOVF & TSE are set to 0
        • -
      • Update HAL_RTCEx_DeactivateWakeUpTimer() to clear WakeUpTimer -flag
        • +
      • Update HAL_RTCEx_DeactivateWakeUpTimer() to clear WakeUpTimer flag
      • Update HAL_RTCEx_DeactivateSSRU() to clear SSR Underflow flag
      • Update HAL_RTC_WaitForSynchro() to fix issue to clear RSF flag
      • @@ -697,51 +690,37 @@

      HAL Drivers updates

      • Add support for Fast Mode Plus to be SMBUS Rev3 compliant:
          -
        • Add HAL_SMBUSEx_EnableFastModePlus() and -HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+
          • +
        • Add HAL_SMBUSEx_EnableFastModePlus() and HAL_SMBUSEx_DisableFastModePlus() APIs to manage Fm+
    • HAL SPI driver
        -
      • Update in SPI_WaitFifoStateUntilTimeout() to fix code optimization -issue
        • +
      • Update in SPI_WaitFifoStateUntilTimeout() to fix code optimization issue
      • Update to fix MISRA-C 2012 Rule-13.2 issue
    • HAL SUBGHZ driver
        -
      • Update HAL_Delay() by a polling loop to avoid blocking situation in -case of Systick is mapped on Tick
        • -
      • Update HAL_SUBGHZ_DeInit() to check RF Busy bit and deassert the -reset signal on RF side
        • +
      • Update HAL_Delay() by a polling loop to avoid blocking situation in case of Systick is mapped on Tick
        • +
      • Update HAL_SUBGHZ_DeInit() to check RF Busy bit and deassert the reset signal on RF side
    • HAL TIM driver
        -
      • Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop -(pooling and IT mode) to take into consideration all OutputChannel -parameters
        • +
      • Update HAL_TIMEx_OnePulseN_Start and HAL_TIMEx_OnePulseN_Stop (pooling and IT mode) to take into consideration all OutputChannel parameters
      • Correct CodeSpell typos in HAL TIM drivers
        • -
      • Update timeout mechanism to avoid false timeout detection in case of -preemption
        • -
      • Update input capture measurement in DMA mode to avoid zero return -values at high frequencies
        • +
      • Update timeout mechanism to avoid false timeout detection in case of preemption
        • +
      • Update input capture measurement in DMA mode to avoid zero return values at high frequencies
    • HAL UART driver
        -
      • Remove an invalid FIFO mode configuration from UART_SetConfig() as -it is not is not member of UART_InitTypeDef Structure
        • -
      • Update HAL_UART_IRQHandler() API to handle receiver timeout -interrupt +
      • Remove an invalid FIFO mode configuration from UART_SetConfig() as it is not is not member of UART_InitTypeDef Structure
        • +
      • Update HAL_UART_IRQHandler() API to handle receiver timeout interrupt
          -
        • Update UART receive processes (IT and DMA) to handle the UART -receive’s timeout interrupt
          • +
        • Update UART receive processes (IT and DMA) to handle the UART receive’s timeout interrupt
      • Update arrays definition to be declared as static const
        • -
      • Fix erroneous UART’s handle state in case of error returned after -DMA reception start within UART_Start_Receive_DMA()
        • -
      • Update UART ReceptionType management in case of ReceptionToIdle API -are called from RxEvent callback
        • -
      • Handling of UART concurrent register access in case of race -condition between Tx and Rx transfers (HAL UART and LL LPUART)
        • +
      • Fix erroneous UART’s handle state in case of error returned after DMA reception start within UART_Start_Receive_DMA()
        • +
      • Update UART ReceptionType management in case of ReceptionToIdle API are called from RxEvent callback
        • +
      • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)


    @@ -754,51 +733,40 @@

    LL Drivers updates

  • LL RTC driver
      -
    • Fix wrong reference of RTC instance in LL_RTC_TIME_Init() and -LL_RTC_DATE_Init() functions
      • +
    • Fix wrong reference of RTC instance in LL_RTC_TIME_Init() and LL_RTC_DATE_Init() functions
  • LL SPI driver
    • Updated to set the FRXTH bit for 8bit data in LL_SPI_Init() API
      • -
    • Update LL_SPI_TransmitData8() to avoid casting the result to 8 -bits
      • +
    • Update LL_SPI_TransmitData8() to avoid casting the result to 8 bits
  • LL TIM driver
      -
    • Updated LL_TIM_GetCounterMode() API to return the correct counter -mode
      • -
    • Update reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse -Mode
      • +
    • Updated LL_TIM_GetCounterMode() API to return the correct counter mode
      • +
    • Update reversed description of TIM_LL_EC_ONEPULSEMODE One Pulse Mode
  • LL LPUART driver
      -
    • Handling of UART concurrent register access in case of race -condition between Tx and Rx transfers (HAL UART and LL LPUART)
      • +
    • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
  • LL USART driver
      -
    • Handling of UART concurrent register access in case of race -condition between Tx and Rx transfers (HAL UART and LL LPUART)
      • -
    • LL_USART_ClockInit now supports clock phase and clock polarity -configuration for SPI_Slave mode
      • -
    • Remove useless check on maximum BRR value by removing -IS_LL_USART_BRR_MAX() macro
      • +
    • Handling of UART concurrent register access in case of race condition between Tx and Rx transfers (HAL UART and LL LPUART)
      • +
    • LL_USART_ClockInit now supports clock phase and clock polarity configuration for SPI_Slave mode
      • +
    • Remove useless check on maximum BRR value by removing IS_LL_USART_BRR_MAX() macro


    • -

    Known Limitations

    +

    Known Limitations

    None

    -

    Development Toolchains -and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
      • -
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain -V5.31
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.31
    • STM32CubeIDE 1.7.0
    -

    Supported Devices and -boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32WL55xx
      • @@ -806,35 +774,30 @@

      Supported Devices and
    • STM32WLE5xx
    • STM32WLE4xx

    -

    Backward Compatibility

    +

    Backward Compatibility

    Not applicable

    -

    Dependencies

    +

    Dependencies

    None


    - - +
    -

    Main Changes

    +

    Main Changes

    First Official Release

    -

    Contents

    +

    Contents

    First official release of LL / HAL Drivers for STM32WLxx series.

    -

    Known Limitations

    +

    Known Limitations

    None

    -

    Development Toolchains -and Compilers

    +

    Development Toolchains and Compilers

    • IAR Embedded Workbench for ARM (EWARM) toolchain V8.30.1
      • -
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain -V5.28
      • +
    • RealView Microcontroller Development Kit (MDK-ARM) toolchain V5.28
    • STM32CubeIDE 1.5.0
    -

    Supported Devices and -boards

    +

    Supported Devices and boards

    Supported Devices:

    • STM32WL55xx
      • @@ -842,25 +805,21 @@

      Supported Devices and
    • STM32WLE5xx
    • STM32WLE4xx

    -

    Backward Compatibility

    +

    Backward Compatibility

    Not applicable

    -

    Dependencies

    +

    Dependencies

    None


    -
    +