From 35a1f92cc008dcb98ec16fb0f1c14b635b57a87c Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Sat, 3 May 2025 18:30:13 -0700 Subject: [PATCH 01/20] Convert stm32-blink to SwiftPM Replaces bespoke shell scripts with a SwiftPM based build for the stm32-blink example. Adds CI for MachO based examples. Future: enable ELF variants of all MachO STM32 examples. --- .../{build-stm.yml => build-stm32-elf.yml} | 12 +- .github/workflows/build-stm32-macho.yml | 26 + stm32-blink/Board.swift | 115 - stm32-blink/Main.swift | 42 - stm32-blink/Makefile | 57 + stm32-blink/Package.resolved | 33 + stm32-blink/Package.swift | 34 + stm32-blink/README.md | 22 +- stm32-blink/Registers.swift | 178 -- .../Sources/Application/Application.swift | 55 + stm32-blink/Sources/STM32F7X6/Device.swift | 12 + stm32-blink/Sources/STM32F7X6/Empty.swift | 13 + stm32-blink/Sources/STM32F7X6/GPIOA.swift | 1075 +++++++ stm32-blink/Sources/STM32F7X6/GPIOI.swift | 7 + stm32-blink/Sources/STM32F7X6/RCC.swift | 2833 +++++++++++++++++ .../Sources/STM32F7X6/stm32f7x6.patched.svd | 1 + stm32-blink/Sources/STM32F7X6/svd2swift.json | 8 + stm32-blink/Sources/Support/Support.c | 51 + .../Support/include/Support.h} | 4 +- stm32-blink/Sources/Support/startup.S | 45 + stm32-blink/Startup.c | 44 - stm32-blink/build-elf.sh | 52 - stm32-blink/build-macho.sh | 56 - stm32-blink/elf-linkerscript.ld | 13 - 24 files changed, 4259 insertions(+), 529 deletions(-) rename .github/workflows/{build-stm.yml => build-stm32-elf.yml} (79%) create mode 100644 .github/workflows/build-stm32-macho.yml delete mode 100644 stm32-blink/Board.swift delete mode 100644 stm32-blink/Main.swift create mode 100644 stm32-blink/Makefile create mode 100644 stm32-blink/Package.resolved create mode 100644 stm32-blink/Package.swift delete mode 100644 stm32-blink/Registers.swift create mode 100644 stm32-blink/Sources/Application/Application.swift create mode 100644 stm32-blink/Sources/STM32F7X6/Device.swift create mode 100644 stm32-blink/Sources/STM32F7X6/Empty.swift create mode 100644 stm32-blink/Sources/STM32F7X6/GPIOA.swift create mode 100644 stm32-blink/Sources/STM32F7X6/GPIOI.swift create mode 100644 stm32-blink/Sources/STM32F7X6/RCC.swift create mode 120000 stm32-blink/Sources/STM32F7X6/stm32f7x6.patched.svd create mode 100644 stm32-blink/Sources/STM32F7X6/svd2swift.json create mode 100644 stm32-blink/Sources/Support/Support.c rename stm32-blink/{BridgingHeader.h => Sources/Support/include/Support.h} (77%) create mode 100644 stm32-blink/Sources/Support/startup.S delete mode 100644 stm32-blink/Startup.c delete mode 100755 stm32-blink/build-elf.sh delete mode 100755 stm32-blink/build-macho.sh delete mode 100644 stm32-blink/elf-linkerscript.ld diff --git a/.github/workflows/build-stm.yml b/.github/workflows/build-stm32-elf.yml similarity index 79% rename from .github/workflows/build-stm.yml rename to .github/workflows/build-stm32-elf.yml index 57afd2c0..c423e11e 100644 --- a/.github/workflows/build-stm.yml +++ b/.github/workflows/build-stm32-elf.yml @@ -1,4 +1,4 @@ -name: STM32 +name: STM32 ELF on: push: @@ -15,7 +15,7 @@ jobs: strategy: fail-fast: false matrix: - example: [stm32-blink, stm32-lvgl] + example: [stm32-lvgl] steps: - name: Checkout repo @@ -36,10 +36,6 @@ jobs: - name: Install Swift uses: ./.github/actions/install-swift - - name: Set environment variables - run: | - echo "STM_BOARD=STM32F746G_DISCOVERY" >> $GITHUB_ENV - - name: Build ${{ matrix.example }} working-directory: ${{ matrix.example }} run: | @@ -47,10 +43,6 @@ jobs: ./fetch-dependencies.sh fi - if [[ -f ./build-elf.sh ]]; then - ./build-elf.sh - fi - if [[ -f Makefile ]]; then make fi diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml new file mode 100644 index 00000000..4f93be1a --- /dev/null +++ b/.github/workflows/build-stm32-macho.yml @@ -0,0 +1,26 @@ +name: STM32 Macho + +on: + push: + branches: ["main"] + pull_request: + types: [opened, reopened, synchronize, ready_for_review] + workflow_dispatch: + +jobs: + build: + name: Build + runs-on: [self-hosted, macos] + + strategy: + fail-fast: false + matrix: + example: [stm32-blink, stm32-lcd-logo, stm32-neopixel, stm32-uart-echo] + + steps: + - name: Install Swift + uses: ./.github/actions/install-swift + + - name: Build ${{ matrix.example }} + working-directory: ${{ matrix.example }} + run: make diff --git a/stm32-blink/Board.swift b/stm32-blink/Board.swift deleted file mode 100644 index 130932e2..00000000 --- a/stm32-blink/Board.swift +++ /dev/null @@ -1,115 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#if STM32F746G_DISCOVERY - -typealias Board = STM32F746Board -enum STM32F746Board { - static func initialize() { - // (1) AHB1ENR[lecConfig.0] = 1 ... enable clock - setRegisterBit( - baseAddress: RCC.BaseAddress, offset: RCC.Offsets.AHB1ENR, - bit: RCC.AHB1ENRBit(for: ledConfig.0), - value: 1) - // (2) MODER[1] = 1 ... set mode to output - setRegisterTwoBitField( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.MODER, - bitsStartingAt: 2 * ledConfig.1, value: 1) - // (3) OTYPER[1] = 0 ... output type is push-pull - setRegisterBit( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.OTYPER, - bit: ledConfig.1, - value: 0) - // (4) OSPEEDR[1] = 2 ... speed is high - setRegisterTwoBitField( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.OSPEEDR, - bitsStartingAt: 2 * ledConfig.1, value: 2) - // (5) PUPDR[1] = 2 ... set pull to down - setRegisterTwoBitField( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.PUPDR, - bitsStartingAt: 2 * ledConfig.1, value: 2) - - ledOff() - } - - static func ledOn() { - // ODR[1] = 1 - setRegisterBit( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.ODR, bit: 1, - value: 1) - } - - static func ledOff() { - // ODR[1] = 0 - setRegisterBit( - baseAddress: GPIO.GPIOi_BaseAddress, offset: GPIO.Offsets.ODR, bit: 1, - value: 0) - } - - static func delay(milliseconds: Int) { - for _ in 0..<10_000 * milliseconds { - nop() - } - } -} - -#elseif NUCLEO_F103RB - -typealias Board = STM32F1Board -enum STM32F1Board { - static func initialize() { - // (1) APB2ENR[ledConfig.0] = 1 ... enable clock - setRegisterBit( - baseAddress: RCC.BaseAddress, offset: RCC.Offsets.APB2ENR, - bit: RCC.APB2ENRBit(for: ledConfig.0), - value: 1) - // (2) CRL.MODE[ledConfig.1] = 0b11 ... set mode to output, high speed - setRegisterTwoBitField( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.CRL, - bitsStartingAt: 4 * ledConfig.1, value: 3) - // (3) CRL.CNF[ledConfig.1] = 0b00 ... general purpose, push-pull - setRegisterTwoBitField( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.CRL, - bitsStartingAt: 4 * ledConfig.1 + 2, value: 0) - - ledOff() - } - - static func ledOn() { - // ODR[ledConfig.1] = 1 - setRegisterBit( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.ODR, bit: ledConfig.1, - value: 1) - } - - static func ledOff() { - // ODR[ledConfig.1] = 0 - setRegisterBit( - baseAddress: GPIO.GPIOBaseAddress(for: ledConfig.0), - offset: GPIO.Offsets.ODR, bit: ledConfig.1, - value: 0) - } - - static func delay(milliseconds: Int) { - for _ in 0..<10_000 * milliseconds { - nop() - } - } -} - -#else - -#error("Unknown board") - -#endif diff --git a/stm32-blink/Main.swift b/stm32-blink/Main.swift deleted file mode 100644 index 43d23858..00000000 --- a/stm32-blink/Main.swift +++ /dev/null @@ -1,42 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#if STM32F746G_DISCOVERY - -// I1 pin aka "Arduino D13" pin on STM32F746 Discovery Board -// https://www.st.com/resource/en/schematic_pack/mb1191-f746ngh6-c01_schematic.pdf -let ledConfig: (GPIOBank, GPIOPin) = (.i, 1) - -#elseif NUCLEO_F103RB - -// A5 pin aka "Arduino D13" pin on Nucleo-64 boards -// https://www.st.com/resource/en/user_manual/um1724-stm32-nucleo64-boards-mb1136-stmicroelectronics.pdf -let ledConfig: (GPIOBank, GPIOPin) = (.a, 5) - -#else - -#error("Unknown board") - -#endif - -@main -struct Main { - static func main() { - Board.initialize() - - while true { - Board.ledOn() - Board.delay(milliseconds: 100) - Board.ledOff() - Board.delay(milliseconds: 300) - } - } -} diff --git a/stm32-blink/Makefile b/stm32-blink/Makefile new file mode 100644 index 00000000..6b0125c0 --- /dev/null +++ b/stm32-blink/Makefile @@ -0,0 +1,57 @@ +##===----------------------------------------------------------------------===## +## +## This source file is part of the Swift open source project +## +## Copyright (c) 2025 Apple Inc. and the Swift project authors. +## Licensed under Apache License v2.0 with Runtime Library Exception +## +## See https://swift.org/LICENSE.txt for license information +## +##===----------------------------------------------------------------------===## + +# Paths +REPOROOT := $(shell git rev-parse --show-toplevel) +TOOLSROOT := $(REPOROOT)/Tools +TOOLSET := $(TOOLSROOT)/Toolsets/stm32f74x.json +MACHO2BIN := $(TOOLSROOT)/macho2bin.py +SWIFT_BUILD := swift build + +# Flags +ARCH := armv7em +TARGET := $(ARCH)-apple-none-macho +SWIFT_BUILD_ARGS := \ + --configuration release \ + --triple $(TARGET) \ + --toolset $(TOOLSET) +BUILDROOT := $(shell $(SWIFT_BUILD) $(SWIFT_BUILD_ARGS) --show-bin-path) + +.PHONY: build +build: + @echo "building..." + $(SWIFT_BUILD) \ + $(SWIFT_BUILD_ARGS) \ + -Xlinker -map -Xlinker $(BUILDROOT)/Application.mangled.map \ + --verbose + + @echo "demangling linker map..." + cat $(BUILDROOT)/Application.mangled.map \ + | c++filt | swift demangle > $(BUILDROOT)/Application.map + + @echo "disassembling..." + otool \ + -arch $(ARCH) -v -V -d -t \ + $(BUILDROOT)/Application \ + | c++filt | swift demangle > $(BUILDROOT)/Application.disassembly + + @echo "extracting binary..." + $(MACHO2BIN) \ + $(BUILDROOT)/Application \ + $(BUILDROOT)/Application.bin \ + --base-address 0x20010000 \ + --segments '__TEXT,__DATA,__VECTORS' + +.PHONY: clean +clean: + @echo "cleaning..." + @swift package clean + @rm -rf .build diff --git a/stm32-blink/Package.resolved b/stm32-blink/Package.resolved new file mode 100644 index 00000000..16cf145e --- /dev/null +++ b/stm32-blink/Package.resolved @@ -0,0 +1,33 @@ +{ + "originHash" : "649f7498720ea2d5d472883ada10b168fafd5de5f84e09ef1d499604823fce63", + "pins" : [ + { + "identity" : "swift-argument-parser", + "kind" : "remoteSourceControl", + "location" : "https://github.com/apple/swift-argument-parser.git", + "state" : { + "revision" : "41982a3656a71c768319979febd796c6fd111d5c", + "version" : "1.5.0" + } + }, + { + "identity" : "swift-mmio", + "kind" : "remoteSourceControl", + "location" : "https://github.com/apple/swift-mmio", + "state" : { + "branch" : "main", + "revision" : "5232c5129a8c70beafc3d6acfbae2716c1b6822a" + } + }, + { + "identity" : "swift-syntax", + "kind" : "remoteSourceControl", + "location" : "https://github.com/swiftlang/swift-syntax.git", + "state" : { + "revision" : "0687f71944021d616d34d922343dcef086855920", + "version" : "600.0.1" + } + } + ], + "version" : 3 +} diff --git a/stm32-blink/Package.swift b/stm32-blink/Package.swift new file mode 100644 index 00000000..2e7f3432 --- /dev/null +++ b/stm32-blink/Package.swift @@ -0,0 +1,34 @@ +// swift-tools-version: 6.0 + +import PackageDescription + +let package = Package( + name: "stm32-blink", + products: [ + .executable(name: "Application", targets: ["Application"]) + ], + dependencies: [ + .package(url: "https://github.com/apple/swift-mmio", branch: "main") + ], + targets: [ + .executableTarget( + name: "Application", + dependencies: ["STM32F7X6", "Support"]), + // SVD2Swift \ + // --input ../Tools/SVDs/stm32f7x6.patched.svd \ + // --output Sources/Application/Registers \ + // --access-level public \ + // --indentation-width 2 \ + // --peripherals GPIOA GPIOI RCC + .target( + name: "STM32F7X6", + dependencies: [ + .product(name: "MMIO", package: "swift-mmio") + ], + plugins: [ + // Plugin disabled because SwiftPM is slow. + // .plugin(name: "SVD2SwiftPlugin", package: "swift-mmio") + ]), + .target(name: "Support"), + ], + swiftLanguageModes: [.v5]) diff --git a/stm32-blink/README.md b/stm32-blink/README.md index 12797e03..6ed6e112 100644 --- a/stm32-blink/README.md +++ b/stm32-blink/README.md @@ -15,29 +15,17 @@ This example shows a simple baremetal firmware for an STM32 board that blinks an - Build and upload the program to flash memory of the microcontroller: ```console $ cd stm32-blink -$ export STM_BOARD=STM32F746G_DISCOVERY # or NUCLEO_F103RB -$ ./build-macho.sh -$ st-flash --reset write .build/blink.bin 0x08000000 +$ make +$ st-flash --reset write .build/Application.bin 0x08000000 ``` -- The green LED next to the RESET button should now be blinking in a pattern. - -## Building and running the firmware as ELF (on either macOS or Linux) - -- Build and upload the program to flash memory of the microcontroller: -```console -$ cd stm32-blink -$ export STM_BOARD=STM32F746G_DISCOVERY # or NUCLEO_F103RB -$ ./build-elf.sh -$ st-flash --format ihex --reset write .build/blink.hex -``` -- The green LED next to the RESET button should now be blinking in a pattern. +- The green LED next to the RESET button should now be blinking. ## Binary size The resulting size of the compiled and linked binary is very small (which shouldn't be surprising given that this toy example only blinks an LED), and demonstrates how the Embedded Swift compilation mode doesn't include unnecessary code or data in the resulting program: ```console -$ size -m .build/blink +$ size -m .build/Application Segment __TEXT: 656 Section __text: 142 total 142 @@ -51,6 +39,6 @@ total 1300 The binary contains only 142 bytes of code! Additionally, the vector table needed by the CPU is actually dominating the size of the final firmware. Note that the `__LINKEDIT` segment is discarded when forming the final `.bin` file, which is 1168 bytes in size: ```console -$ cat .build/blink.bin | wc -c +$ cat .build/Application.bin | wc -c 1168 ``` diff --git a/stm32-blink/Registers.swift b/stm32-blink/Registers.swift deleted file mode 100644 index ccbf13fb..00000000 --- a/stm32-blink/Registers.swift +++ /dev/null @@ -1,178 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -// swift-format-ignore-file - -import _Volatile - -#if STM32F746G_DISCOVERY - -// Register definitions for STM32F746NG MCU -// https://www.st.com/resource/en/reference_manual/rm0385-stm32f75xxx-and-stm32f74xxx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -enum GPIOBank: Int { - case a, b, c, d, e, f, g, h, i, j, k -} -typealias GPIOPin = Int - -enum RCC { - static let BaseAddress = UnsafeMutablePointer(bitPattern: 0x40023800 as UInt)! - enum Offsets { - static let AHB1ENR = 0x30 - } - enum Bits { - static let AHB1ENR_GPIOAEN = 0 - static let AHB1ENR_GPIOBEN = 1 - static let AHB1ENR_GPIOCEN = 2 - static let AHB1ENR_GPIODEN = 3 - static let AHB1ENR_GPIOEEN = 4 - static let AHB1ENR_GPIOFEN = 5 - static let AHB1ENR_GPIOGEN = 6 - static let AHB1ENR_GPIOHEN = 7 - static let AHB1ENR_GPIOIEN = 8 - static let AHB1ENR_GPIOJEN = 9 - static let AHB1ENR_GPIOKEN = 10 - } - - static func AHB1ENRBit(for bank: GPIOBank) -> Int { - return switch bank { - case .a: Bits.AHB1ENR_GPIOAEN - case .b: Bits.AHB1ENR_GPIOBEN - case .c: Bits.AHB1ENR_GPIOCEN - case .d: Bits.AHB1ENR_GPIODEN - case .e: Bits.AHB1ENR_GPIOEEN - case .f: Bits.AHB1ENR_GPIOFEN - case .g: Bits.AHB1ENR_GPIOGEN - case .h: Bits.AHB1ENR_GPIOHEN - case .i: Bits.AHB1ENR_GPIOIEN - case .j: Bits.AHB1ENR_GPIOJEN - case .k: Bits.AHB1ENR_GPIOKEN - } - } -} - -enum GPIO { - static let GPIOa_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020000 as UInt)! - static let GPIOb_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020400 as UInt)! - static let GPIOc_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020800 as UInt)! - static let GPIOd_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40020c00 as UInt)! - static let GPIOe_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021000 as UInt)! - static let GPIOf_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021400 as UInt)! - static let GPIOg_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021800 as UInt)! - static let GPIOh_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021c00 as UInt)! - static let GPIOi_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40022000 as UInt)! - static let GPIOj_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40022400 as UInt)! - static let GPIOk_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40022800 as UInt)! - - enum Offsets { - static let MODER = 0x0 - static let OTYPER = 0x4 - static let OSPEEDR = 0x8 - static let PUPDR = 0xc - static let IDR = 0x10 - static let ODR = 0x14 - } -} - -#elseif NUCLEO_F103RB - -// Register definitions for STM32F103RB MCU -// https://www.st.com/resource/en/reference_manual/rm0008-stm32f101xx-stm32f102xx-stm32f103xx-stm32f105xx-and-stm32f107xx-advanced-armbased-32bit-mcus-stmicroelectronics.pdf - -enum GPIOBank: Int { - case a, b, c, d, e, f, g -} -typealias GPIOPin = Int - -enum RCC { - static let BaseAddress = UnsafeMutablePointer(bitPattern: 0x40021000 as UInt)! - enum Offsets { - static let APB2ENR = 0x18 - } - enum Bits { - static let APB2ENR_IOPAEN = 2 - static let APB2ENR_IOPBEN = 3 - static let APB2ENR_IOPCEN = 4 - static let APB2ENR_IOPDEN = 5 - static let APB2ENR_IOPEEN = 6 - static let APB2ENR_IOPFEN = 7 - static let APB2ENR_IOPGEN = 8 - } - - static func APB2ENRBit(for bank: GPIOBank) -> Int { - return switch bank { - case .a: Bits.APB2ENR_IOPAEN - case .b: Bits.APB2ENR_IOPBEN - case .c: Bits.APB2ENR_IOPCEN - case .d: Bits.APB2ENR_IOPDEN - case .e: Bits.APB2ENR_IOPEEN - case .f: Bits.APB2ENR_IOPFEN - case .g: Bits.APB2ENR_IOPGEN - } - } -} - -enum GPIO { - static let GPIOa_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40010800 as UInt)! - static let GPIOb_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40010c00 as UInt)! - static let GPIOc_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011000 as UInt)! - static let GPIOd_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011400 as UInt)! - static let GPIOe_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011800 as UInt)! - static let GPIOf_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40011c00 as UInt)! - static let GPIOg_BaseAddress = UnsafeMutablePointer(bitPattern: 0x40012000 as UInt)! - - static func GPIOBaseAddress(for bank: GPIOBank) -> UnsafeMutablePointer { - return switch bank { - case .a: GPIOa_BaseAddress - case .b: GPIOb_BaseAddress - case .c: GPIOc_BaseAddress - case .d: GPIOd_BaseAddress - case .e: GPIOe_BaseAddress - case .f: GPIOf_BaseAddress - case .g: GPIOg_BaseAddress - } - } - - enum Offsets { - static let CRL = 0x0 - static let CRH = 0x4 - static let IDR = 0x8 - static let ODR = 0xc - } -} - -#else - -#error("Unknown board") - -#endif - -func setRegisterBit(baseAddress: UnsafeMutablePointer, offset: Int, bit: Int, value: Int) { - precondition(offset % 4 == 0) - precondition(bit >= 0 && bit < 32) - precondition(value >= 0 && value < 2) - let p = baseAddress.advanced(by: offset / 4) - let m = VolatileMappedRegister(unsafeBitPattern: UInt(bitPattern: p)) - let previousValue: UInt32 = m.load() - let newValue: UInt32 = previousValue & ~(1 << UInt32(bit)) | (UInt32(value) << UInt32(bit)) - m.store(newValue) -} - -func setRegisterTwoBitField(baseAddress: UnsafeMutablePointer, offset: Int, bitsStartingAt: Int, value: Int) { - precondition(offset % 4 == 0) - precondition(bitsStartingAt >= 0 && bitsStartingAt < 31) - precondition(value >= 0 && value < 4) - let p = baseAddress.advanced(by: offset / 4) - let m = VolatileMappedRegister(unsafeBitPattern: UInt(bitPattern: p)) - let previousValue: UInt32 = m.load() - let newValue: UInt32 = previousValue & ~(0b11 << UInt32(bitsStartingAt)) | (UInt32(value) << UInt32(bitsStartingAt)) - m.store(newValue) -} diff --git a/stm32-blink/Sources/Application/Application.swift b/stm32-blink/Sources/Application/Application.swift new file mode 100644 index 00000000..34727b84 --- /dev/null +++ b/stm32-blink/Sources/Application/Application.swift @@ -0,0 +1,55 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2023 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +import Support +import STM32F7X6 + +// I1 pin aka "Arduino D13" pin on STM32F746 Discovery Board +// https://www.st.com/resource/en/schematic_pack/mb1191-f746ngh6-c01_schematic.pdf +// let ledConfig: (GPIOBank, GPIOPin) = (.i, 1) + +@main +struct Application { + static func main() { + // MARK: Clock configuration + rcc.ahb1enr.modify { rw in + // Enable AHB clock to port I + rw.raw.gpioien = 1 + } + + // MARK: Peripheral Configuration + // Configure I1 as GPIO Out + // Put Pin I1 into output mode + gpioi.moder.modify { $0.raw.moder1 = 0b1 } + // Put Pin I1 into push pull + gpioi.otyper.modify { $0.raw.ot1 = 0b0 } + // Put Pin I1 into low speed + gpioi.ospeedr.modify { $0.raw.ospeedr1 = 0b00 } + // Enable pull down on Pin I1 + gpioi.pupdr.modify { $0.raw.pupdr1 = 0b10 } + + var enable = false + while true { + // Enable/Disable LED + gpioi.odr.modify { rw in + rw.raw.odr1 = enable ? 1 : 0 + } + enable.toggle() + delay(milliseconds: 100) + } + } +} + +func delay(milliseconds: Int) { + for _ in 0..<10_000 * milliseconds { + nop() + } +} diff --git a/stm32-blink/Sources/STM32F7X6/Device.swift b/stm32-blink/Sources/STM32F7X6/Device.swift new file mode 100644 index 00000000..ff04f654 --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/Device.swift @@ -0,0 +1,12 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public let gpioa = GPIOA(unsafeAddress: 0x40020000) + +/// General-purpose I/Os +public let gpioi = GPIOI(unsafeAddress: 0x40022000) + +/// Reset and clock control +public let rcc = RCC(unsafeAddress: 0x40023800) diff --git a/stm32-blink/Sources/STM32F7X6/Empty.swift b/stm32-blink/Sources/STM32F7X6/Empty.swift new file mode 100644 index 00000000..934a795a --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/Empty.swift @@ -0,0 +1,13 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +// This file is intentionally left empty for SwiftPM to recognize the target as +// a Swift source module. diff --git a/stm32-blink/Sources/STM32F7X6/GPIOA.swift b/stm32-blink/Sources/STM32F7X6/GPIOA.swift new file mode 100644 index 00000000..a70e68c7 --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/GPIOA.swift @@ -0,0 +1,1075 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +@RegisterBlock +public struct GPIOA { + /// GPIO port mode register + @RegisterBlock(offset: 0x0) + public var moder: Register + + /// GPIO port output type register + @RegisterBlock(offset: 0x4) + public var otyper: Register + + /// GPIO port output speed register + @RegisterBlock(offset: 0x8) + public var ospeedr: Register + + /// GPIO port pull-up/pull-down register + @RegisterBlock(offset: 0xc) + public var pupdr: Register + + /// GPIO port input data register + @RegisterBlock(offset: 0x10) + public var idr: Register + + /// GPIO port output data register + @RegisterBlock(offset: 0x14) + public var odr: Register + + /// GPIO port bit set/reset register + @RegisterBlock(offset: 0x18) + public var bsrr: Register + + /// GPIO port configuration lock register + @RegisterBlock(offset: 0x1c) + public var lckr: Register + + /// GPIO alternate function low register + @RegisterBlock(offset: 0x20) + public var afrl: Register + + /// GPIO alternate function high register + @RegisterBlock(offset: 0x24) + public var afrh: Register + + /// GPIO port bit reset register + @RegisterBlock(offset: 0x28) + public var brr: Register +} + +extension GPIOA { + /// GPIO port mode register + @Register(bitWidth: 32) + public struct MODER { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 30..<32) + public var moder15: MODER15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 28..<30) + public var moder14: MODER14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 26..<28) + public var moder13: MODER13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 24..<26) + public var moder12: MODER12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 22..<24) + public var moder11: MODER11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 20..<22) + public var moder10: MODER10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 18..<20) + public var moder9: MODER9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 16..<18) + public var moder8: MODER8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<16) + public var moder7: MODER7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<14) + public var moder6: MODER6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<12) + public var moder5: MODER5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<10) + public var moder4: MODER4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<8) + public var moder3: MODER3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<6) + public var moder2: MODER2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<4) + public var moder1: MODER1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<2, as: MODER0Values.self) + public var moder0: MODER0 + } + + /// GPIO port output type register + @Register(bitWidth: 32) + public struct OTYPER { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 15..<16) + public var ot15: OT15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<15) + public var ot14: OT14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 13..<14) + public var ot13: OT13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<13) + public var ot12: OT12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 11..<12) + public var ot11: OT11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<11) + public var ot10: OT10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 9..<10) + public var ot9: OT9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<9) + public var ot8: OT8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 7..<8) + public var ot7: OT7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<7) + public var ot6: OT6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 5..<6) + public var ot5: OT5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<5) + public var ot4: OT4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 3..<4) + public var ot3: OT3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<3) + public var ot2: OT2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 1..<2) + public var ot1: OT1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<1, as: OT0Values.self) + public var ot0: OT0 + } + + /// GPIO port output speed register + @Register(bitWidth: 32) + public struct OSPEEDR { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 30..<32) + public var ospeedr15: OSPEEDR15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 28..<30) + public var ospeedr14: OSPEEDR14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 26..<28) + public var ospeedr13: OSPEEDR13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 24..<26) + public var ospeedr12: OSPEEDR12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 22..<24) + public var ospeedr11: OSPEEDR11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 20..<22) + public var ospeedr10: OSPEEDR10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 18..<20) + public var ospeedr9: OSPEEDR9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 16..<18) + public var ospeedr8: OSPEEDR8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<16) + public var ospeedr7: OSPEEDR7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<14) + public var ospeedr6: OSPEEDR6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<12) + public var ospeedr5: OSPEEDR5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<10) + public var ospeedr4: OSPEEDR4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<8) + public var ospeedr3: OSPEEDR3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<6) + public var ospeedr2: OSPEEDR2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<4) + public var ospeedr1: OSPEEDR1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<2, as: OSPEEDR0Values.self) + public var ospeedr0: OSPEEDR0 + } + + /// GPIO port pull-up/pull-down register + @Register(bitWidth: 32) + public struct PUPDR { + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 30..<32) + public var pupdr15: PUPDR15 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 28..<30) + public var pupdr14: PUPDR14 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 26..<28) + public var pupdr13: PUPDR13 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 24..<26) + public var pupdr12: PUPDR12 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 22..<24) + public var pupdr11: PUPDR11 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 20..<22) + public var pupdr10: PUPDR10 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 18..<20) + public var pupdr9: PUPDR9 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 16..<18) + public var pupdr8: PUPDR8 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 14..<16) + public var pupdr7: PUPDR7 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 12..<14) + public var pupdr6: PUPDR6 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 10..<12) + public var pupdr5: PUPDR5 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 8..<10) + public var pupdr4: PUPDR4 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 6..<8) + public var pupdr3: PUPDR3 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 4..<6) + public var pupdr2: PUPDR2 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 2..<4) + public var pupdr1: PUPDR1 + + /// Port x configuration bits (y = 0..15) + @ReadWrite(bits: 0..<2, as: PUPDR0Values.self) + public var pupdr0: PUPDR0 + } + + /// GPIO port input data register + @Register(bitWidth: 32) + public struct IDR { + /// Port input data (y = 0..15) + @ReadOnly(bits: 15..<16) + public var idr15: IDR15 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 14..<15) + public var idr14: IDR14 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 13..<14) + public var idr13: IDR13 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 12..<13) + public var idr12: IDR12 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 11..<12) + public var idr11: IDR11 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 10..<11) + public var idr10: IDR10 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 9..<10) + public var idr9: IDR9 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 8..<9) + public var idr8: IDR8 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 7..<8) + public var idr7: IDR7 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 6..<7) + public var idr6: IDR6 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 5..<6) + public var idr5: IDR5 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 4..<5) + public var idr4: IDR4 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 3..<4) + public var idr3: IDR3 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 2..<3) + public var idr2: IDR2 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 1..<2) + public var idr1: IDR1 + + /// Port input data (y = 0..15) + @ReadOnly(bits: 0..<1) + public var idr0: IDR0 + } + + /// GPIO port output data register + @Register(bitWidth: 32) + public struct ODR { + /// Port output data (y = 0..15) + @ReadWrite(bits: 15..<16) + public var odr15: ODR15 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 14..<15) + public var odr14: ODR14 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 13..<14) + public var odr13: ODR13 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 12..<13) + public var odr12: ODR12 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 11..<12) + public var odr11: ODR11 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 10..<11) + public var odr10: ODR10 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 9..<10) + public var odr9: ODR9 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 8..<9) + public var odr8: ODR8 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 7..<8) + public var odr7: ODR7 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 6..<7) + public var odr6: ODR6 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 5..<6) + public var odr5: ODR5 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 4..<5) + public var odr4: ODR4 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 3..<4) + public var odr3: ODR3 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 2..<3) + public var odr2: ODR2 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 1..<2) + public var odr1: ODR1 + + /// Port output data (y = 0..15) + @ReadWrite(bits: 0..<1, as: ODR0Values.self) + public var odr0: ODR0 + } + + /// GPIO port bit set/reset register + @Register(bitWidth: 32) + public struct BSRR { + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 31..<32) + public var br15: BR15 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 30..<31) + public var br14: BR14 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 29..<30) + public var br13: BR13 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 28..<29) + public var br12: BR12 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 27..<28) + public var br11: BR11 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 26..<27) + public var br10: BR10 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 25..<26) + public var br9: BR9 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 24..<25) + public var br8: BR8 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 23..<24) + public var br7: BR7 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 22..<23) + public var br6: BR6 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 21..<22) + public var br5: BR5 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 20..<21) + public var br4: BR4 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 19..<20) + public var br3: BR3 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 18..<19) + public var br2: BR2 + + /// Port x reset bit y (y = 0..15) + @WriteOnly(bits: 17..<18) + public var br1: BR1 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 16..<17) + public var br0: BR0 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 15..<16) + public var bs15: BS15 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 14..<15) + public var bs14: BS14 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 13..<14) + public var bs13: BS13 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 12..<13) + public var bs12: BS12 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 11..<12) + public var bs11: BS11 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 10..<11) + public var bs10: BS10 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 9..<10) + public var bs9: BS9 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 8..<9) + public var bs8: BS8 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 7..<8) + public var bs7: BS7 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 6..<7) + public var bs6: BS6 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 5..<6) + public var bs5: BS5 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 4..<5) + public var bs4: BS4 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 3..<4) + public var bs3: BS3 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 2..<3) + public var bs2: BS2 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 1..<2) + public var bs1: BS1 + + /// Port x set bit y (y= 0..15) + @WriteOnly(bits: 0..<1) + public var bs0: BS0 + } + + /// GPIO port configuration lock register + @Register(bitWidth: 32) + public struct LCKR { + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 16..<17, as: LCKKValues.self) + public var lckk: LCKK + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 15..<16) + public var lck15: LCK15 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 14..<15) + public var lck14: LCK14 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 13..<14) + public var lck13: LCK13 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 12..<13) + public var lck12: LCK12 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 11..<12) + public var lck11: LCK11 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 10..<11) + public var lck10: LCK10 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 9..<10) + public var lck9: LCK9 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 8..<9) + public var lck8: LCK8 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 7..<8) + public var lck7: LCK7 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 6..<7) + public var lck6: LCK6 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 5..<6) + public var lck5: LCK5 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 4..<5) + public var lck4: LCK4 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 3..<4) + public var lck3: LCK3 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 2..<3) + public var lck2: LCK2 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 1..<2) + public var lck1: LCK1 + + /// Port x lock bit y (y= 0..15) + @ReadWrite(bits: 0..<1, as: LCK0Values.self) + public var lck0: LCK0 + } + + /// GPIO alternate function low register + @Register(bitWidth: 32) + public struct AFRL { + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 28..<32) + public var afrl7: AFRL7 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 24..<28) + public var afrl6: AFRL6 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 20..<24) + public var afrl5: AFRL5 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 16..<20) + public var afrl4: AFRL4 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 12..<16) + public var afrl3: AFRL3 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 8..<12) + public var afrl2: AFRL2 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 4..<8) + public var afrl1: AFRL1 + + /// Alternate function selection for port x bit y (y = 0..7) + @ReadWrite(bits: 0..<4, as: AFRL0Values.self) + public var afrl0: AFRL0 + } + + /// GPIO alternate function high register + @Register(bitWidth: 32) + public struct AFRH { + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 28..<32) + public var afrh15: AFRH15 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 24..<28) + public var afrh14: AFRH14 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 20..<24) + public var afrh13: AFRH13 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 16..<20) + public var afrh12: AFRH12 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 12..<16) + public var afrh11: AFRH11 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 8..<12) + public var afrh10: AFRH10 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 4..<8) + public var afrh9: AFRH9 + + /// Alternate function selection for port x bit y (y = 8..15) + @ReadWrite(bits: 0..<4, as: AFRH8Values.self) + public var afrh8: AFRH8 + } + + /// GPIO port bit reset register + @Register(bitWidth: 32) + public struct BRR { + /// Port A Reset bit 0 + @ReadWrite(bits: 0..<1) + public var br0: BR0 + + /// Port A Reset bit 1 + @ReadWrite(bits: 1..<2) + public var br1: BR1 + + /// Port A Reset bit 2 + @ReadWrite(bits: 2..<3) + public var br2: BR2 + + /// Port A Reset bit 3 + @ReadWrite(bits: 3..<4) + public var br3: BR3 + + /// Port A Reset bit 4 + @ReadWrite(bits: 4..<5) + public var br4: BR4 + + /// Port A Reset bit 5 + @ReadWrite(bits: 5..<6) + public var br5: BR5 + + /// Port A Reset bit 6 + @ReadWrite(bits: 6..<7) + public var br6: BR6 + + /// Port A Reset bit 7 + @ReadWrite(bits: 7..<8) + public var br7: BR7 + + /// Port A Reset bit 8 + @ReadWrite(bits: 8..<9) + public var br8: BR8 + + /// Port A Reset bit 9 + @ReadWrite(bits: 9..<10) + public var br9: BR9 + + /// Port A Reset bit 10 + @ReadWrite(bits: 10..<11) + public var br10: BR10 + + /// Port A Reset bit 11 + @ReadWrite(bits: 11..<12) + public var br11: BR11 + + /// Port A Reset bit 12 + @ReadWrite(bits: 12..<13) + public var br12: BR12 + + /// Port A Reset bit 13 + @ReadWrite(bits: 13..<14) + public var br13: BR13 + + /// Port A Reset bit 14 + @ReadWrite(bits: 14..<15) + public var br14: BR14 + + /// Port A Reset bit 15 + @ReadWrite(bits: 15..<16) + public var br15: BR15 + } +} + +extension GPIOA.MODER { + public struct MODER0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Input mode (reset state) + public static let Input = Self(rawValue: 0x0) + + /// General purpose output mode + public static let Output = Self(rawValue: 0x1) + + /// Alternate function mode + public static let Alternate = Self(rawValue: 0x2) + + /// Analog mode + public static let Analog = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OTYPER { + public struct OT0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Output push-pull (reset state) + public static let PushPull = Self(rawValue: 0x0) + + /// Output open-drain + public static let OpenDrain = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.OSPEEDR { + public struct OSPEEDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Low speed + public static let LowSpeed = Self(rawValue: 0x0) + + /// Medium speed + public static let MediumSpeed = Self(rawValue: 0x1) + + /// High speed + public static let HighSpeed = Self(rawValue: 0x2) + + /// Very high speed + public static let VeryHighSpeed = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.PUPDR { + public struct PUPDR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// No pull-up, pull-down + public static let Floating = Self(rawValue: 0x0) + + /// Pull-up + public static let PullUp = Self(rawValue: 0x1) + + /// Pull-down + public static let PullDown = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.ODR { + public struct ODR0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Set output to logic low + public static let Low = Self(rawValue: 0x0) + + /// Set output to logic high + public static let High = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + public struct LCKKValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Port configuration lock key not active + public static let NotActive = Self(rawValue: 0x0) + + /// Port configuration lock key active + public static let Active = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.LCKR { + public struct LCK0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Port configuration not locked + public static let Unlocked = Self(rawValue: 0x0) + + /// Port configuration locked + public static let Locked = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRL { + public struct AFRL0Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// AF0 + public static let AF0 = Self(rawValue: 0x0) + + /// AF1 + public static let AF1 = Self(rawValue: 0x1) + + /// AF2 + public static let AF2 = Self(rawValue: 0x2) + + /// AF3 + public static let AF3 = Self(rawValue: 0x3) + + /// AF4 + public static let AF4 = Self(rawValue: 0x4) + + /// AF5 + public static let AF5 = Self(rawValue: 0x5) + + /// AF6 + public static let AF6 = Self(rawValue: 0x6) + + /// AF7 + public static let AF7 = Self(rawValue: 0x7) + + /// AF8 + public static let AF8 = Self(rawValue: 0x8) + + /// AF9 + public static let AF9 = Self(rawValue: 0x9) + + /// AF10 + public static let AF10 = Self(rawValue: 0xa) + + /// AF11 + public static let AF11 = Self(rawValue: 0xb) + + /// AF12 + public static let AF12 = Self(rawValue: 0xc) + + /// AF13 + public static let AF13 = Self(rawValue: 0xd) + + /// AF14 + public static let AF14 = Self(rawValue: 0xe) + + /// AF15 + public static let AF15 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension GPIOA.AFRH { + public struct AFRH8Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// AF0 + public static let AF0 = Self(rawValue: 0x0) + + /// AF1 + public static let AF1 = Self(rawValue: 0x1) + + /// AF2 + public static let AF2 = Self(rawValue: 0x2) + + /// AF3 + public static let AF3 = Self(rawValue: 0x3) + + /// AF4 + public static let AF4 = Self(rawValue: 0x4) + + /// AF5 + public static let AF5 = Self(rawValue: 0x5) + + /// AF6 + public static let AF6 = Self(rawValue: 0x6) + + /// AF7 + public static let AF7 = Self(rawValue: 0x7) + + /// AF8 + public static let AF8 = Self(rawValue: 0x8) + + /// AF9 + public static let AF9 = Self(rawValue: 0x9) + + /// AF10 + public static let AF10 = Self(rawValue: 0xa) + + /// AF11 + public static let AF11 = Self(rawValue: 0xb) + + /// AF12 + public static let AF12 = Self(rawValue: 0xc) + + /// AF13 + public static let AF13 = Self(rawValue: 0xd) + + /// AF14 + public static let AF14 = Self(rawValue: 0xe) + + /// AF15 + public static let AF15 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-blink/Sources/STM32F7X6/GPIOI.swift b/stm32-blink/Sources/STM32F7X6/GPIOI.swift new file mode 100644 index 00000000..6b2b5182 --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/GPIOI.swift @@ -0,0 +1,7 @@ +// Generated by svd2swift. + +import MMIO + +/// General-purpose I/Os +public typealias GPIOI = GPIOA + diff --git a/stm32-blink/Sources/STM32F7X6/RCC.swift b/stm32-blink/Sources/STM32F7X6/RCC.swift new file mode 100644 index 00000000..4a36aea8 --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/RCC.swift @@ -0,0 +1,2833 @@ +// Generated by svd2swift. + +import MMIO + +/// Reset and clock control +@RegisterBlock +public struct RCC { + /// clock control register + @RegisterBlock(offset: 0x0) + public var cr: Register + + /// PLL configuration register + @RegisterBlock(offset: 0x4) + public var pllcfgr: Register + + /// clock configuration register + @RegisterBlock(offset: 0x8) + public var cfgr: Register + + /// clock interrupt register + @RegisterBlock(offset: 0xc) + public var cir: Register + + /// AHB1 peripheral reset register + @RegisterBlock(offset: 0x10) + public var ahb1rstr: Register + + /// AHB2 peripheral reset register + @RegisterBlock(offset: 0x14) + public var ahb2rstr: Register + + /// AHB3 peripheral reset register + @RegisterBlock(offset: 0x18) + public var ahb3rstr: Register + + /// APB1 peripheral reset register + @RegisterBlock(offset: 0x20) + public var apb1rstr: Register + + /// APB2 peripheral reset register + @RegisterBlock(offset: 0x24) + public var apb2rstr: Register + + /// AHB1 peripheral clock register + @RegisterBlock(offset: 0x30) + public var ahb1enr: Register + + /// AHB2 peripheral clock enable register + @RegisterBlock(offset: 0x34) + public var ahb2enr: Register + + /// AHB3 peripheral clock enable register + @RegisterBlock(offset: 0x38) + public var ahb3enr: Register + + /// APB1 peripheral clock enable register + @RegisterBlock(offset: 0x40) + public var apb1enr: Register + + /// APB2 peripheral clock enable register + @RegisterBlock(offset: 0x44) + public var apb2enr: Register + + /// AHB1 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x50) + public var ahb1lpenr: Register + + /// AHB2 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x54) + public var ahb2lpenr: Register + + /// AHB3 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x58) + public var ahb3lpenr: Register + + /// APB1 peripheral clock enable in low power mode register + @RegisterBlock(offset: 0x60) + public var apb1lpenr: Register + + /// APB2 peripheral clock enabled in low power mode register + @RegisterBlock(offset: 0x64) + public var apb2lpenr: Register + + /// Backup domain control register + @RegisterBlock(offset: 0x70) + public var bdcr: Register + + /// clock control & status register + @RegisterBlock(offset: 0x74) + public var csr: Register + + /// spread spectrum clock generation register + @RegisterBlock(offset: 0x80) + public var sscgr: Register + + /// PLLI2S configuration register + @RegisterBlock(offset: 0x84) + public var plli2scfgr: Register + + /// PLL configuration register + @RegisterBlock(offset: 0x88) + public var pllsaicfgr: Register + + /// dedicated clocks configuration register + @RegisterBlock(offset: 0x8c) + public var dckcfgr1: Register + + /// dedicated clocks configuration register + @RegisterBlock(offset: 0x90) + public var dckcfgr2: Register +} + +extension RCC { + /// clock control register + @Register(bitWidth: 32) + public struct CR { + /// PLLI2S clock ready flag + @ReadOnly(bits: 27..<28) + public var plli2srdy: PLLI2SRDY + + /// PLLI2S enable + @ReadWrite(bits: 26..<27) + public var plli2son: PLLI2SON + + /// Main PLL (PLL) clock ready flag + @ReadOnly(bits: 25..<26) + public var pllrdy: PLLRDY + + /// Main PLL (PLL) enable + @ReadWrite(bits: 24..<25) + public var pllon: PLLON + + /// Clock security system enable + @ReadWrite(bits: 19..<20, as: CSSONValues.self) + public var csson: CSSON + + /// HSE clock bypass + @ReadWrite(bits: 18..<19, as: HSEBYPValues.self) + public var hsebyp: HSEBYP + + /// HSE clock ready flag + @ReadOnly(bits: 17..<18) + public var hserdy: HSERDY + + /// HSE clock enable + @ReadWrite(bits: 16..<17) + public var hseon: HSEON + + /// Internal high-speed clock calibration + @ReadOnly(bits: 8..<16) + public var hsical: HSICAL + + /// Internal high-speed clock trimming + @ReadWrite(bits: 3..<8) + public var hsitrim: HSITRIM + + /// Internal high-speed clock ready flag + @ReadOnly(bits: 1..<2) + public var hsirdy: HSIRDY + + /// Internal high-speed clock enable + @ReadWrite(bits: 0..<1, as: HSIONValues.self) + public var hsion: HSION + + /// PLLSAI clock ready flag + @ReadOnly(bits: 29..<30) + public var pllsairdy: PLLSAIRDY + + /// PLLSAI enable + @ReadWrite(bits: 28..<29) + public var pllsaion: PLLSAION + } + + /// PLL configuration register + @Register(bitWidth: 32) + public struct PLLCFGR { + /// Main PLL(PLL) and audio PLL (PLLI2S) entry clock source + @ReadWrite(bits: 22..<23, as: PLLSRCValues.self) + public var pllsrc: PLLSRC + + /// Division factor for the main PLL (PLL) and audio PLL (PLLI2S) input clock + @ReadWrite(bits: 0..<6) + public var pllm: PLLM + + /// Main PLL (PLL) multiplication factor for VCO + @ReadWrite(bits: 6..<15) + public var plln: PLLN + + /// Main PLL (PLL) division factor for main system clock + @ReadWrite(bits: 16..<18, as: PLLPValues.self) + public var pllp: PLLP + + /// Main PLL (PLL) division factor for USB OTG FS, SDIO and random number generator clocks + @ReadWrite(bits: 24..<28) + public var pllq: PLLQ + } + + /// clock configuration register + @Register(bitWidth: 32) + public struct CFGR { + /// Microcontroller clock output 2 + @ReadWrite(bits: 30..<32, as: MCO2Values.self) + public var mco2: MCO2 + + /// MCO2 prescaler + @ReadWrite(bits: 27..<30) + public var mco2pre: MCO2PRE + + /// MCO1 prescaler + @ReadWrite(bits: 24..<27, as: MCO1PREValues.self) + public var mco1pre: MCO1PRE + + /// I2S clock selection + @ReadWrite(bits: 23..<24, as: I2SSRCValues.self) + public var i2ssrc: I2SSRC + + /// Microcontroller clock output 1 + @ReadWrite(bits: 21..<23, as: MCO1Values.self) + public var mco1: MCO1 + + /// HSE division factor for RTC clock + @ReadWrite(bits: 16..<21) + public var rtcpre: RTCPRE + + /// APB high-speed prescaler (APB2) + @ReadWrite(bits: 13..<16) + public var ppre2: PPRE2 + + /// APB Low speed prescaler (APB1) + @ReadWrite(bits: 10..<13, as: PPRE1Values.self) + public var ppre1: PPRE1 + + /// AHB prescaler + @ReadWrite(bits: 4..<8, as: HPREValues.self) + public var hpre: HPRE + + /// System clock switch + @Reserved(bits: 0..<2, as: SWValues.self) + public var sw: SW + + /// System clock switch status + @Reserved(bits: 2..<4) + public var sws: SWS + } + + /// clock interrupt register + @Register(bitWidth: 32) + public struct CIR { + /// Clock security system interrupt clear + @WriteOnly(bits: 23..<24) + public var cssc: CSSC + + /// PLLSAI Ready Interrupt Clear + @WriteOnly(bits: 22..<23) + public var pllsairdyc: PLLSAIRDYC + + /// PLLI2S ready interrupt clear + @WriteOnly(bits: 21..<22) + public var plli2srdyc: PLLI2SRDYC + + /// Main PLL(PLL) ready interrupt clear + @WriteOnly(bits: 20..<21) + public var pllrdyc: PLLRDYC + + /// HSE ready interrupt clear + @WriteOnly(bits: 19..<20) + public var hserdyc: HSERDYC + + /// HSI ready interrupt clear + @WriteOnly(bits: 18..<19) + public var hsirdyc: HSIRDYC + + /// LSE ready interrupt clear + @WriteOnly(bits: 17..<18) + public var lserdyc: LSERDYC + + /// LSI ready interrupt clear + @WriteOnly(bits: 16..<17) + public var lsirdyc: LSIRDYC + + /// PLLSAI Ready Interrupt Enable + @ReadWrite(bits: 14..<15) + public var pllsairdyie: PLLSAIRDYIE + + /// PLLI2S ready interrupt enable + @ReadWrite(bits: 13..<14) + public var plli2srdyie: PLLI2SRDYIE + + /// Main PLL (PLL) ready interrupt enable + @ReadWrite(bits: 12..<13) + public var pllrdyie: PLLRDYIE + + /// HSE ready interrupt enable + @ReadWrite(bits: 11..<12) + public var hserdyie: HSERDYIE + + /// HSI ready interrupt enable + @ReadWrite(bits: 10..<11) + public var hsirdyie: HSIRDYIE + + /// LSE ready interrupt enable + @ReadWrite(bits: 9..<10) + public var lserdyie: LSERDYIE + + /// LSI ready interrupt enable + @ReadWrite(bits: 8..<9, as: LSIRDYIEValues.self) + public var lsirdyie: LSIRDYIE + + /// Clock security system interrupt flag + @ReadOnly(bits: 7..<8) + public var cssf: CSSF + + /// PLLSAI ready interrupt flag + @ReadOnly(bits: 6..<7) + public var pllsairdyf: PLLSAIRDYF + + /// PLLI2S ready interrupt flag + @ReadOnly(bits: 5..<6) + public var plli2srdyf: PLLI2SRDYF + + /// Main PLL (PLL) ready interrupt flag + @ReadOnly(bits: 4..<5) + public var pllrdyf: PLLRDYF + + /// HSE ready interrupt flag + @ReadOnly(bits: 3..<4) + public var hserdyf: HSERDYF + + /// HSI ready interrupt flag + @ReadOnly(bits: 2..<3) + public var hsirdyf: HSIRDYF + + /// LSE ready interrupt flag + @ReadOnly(bits: 1..<2) + public var lserdyf: LSERDYF + + /// LSI ready interrupt flag + @ReadOnly(bits: 0..<1) + public var lsirdyf: LSIRDYF + } + + /// AHB1 peripheral reset register + @Register(bitWidth: 32) + public struct AHB1RSTR { + /// USB OTG HS module reset + @ReadWrite(bits: 29..<30) + public var otghsrst: OTGHSRST + + /// Ethernet MAC reset + @ReadWrite(bits: 25..<26) + public var ethmacrst: ETHMACRST + + /// DMA2D reset + @ReadWrite(bits: 23..<24) + public var dma2drst: DMA2DRST + + /// DMA2 reset + @ReadWrite(bits: 22..<23) + public var dma2rst: DMA2RST + + /// DMA2 reset + @ReadWrite(bits: 21..<22) + public var dma1rst: DMA1RST + + /// CRC reset + @ReadWrite(bits: 12..<13) + public var crcrst: CRCRST + + /// IO port K reset + @ReadWrite(bits: 10..<11) + public var gpiokrst: GPIOKRST + + /// IO port J reset + @ReadWrite(bits: 9..<10) + public var gpiojrst: GPIOJRST + + /// IO port I reset + @ReadWrite(bits: 8..<9) + public var gpioirst: GPIOIRST + + /// IO port H reset + @ReadWrite(bits: 7..<8) + public var gpiohrst: GPIOHRST + + /// IO port G reset + @ReadWrite(bits: 6..<7) + public var gpiogrst: GPIOGRST + + /// IO port F reset + @ReadWrite(bits: 5..<6) + public var gpiofrst: GPIOFRST + + /// IO port E reset + @ReadWrite(bits: 4..<5) + public var gpioerst: GPIOERST + + /// IO port D reset + @ReadWrite(bits: 3..<4) + public var gpiodrst: GPIODRST + + /// IO port C reset + @ReadWrite(bits: 2..<3) + public var gpiocrst: GPIOCRST + + /// IO port B reset + @ReadWrite(bits: 1..<2) + public var gpiobrst: GPIOBRST + + /// IO port A reset + @ReadWrite(bits: 0..<1, as: GPIOARSTValues.self) + public var gpioarst: GPIOARST + } + + /// AHB2 peripheral reset register + @Register(bitWidth: 32) + public struct AHB2RSTR { + /// USB OTG FS module reset + @ReadWrite(bits: 7..<8) + public var otgfsrst: OTGFSRST + + /// Random number generator module reset + @ReadWrite(bits: 6..<7) + public var rngrst: RNGRST + + /// Hash module reset + @ReadWrite(bits: 5..<6) + public var hsahrst: HSAHRST + + /// Cryptographic module reset + @ReadWrite(bits: 4..<5) + public var cryprst: CRYPRST + + /// Camera interface reset + @ReadWrite(bits: 0..<1, as: DCMIRSTValues.self) + public var dcmirst: DCMIRST + } + + /// AHB3 peripheral reset register + @Register(bitWidth: 32) + public struct AHB3RSTR { + /// Flexible memory controller module reset + @ReadWrite(bits: 0..<1, as: FMCRSTValues.self) + public var fmcrst: FMCRST + + /// Quad SPI memory controller reset + @ReadWrite(bits: 1..<2) + public var qspirst: QSPIRST + } + + /// APB1 peripheral reset register + @Register(bitWidth: 32) + public struct APB1RSTR { + /// TIM2 reset + @ReadWrite(bits: 0..<1, as: TIM2RSTValues.self) + public var tim2rst: TIM2RST + + /// TIM3 reset + @ReadWrite(bits: 1..<2) + public var tim3rst: TIM3RST + + /// TIM4 reset + @ReadWrite(bits: 2..<3) + public var tim4rst: TIM4RST + + /// TIM5 reset + @ReadWrite(bits: 3..<4) + public var tim5rst: TIM5RST + + /// TIM6 reset + @ReadWrite(bits: 4..<5) + public var tim6rst: TIM6RST + + /// TIM7 reset + @ReadWrite(bits: 5..<6) + public var tim7rst: TIM7RST + + /// TIM12 reset + @ReadWrite(bits: 6..<7) + public var tim12rst: TIM12RST + + /// TIM13 reset + @ReadWrite(bits: 7..<8) + public var tim13rst: TIM13RST + + /// TIM14 reset + @ReadWrite(bits: 8..<9) + public var tim14rst: TIM14RST + + /// Window watchdog reset + @ReadWrite(bits: 11..<12) + public var wwdgrst: WWDGRST + + /// SPI 2 reset + @ReadWrite(bits: 14..<15) + public var spi2rst: SPI2RST + + /// SPI 3 reset + @ReadWrite(bits: 15..<16) + public var spi3rst: SPI3RST + + /// USART 2 reset + @ReadWrite(bits: 17..<18) + public var usart2rst: USART2RST + + /// USART 3 reset + @ReadWrite(bits: 18..<19) + public var usart3rst: USART3RST + + /// USART 4 reset + @ReadWrite(bits: 19..<20) + public var uart4rst: UART4RST + + /// USART 5 reset + @ReadWrite(bits: 20..<21) + public var uart5rst: UART5RST + + /// I2C 1 reset + @ReadWrite(bits: 21..<22) + public var i2c1rst: I2C1RST + + /// I2C 2 reset + @ReadWrite(bits: 22..<23) + public var i2c2rst: I2C2RST + + /// I2C3 reset + @ReadWrite(bits: 23..<24) + public var i2c3rst: I2C3RST + + /// CAN1 reset + @ReadWrite(bits: 25..<26) + public var can1rst: CAN1RST + + /// CAN2 reset + @ReadWrite(bits: 26..<27) + public var can2rst: CAN2RST + + /// Power interface reset + @ReadWrite(bits: 28..<29) + public var pwrrst: PWRRST + + /// DAC reset + @ReadWrite(bits: 29..<30) + public var dacrst: DACRST + + /// UART7 reset + @ReadWrite(bits: 30..<31) + public var uart7rst: UART7RST + + /// UART8 reset + @ReadWrite(bits: 31..<32) + public var uart8rst: UART8RST + + /// SPDIF-RX reset + @ReadWrite(bits: 16..<17) + public var spdifrxrst: SPDIFRXRST + + /// HDMI-CEC reset + @ReadWrite(bits: 27..<28) + public var cecrst: CECRST + + /// Low power timer 1 reset + @ReadWrite(bits: 9..<10) + public var lptim1rst: LPTIM1RST + + /// I2C 4 reset + @ReadWrite(bits: 24..<25) + public var i2c4rst: I2C4RST + } + + /// APB2 peripheral reset register + @Register(bitWidth: 32) + public struct APB2RSTR { + /// TIM1 reset + @ReadWrite(bits: 0..<1, as: TIM1RSTValues.self) + public var tim1rst: TIM1RST + + /// TIM8 reset + @ReadWrite(bits: 1..<2) + public var tim8rst: TIM8RST + + /// USART1 reset + @ReadWrite(bits: 4..<5) + public var usart1rst: USART1RST + + /// USART6 reset + @ReadWrite(bits: 5..<6) + public var usart6rst: USART6RST + + /// ADC interface reset (common to all ADCs) + @ReadWrite(bits: 8..<9) + public var adcrst: ADCRST + + /// SPI 1 reset + @ReadWrite(bits: 12..<13) + public var spi1rst: SPI1RST + + /// SPI4 reset + @ReadWrite(bits: 13..<14) + public var spi4rst: SPI4RST + + /// System configuration controller reset + @ReadWrite(bits: 14..<15) + public var syscfgrst: SYSCFGRST + + /// TIM9 reset + @ReadWrite(bits: 16..<17) + public var tim9rst: TIM9RST + + /// TIM10 reset + @ReadWrite(bits: 17..<18) + public var tim10rst: TIM10RST + + /// TIM11 reset + @ReadWrite(bits: 18..<19) + public var tim11rst: TIM11RST + + /// SPI5 reset + @ReadWrite(bits: 20..<21) + public var spi5rst: SPI5RST + + /// SPI6 reset + @ReadWrite(bits: 21..<22) + public var spi6rst: SPI6RST + + /// SAI1 reset + @ReadWrite(bits: 22..<23) + public var sai1rst: SAI1RST + + /// LTDC reset + @ReadWrite(bits: 26..<27) + public var ltdcrst: LTDCRST + + /// SAI2 reset + @ReadWrite(bits: 23..<24) + public var sai2rst: SAI2RST + + /// SDMMC1 reset + @ReadWrite(bits: 11..<12) + public var sdmmc1rst: SDMMC1RST + } + + /// AHB1 peripheral clock register + @Register(bitWidth: 32) + public struct AHB1ENR { + /// USB OTG HSULPI clock enable + @ReadWrite(bits: 30..<31) + public var otghsulpien: OTGHSULPIEN + + /// USB OTG HS clock enable + @ReadWrite(bits: 29..<30) + public var otghsen: OTGHSEN + + /// Ethernet PTP clock enable + @ReadWrite(bits: 28..<29) + public var ethmacptpen: ETHMACPTPEN + + /// Ethernet Reception clock enable + @ReadWrite(bits: 27..<28) + public var ethmacrxen: ETHMACRXEN + + /// Ethernet Transmission clock enable + @ReadWrite(bits: 26..<27) + public var ethmactxen: ETHMACTXEN + + /// Ethernet MAC clock enable + @ReadWrite(bits: 25..<26) + public var ethmacen: ETHMACEN + + /// DMA2D clock enable + @ReadWrite(bits: 23..<24) + public var dma2den: DMA2DEN + + /// DMA2 clock enable + @ReadWrite(bits: 22..<23) + public var dma2en: DMA2EN + + /// DMA1 clock enable + @ReadWrite(bits: 21..<22) + public var dma1en: DMA1EN + + /// CCM data RAM clock enable + @ReadWrite(bits: 20..<21) + public var dtcmramen: DTCMRAMEN + + /// Backup SRAM interface clock enable + @ReadWrite(bits: 18..<19) + public var bkpsramen: BKPSRAMEN + + /// CRC clock enable + @ReadWrite(bits: 12..<13) + public var crcen: CRCEN + + /// IO port K clock enable + @ReadWrite(bits: 10..<11) + public var gpioken: GPIOKEN + + /// IO port J clock enable + @ReadWrite(bits: 9..<10) + public var gpiojen: GPIOJEN + + /// IO port I clock enable + @ReadWrite(bits: 8..<9) + public var gpioien: GPIOIEN + + /// IO port H clock enable + @ReadWrite(bits: 7..<8) + public var gpiohen: GPIOHEN + + /// IO port G clock enable + @ReadWrite(bits: 6..<7) + public var gpiogen: GPIOGEN + + /// IO port F clock enable + @ReadWrite(bits: 5..<6) + public var gpiofen: GPIOFEN + + /// IO port E clock enable + @ReadWrite(bits: 4..<5) + public var gpioeen: GPIOEEN + + /// IO port D clock enable + @ReadWrite(bits: 3..<4) + public var gpioden: GPIODEN + + /// IO port C clock enable + @ReadWrite(bits: 2..<3) + public var gpiocen: GPIOCEN + + /// IO port B clock enable + @ReadWrite(bits: 1..<2) + public var gpioben: GPIOBEN + + /// IO port A clock enable + @ReadWrite(bits: 0..<1, as: GPIOAENValues.self) + public var gpioaen: GPIOAEN + } + + /// AHB2 peripheral clock enable register + @Register(bitWidth: 32) + public struct AHB2ENR { + /// USB OTG FS clock enable + @ReadWrite(bits: 7..<8) + public var otgfsen: OTGFSEN + + /// Random number generator clock enable + @ReadWrite(bits: 6..<7) + public var rngen: RNGEN + + /// Hash modules clock enable + @ReadWrite(bits: 5..<6) + public var hashen: HASHEN + + /// Cryptographic modules clock enable + @ReadWrite(bits: 4..<5) + public var crypen: CRYPEN + + /// Camera interface enable + @ReadWrite(bits: 0..<1, as: DCMIENValues.self) + public var dcmien: DCMIEN + } + + /// AHB3 peripheral clock enable register + @Register(bitWidth: 32) + public struct AHB3ENR { + /// Flexible memory controller module clock enable + @ReadWrite(bits: 0..<1, as: FMCENValues.self) + public var fmcen: FMCEN + + /// Quad SPI memory controller clock enable + @ReadWrite(bits: 1..<2) + public var qspien: QSPIEN + } + + /// APB1 peripheral clock enable register + @Register(bitWidth: 32) + public struct APB1ENR { + /// TIM2 clock enable + @ReadWrite(bits: 0..<1, as: TIM2ENValues.self) + public var tim2en: TIM2EN + + /// TIM3 clock enable + @ReadWrite(bits: 1..<2) + public var tim3en: TIM3EN + + /// TIM4 clock enable + @ReadWrite(bits: 2..<3) + public var tim4en: TIM4EN + + /// TIM5 clock enable + @ReadWrite(bits: 3..<4) + public var tim5en: TIM5EN + + /// TIM6 clock enable + @ReadWrite(bits: 4..<5) + public var tim6en: TIM6EN + + /// TIM7 clock enable + @ReadWrite(bits: 5..<6) + public var tim7en: TIM7EN + + /// TIM12 clock enable + @ReadWrite(bits: 6..<7) + public var tim12en: TIM12EN + + /// TIM13 clock enable + @ReadWrite(bits: 7..<8) + public var tim13en: TIM13EN + + /// TIM14 clock enable + @ReadWrite(bits: 8..<9) + public var tim14en: TIM14EN + + /// Window watchdog clock enable + @ReadWrite(bits: 11..<12) + public var wwdgen: WWDGEN + + /// SPI2 clock enable + @ReadWrite(bits: 14..<15) + public var spi2en: SPI2EN + + /// SPI3 clock enable + @ReadWrite(bits: 15..<16) + public var spi3en: SPI3EN + + /// USART 2 clock enable + @ReadWrite(bits: 17..<18) + public var usart2en: USART2EN + + /// USART3 clock enable + @ReadWrite(bits: 18..<19) + public var usart3en: USART3EN + + /// UART4 clock enable + @ReadWrite(bits: 19..<20) + public var uart4en: UART4EN + + /// UART5 clock enable + @ReadWrite(bits: 20..<21) + public var uart5en: UART5EN + + /// I2C1 clock enable + @ReadWrite(bits: 21..<22) + public var i2c1en: I2C1EN + + /// I2C2 clock enable + @ReadWrite(bits: 22..<23) + public var i2c2en: I2C2EN + + /// I2C3 clock enable + @ReadWrite(bits: 23..<24) + public var i2c3en: I2C3EN + + /// CAN 1 clock enable + @ReadWrite(bits: 25..<26) + public var can1en: CAN1EN + + /// CAN 2 clock enable + @ReadWrite(bits: 26..<27) + public var can2en: CAN2EN + + /// Power interface clock enable + @ReadWrite(bits: 28..<29) + public var pwren: PWREN + + /// DAC interface clock enable + @ReadWrite(bits: 29..<30) + public var dacen: DACEN + + /// UART7 clock enable + @ReadWrite(bits: 30..<31) + public var uart7en: UART7EN + + /// UART8 clock enable + @ReadWrite(bits: 31..<32) + public var uart8en: UART8EN + + /// SPDIF-RX clock enable + @ReadWrite(bits: 16..<17) + public var spdifrxen: SPDIFRXEN + + /// HDMI-CEN clock enable + @ReadWrite(bits: 27..<28) + public var cecen: CECEN + + /// Low power timer 1 clock enable + @ReadWrite(bits: 9..<10) + public var lptim1en: LPTIM1EN + + /// I2C4 clock enable + @ReadWrite(bits: 24..<25) + public var i2c4en: I2C4EN + } + + /// APB2 peripheral clock enable register + @Register(bitWidth: 32) + public struct APB2ENR { + /// TIM1 clock enable + @ReadWrite(bits: 0..<1, as: TIM1ENValues.self) + public var tim1en: TIM1EN + + /// TIM8 clock enable + @ReadWrite(bits: 1..<2) + public var tim8en: TIM8EN + + /// USART1 clock enable + @ReadWrite(bits: 4..<5) + public var usart1en: USART1EN + + /// USART6 clock enable + @ReadWrite(bits: 5..<6) + public var usart6en: USART6EN + + /// ADC1 clock enable + @ReadWrite(bits: 8..<9) + public var adc1en: ADC1EN + + /// ADC2 clock enable + @ReadWrite(bits: 9..<10) + public var adc2en: ADC2EN + + /// ADC3 clock enable + @ReadWrite(bits: 10..<11) + public var adc3en: ADC3EN + + /// SPI1 clock enable + @ReadWrite(bits: 12..<13) + public var spi1en: SPI1EN + + /// SPI4 clock enable + @ReadWrite(bits: 13..<14) + public var spi4en: SPI4EN + + /// System configuration controller clock enable + @ReadWrite(bits: 14..<15) + public var syscfgen: SYSCFGEN + + /// TIM9 clock enable + @ReadWrite(bits: 16..<17) + public var tim9en: TIM9EN + + /// TIM10 clock enable + @ReadWrite(bits: 17..<18) + public var tim10en: TIM10EN + + /// TIM11 clock enable + @ReadWrite(bits: 18..<19) + public var tim11en: TIM11EN + + /// SPI5 clock enable + @ReadWrite(bits: 20..<21) + public var spi5en: SPI5EN + + /// SPI6 clock enable + @ReadWrite(bits: 21..<22) + public var spi6en: SPI6EN + + /// SAI1 clock enable + @ReadWrite(bits: 22..<23) + public var sai1en: SAI1EN + + /// LTDC clock enable + @ReadWrite(bits: 26..<27) + public var ltdcen: LTDCEN + + /// SAI2 clock enable + @ReadWrite(bits: 23..<24) + public var sai2en: SAI2EN + + /// SDMMC1 clock enable + @ReadWrite(bits: 11..<12) + public var sdmmc1en: SDMMC1EN + } + + /// AHB1 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct AHB1LPENR { + /// IO port A clock enable during sleep mode + @ReadWrite(bits: 0..<1, as: GPIOALPENValues.self) + public var gpioalpen: GPIOALPEN + + /// IO port B clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var gpioblpen: GPIOBLPEN + + /// IO port C clock enable during Sleep mode + @ReadWrite(bits: 2..<3) + public var gpioclpen: GPIOCLPEN + + /// IO port D clock enable during Sleep mode + @ReadWrite(bits: 3..<4) + public var gpiodlpen: GPIODLPEN + + /// IO port E clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var gpioelpen: GPIOELPEN + + /// IO port F clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var gpioflpen: GPIOFLPEN + + /// IO port G clock enable during Sleep mode + @ReadWrite(bits: 6..<7) + public var gpioglpen: GPIOGLPEN + + /// IO port H clock enable during Sleep mode + @ReadWrite(bits: 7..<8) + public var gpiohlpen: GPIOHLPEN + + /// IO port I clock enable during Sleep mode + @ReadWrite(bits: 8..<9) + public var gpioilpen: GPIOILPEN + + /// IO port J clock enable during Sleep mode + @ReadWrite(bits: 9..<10) + public var gpiojlpen: GPIOJLPEN + + /// IO port K clock enable during Sleep mode + @ReadWrite(bits: 10..<11) + public var gpioklpen: GPIOKLPEN + + /// CRC clock enable during Sleep mode + @ReadWrite(bits: 12..<13) + public var crclpen: CRCLPEN + + /// Flash interface clock enable during Sleep mode + @ReadWrite(bits: 15..<16) + public var flitflpen: FLITFLPEN + + /// SRAM 1interface clock enable during Sleep mode + @ReadWrite(bits: 16..<17) + public var sram1lpen: SRAM1LPEN + + /// SRAM 2 interface clock enable during Sleep mode + @ReadWrite(bits: 17..<18) + public var sram2lpen: SRAM2LPEN + + /// Backup SRAM interface clock enable during Sleep mode + @ReadWrite(bits: 18..<19) + public var bkpsramlpen: BKPSRAMLPEN + + /// SRAM 3 interface clock enable during Sleep mode + @ReadWrite(bits: 19..<20) + public var sram3lpen: SRAM3LPEN + + /// DMA1 clock enable during Sleep mode + @ReadWrite(bits: 21..<22) + public var dma1lpen: DMA1LPEN + + /// DMA2 clock enable during Sleep mode + @ReadWrite(bits: 22..<23) + public var dma2lpen: DMA2LPEN + + /// DMA2D clock enable during Sleep mode + @ReadWrite(bits: 23..<24) + public var dma2dlpen: DMA2DLPEN + + /// Ethernet MAC clock enable during Sleep mode + @ReadWrite(bits: 25..<26) + public var ethmaclpen: ETHMACLPEN + + /// Ethernet transmission clock enable during Sleep mode + @ReadWrite(bits: 26..<27) + public var ethmactxlpen: ETHMACTXLPEN + + /// Ethernet reception clock enable during Sleep mode + @ReadWrite(bits: 27..<28) + public var ethmacrxlpen: ETHMACRXLPEN + + /// Ethernet PTP clock enable during Sleep mode + @ReadWrite(bits: 28..<29) + public var ethmacptplpen: ETHMACPTPLPEN + + /// USB OTG HS clock enable during Sleep mode + @ReadWrite(bits: 29..<30) + public var otghslpen: OTGHSLPEN + + /// USB OTG HS ULPI clock enable during Sleep mode + @ReadWrite(bits: 30..<31) + public var otghsulpilpen: OTGHSULPILPEN + + /// AXI to AHB bridge clock enable during Sleep mode + @ReadWrite(bits: 13..<14) + public var axilpen: AXILPEN + + /// DTCM RAM interface clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + public var dtcmlpen: DTCMLPEN + } + + /// AHB2 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct AHB2LPENR { + /// USB OTG FS clock enable during Sleep mode + @ReadWrite(bits: 7..<8) + public var otgfslpen: OTGFSLPEN + + /// Random number generator clock enable during Sleep mode + @ReadWrite(bits: 6..<7) + public var rnglpen: RNGLPEN + + /// Hash modules clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var hashlpen: HASHLPEN + + /// Cryptography modules clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var cryplpen: CRYPLPEN + + /// Camera interface enable during Sleep mode + @ReadWrite(bits: 0..<1, as: DCMILPENValues.self) + public var dcmilpen: DCMILPEN + } + + /// AHB3 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct AHB3LPENR { + /// Flexible memory controller module clock enable during Sleep mode + @ReadWrite(bits: 0..<1, as: FMCLPENValues.self) + public var fmclpen: FMCLPEN + + /// Quand SPI memory controller clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var qspilpen: QSPILPEN + } + + /// APB1 peripheral clock enable in low power mode register + @Register(bitWidth: 32) + public struct APB1LPENR { + /// TIM2 clock enable during Sleep mode + @ReadWrite(bits: 0..<1, as: TIM2LPENValues.self) + public var tim2lpen: TIM2LPEN + + /// TIM3 clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var tim3lpen: TIM3LPEN + + /// TIM4 clock enable during Sleep mode + @ReadWrite(bits: 2..<3) + public var tim4lpen: TIM4LPEN + + /// TIM5 clock enable during Sleep mode + @ReadWrite(bits: 3..<4) + public var tim5lpen: TIM5LPEN + + /// TIM6 clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var tim6lpen: TIM6LPEN + + /// TIM7 clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var tim7lpen: TIM7LPEN + + /// TIM12 clock enable during Sleep mode + @ReadWrite(bits: 6..<7) + public var tim12lpen: TIM12LPEN + + /// TIM13 clock enable during Sleep mode + @ReadWrite(bits: 7..<8) + public var tim13lpen: TIM13LPEN + + /// TIM14 clock enable during Sleep mode + @ReadWrite(bits: 8..<9) + public var tim14lpen: TIM14LPEN + + /// Window watchdog clock enable during Sleep mode + @ReadWrite(bits: 11..<12) + public var wwdglpen: WWDGLPEN + + /// SPI2 clock enable during Sleep mode + @ReadWrite(bits: 14..<15) + public var spi2lpen: SPI2LPEN + + /// SPI3 clock enable during Sleep mode + @ReadWrite(bits: 15..<16) + public var spi3lpen: SPI3LPEN + + /// USART2 clock enable during Sleep mode + @ReadWrite(bits: 17..<18) + public var usart2lpen: USART2LPEN + + /// USART3 clock enable during Sleep mode + @ReadWrite(bits: 18..<19) + public var usart3lpen: USART3LPEN + + /// UART4 clock enable during Sleep mode + @ReadWrite(bits: 19..<20) + public var uart4lpen: UART4LPEN + + /// UART5 clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + public var uart5lpen: UART5LPEN + + /// I2C1 clock enable during Sleep mode + @ReadWrite(bits: 21..<22) + public var i2c1lpen: I2C1LPEN + + /// I2C2 clock enable during Sleep mode + @ReadWrite(bits: 22..<23) + public var i2c2lpen: I2C2LPEN + + /// I2C3 clock enable during Sleep mode + @ReadWrite(bits: 23..<24) + public var i2c3lpen: I2C3LPEN + + /// CAN 1 clock enable during Sleep mode + @ReadWrite(bits: 25..<26) + public var can1lpen: CAN1LPEN + + /// CAN 2 clock enable during Sleep mode + @ReadWrite(bits: 26..<27) + public var can2lpen: CAN2LPEN + + /// Power interface clock enable during Sleep mode + @ReadWrite(bits: 28..<29) + public var pwrlpen: PWRLPEN + + /// DAC interface clock enable during Sleep mode + @ReadWrite(bits: 29..<30) + public var daclpen: DACLPEN + + /// UART7 clock enable during Sleep mode + @ReadWrite(bits: 30..<31) + public var uart7lpen: UART7LPEN + + /// UART8 clock enable during Sleep mode + @ReadWrite(bits: 31..<32) + public var uart8lpen: UART8LPEN + + /// SPDIF-RX clock enable during sleep mode + @ReadWrite(bits: 16..<17) + public var spdifrxlpen: SPDIFRXLPEN + + /// HDMI-CEN clock enable during Sleep mode + @ReadWrite(bits: 27..<28) + public var ceclpen: CECLPEN + + /// low power timer 1 clock enable during Sleep mode + @ReadWrite(bits: 9..<10) + public var lptim1lpen: LPTIM1LPEN + + /// I2C4 clock enable during Sleep mode + @ReadWrite(bits: 24..<25) + public var i2c4lpen: I2C4LPEN + } + + /// APB2 peripheral clock enabled in low power mode register + @Register(bitWidth: 32) + public struct APB2LPENR { + /// TIM1 clock enable during Sleep mode + @ReadWrite(bits: 0..<1, as: TIM1LPENValues.self) + public var tim1lpen: TIM1LPEN + + /// TIM8 clock enable during Sleep mode + @ReadWrite(bits: 1..<2) + public var tim8lpen: TIM8LPEN + + /// USART1 clock enable during Sleep mode + @ReadWrite(bits: 4..<5) + public var usart1lpen: USART1LPEN + + /// USART6 clock enable during Sleep mode + @ReadWrite(bits: 5..<6) + public var usart6lpen: USART6LPEN + + /// ADC1 clock enable during Sleep mode + @ReadWrite(bits: 8..<9) + public var adc1lpen: ADC1LPEN + + /// ADC2 clock enable during Sleep mode + @ReadWrite(bits: 9..<10) + public var adc2lpen: ADC2LPEN + + /// ADC 3 clock enable during Sleep mode + @ReadWrite(bits: 10..<11) + public var adc3lpen: ADC3LPEN + + /// SPI 1 clock enable during Sleep mode + @ReadWrite(bits: 12..<13) + public var spi1lpen: SPI1LPEN + + /// SPI 4 clock enable during Sleep mode + @ReadWrite(bits: 13..<14) + public var spi4lpen: SPI4LPEN + + /// System configuration controller clock enable during Sleep mode + @ReadWrite(bits: 14..<15) + public var syscfglpen: SYSCFGLPEN + + /// TIM9 clock enable during sleep mode + @ReadWrite(bits: 16..<17) + public var tim9lpen: TIM9LPEN + + /// TIM10 clock enable during Sleep mode + @ReadWrite(bits: 17..<18) + public var tim10lpen: TIM10LPEN + + /// TIM11 clock enable during Sleep mode + @ReadWrite(bits: 18..<19) + public var tim11lpen: TIM11LPEN + + /// SPI 5 clock enable during Sleep mode + @ReadWrite(bits: 20..<21) + public var spi5lpen: SPI5LPEN + + /// SPI 6 clock enable during Sleep mode + @ReadWrite(bits: 21..<22) + public var spi6lpen: SPI6LPEN + + /// SAI1 clock enable during sleep mode + @ReadWrite(bits: 22..<23) + public var sai1lpen: SAI1LPEN + + /// LTDC clock enable during sleep mode + @ReadWrite(bits: 26..<27) + public var ltdclpen: LTDCLPEN + + /// SAI2 clock enable during sleep mode + @ReadWrite(bits: 23..<24) + public var sai2lpen: SAI2LPEN + + /// SDMMC1 clock enable during Sleep mode + @ReadWrite(bits: 11..<12) + public var sdmmc1lpen: SDMMC1LPEN + } + + /// Backup domain control register + @Register(bitWidth: 32) + public struct BDCR { + /// Backup domain software reset + @ReadWrite(bits: 16..<17, as: BDRSTValues.self) + public var bdrst: BDRST + + /// RTC clock enable + @ReadWrite(bits: 15..<16, as: RTCENValues.self) + public var rtcen: RTCEN + + /// External low-speed oscillator bypass + @ReadWrite(bits: 2..<3, as: LSEBYPValues.self) + public var lsebyp: LSEBYP + + /// External low-speed oscillator ready + @ReadOnly(bits: 1..<2) + public var lserdy: LSERDY + + /// External low-speed oscillator enable + @ReadWrite(bits: 0..<1, as: LSEONValues.self) + public var lseon: LSEON + + /// LSE oscillator drive capability + @ReadWrite(bits: 3..<5, as: LSEDRVValues.self) + public var lsedrv: LSEDRV + + /// RTC clock source selection + @Reserved(bits: 8..<10, as: RTCSELValues.self) + public var rtcsel: RTCSEL + } + + /// clock control & status register + @Register(bitWidth: 32) + public struct CSR { + /// Low-power reset flag + @ReadWrite(bits: 31..<32) + public var lpwrrstf: LPWRRSTF + + /// Window watchdog reset flag + @ReadWrite(bits: 30..<31) + public var wwdgrstf: WWDGRSTF + + /// Independent watchdog reset flag + @ReadWrite(bits: 29..<30) + public var wdgrstf: WDGRSTF + + /// Software reset flag + @ReadWrite(bits: 28..<29) + public var sftrstf: SFTRSTF + + /// POR/PDR reset flag + @ReadWrite(bits: 27..<28) + public var porrstf: PORRSTF + + /// PIN reset flag + @ReadWrite(bits: 26..<27) + public var padrstf: PADRSTF + + /// BOR reset flag + @ReadWrite(bits: 25..<26) + public var borrstf: BORRSTF + + /// Remove reset flag + @ReadWrite(bits: 24..<25) + public var rmvf: RMVF + + /// Internal low-speed oscillator ready + @ReadOnly(bits: 1..<2) + public var lsirdy: LSIRDY + + /// Internal low-speed oscillator enable + @ReadWrite(bits: 0..<1, as: LSIONValues.self) + public var lsion: LSION + } + + /// spread spectrum clock generation register + @Register(bitWidth: 32) + public struct SSCGR { + /// Spread spectrum modulation enable + @ReadWrite(bits: 31..<32, as: SSCGENValues.self) + public var sscgen: SSCGEN + + /// Spread Select + @ReadWrite(bits: 30..<31, as: SPREADSELValues.self) + public var spreadsel: SPREADSEL + + /// Incrementation step + @ReadWrite(bits: 13..<28) + public var incstep: INCSTEP + + /// Modulation period + @ReadWrite(bits: 0..<13) + public var modper: MODPER + } + + /// PLLI2S configuration register + @Register(bitWidth: 32) + public struct PLLI2SCFGR { + /// PLLI2S division factor for I2S clocks + @ReadWrite(bits: 28..<31) + public var plli2sr: PLLI2SR + + /// PLLI2S division factor for SAI1 clock + @ReadWrite(bits: 24..<28) + public var plli2sq: PLLI2SQ + + /// PLLI2S multiplication factor for VCO + @ReadWrite(bits: 6..<15) + public var plli2sn: PLLI2SN + + /// PLLI2S division factor for SPDIFRX clock + @ReadWrite(bits: 16..<18, as: PLLI2SPValues.self) + public var plli2sp: PLLI2SP + } + + /// PLL configuration register + @Register(bitWidth: 32) + public struct PLLSAICFGR { + /// PLLSAI division factor for VCO + @ReadWrite(bits: 6..<15) + public var pllsain: PLLSAIN + + /// PLLSAI division factor for 48MHz clock + @ReadWrite(bits: 16..<18, as: PLLSAIPValues.self) + public var pllsaip: PLLSAIP + + /// PLLSAI division factor for SAI clock + @ReadWrite(bits: 24..<28) + public var pllsaiq: PLLSAIQ + + /// PLLSAI division factor for LCD clock + @ReadWrite(bits: 28..<31) + public var pllsair: PLLSAIR + } + + /// dedicated clocks configuration register + @Register(bitWidth: 32) + public struct DCKCFGR1 { + /// PLLI2S division factor for SAI1 clock + @ReadWrite(bits: 0..<5, as: PLLI2SDIVQValues.self) + public var plli2sdivq: PLLI2SDIVQ + + /// PLLSAI division factor for SAI1 clock + @ReadWrite(bits: 8..<13, as: PLLSAIDIVQValues.self) + public var pllsaidivq: PLLSAIDIVQ + + /// division factor for LCD_CLK + @ReadWrite(bits: 16..<18, as: PLLSAIDIVRValues.self) + public var pllsaidivr: PLLSAIDIVR + + /// SAI1 clock source selection + @ReadWrite(bits: 20..<22, as: SAI1SELValues.self) + public var sai1sel: SAI1SEL + + /// SAI2 clock source selection + @ReadWrite(bits: 22..<24, as: SAI2SELValues.self) + public var sai2sel: SAI2SEL + + /// Timers clocks prescalers selection + @ReadWrite(bits: 24..<25, as: TIMPREValues.self) + public var timpre: TIMPRE + } + + /// dedicated clocks configuration register + @Register(bitWidth: 32) + public struct DCKCFGR2 { + /// USART 1 clock source selection + @ReadWrite(bits: 0..<2, as: USART1SELValues.self) + public var usart1sel: USART1SEL + + /// USART 2 clock source selection + @ReadWrite(bits: 2..<4, as: USART2SELValues.self) + public var usart2sel: USART2SEL + + /// USART 3 clock source selection + @ReadWrite(bits: 4..<6) + public var usart3sel: USART3SEL + + /// UART 4 clock source selection + @ReadWrite(bits: 6..<8) + public var uart4sel: UART4SEL + + /// UART 5 clock source selection + @ReadWrite(bits: 8..<10) + public var uart5sel: UART5SEL + + /// USART 6 clock source selection + @ReadWrite(bits: 10..<12) + public var usart6sel: USART6SEL + + /// UART 7 clock source selection + @ReadWrite(bits: 12..<14) + public var uart7sel: UART7SEL + + /// UART 8 clock source selection + @ReadWrite(bits: 14..<16) + public var uart8sel: UART8SEL + + /// I2C1 clock source selection + @ReadWrite(bits: 16..<18, as: I2C1SELValues.self) + public var i2c1sel: I2C1SEL + + /// I2C2 clock source selection + @ReadWrite(bits: 18..<20) + public var i2c2sel: I2C2SEL + + /// I2C3 clock source selection + @ReadWrite(bits: 20..<22) + public var i2c3sel: I2C3SEL + + /// I2C4 clock source selection + @ReadWrite(bits: 22..<24) + public var i2c4sel: I2C4SEL + + /// Low power timer 1 clock source selection + @ReadWrite(bits: 24..<26, as: LPTIM1SELValues.self) + public var lptim1sel: LPTIM1SEL + + /// HDMI-CEC clock source selection + @ReadWrite(bits: 26..<27, as: CECSELValues.self) + public var cecsel: CECSEL + + /// 48MHz clock source selection + @ReadWrite(bits: 27..<28, as: CK48MSELValues.self) + public var ck48msel: CK48MSEL + + /// SDMMC clock source selection + @ReadWrite(bits: 28..<29, as: SDMMC1SELValues.self) + public var sdmmc1sel: SDMMC1SEL + } +} + +extension RCC.CR { + public struct CSSONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Clock security system disabled (clock detector OFF) + public static let Off = Self(rawValue: 0x0) + + /// Clock security system enable (clock detector ON if the HSE is ready, OFF if not) + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + public struct HSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// HSE crystal oscillator not bypassed + public static let NotBypassed = Self(rawValue: 0x0) + + /// HSE crystal oscillator bypassed with external clock + public static let Bypassed = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CR { + public struct HSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Clock Off + public static let Off = Self(rawValue: 0x0) + + /// Clock On + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + public struct PLLSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// HSI clock selected as PLL and PLLI2S clock entry + public static let HSI = Self(rawValue: 0x0) + + /// HSE oscillator clock selected as PLL and PLLI2S clock entry + public static let HSE = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLCFGR { + public struct PLLPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLLP=2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLLP=4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLLP=6 + public static let Div6 = Self(rawValue: 0x2) + + /// PLLP=8 + public static let Div8 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct MCO2Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// System clock (SYSCLK) selected + public static let SYSCLK = Self(rawValue: 0x0) + + /// PLLI2S clock selected + public static let PLLI2S = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + public static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + public static let PLL = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct MCO1PREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// No division + public static let Div1 = Self(rawValue: 0x0) + + /// Division by 2 + public static let Div2 = Self(rawValue: 0x4) + + /// Division by 3 + public static let Div3 = Self(rawValue: 0x5) + + /// Division by 4 + public static let Div4 = Self(rawValue: 0x6) + + /// Division by 5 + public static let Div5 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct I2SSRCValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// PLLI2S clock used as I2S clock source + public static let PLLI2S = Self(rawValue: 0x0) + + /// External clock mapped on the I2S_CKIN pin used as I2S clock source + public static let CKIN = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct MCO1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// HSI clock selected + public static let HSI = Self(rawValue: 0x0) + + /// LSE oscillator selected + public static let LSE = Self(rawValue: 0x1) + + /// HSE oscillator clock selected + public static let HSE = Self(rawValue: 0x2) + + /// PLL clock selected + public static let PLL = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct PPRE1Values: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 3 + + /// HCLK not divided + public static let Div1 = Self(rawValue: 0x0) + + /// HCLK divided by 2 + public static let Div2 = Self(rawValue: 0x4) + + /// HCLK divided by 4 + public static let Div4 = Self(rawValue: 0x5) + + /// HCLK divided by 8 + public static let Div8 = Self(rawValue: 0x6) + + /// HCLK divided by 16 + public static let Div16 = Self(rawValue: 0x7) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct HPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 4 + + /// SYSCLK not divided + public static let Div1 = Self(rawValue: 0x0) + + /// SYSCLK divided by 2 + public static let Div2 = Self(rawValue: 0x8) + + /// SYSCLK divided by 4 + public static let Div4 = Self(rawValue: 0x9) + + /// SYSCLK divided by 8 + public static let Div8 = Self(rawValue: 0xa) + + /// SYSCLK divided by 16 + public static let Div16 = Self(rawValue: 0xb) + + /// SYSCLK divided by 64 + public static let Div64 = Self(rawValue: 0xc) + + /// SYSCLK divided by 128 + public static let Div128 = Self(rawValue: 0xd) + + /// SYSCLK divided by 256 + public static let Div256 = Self(rawValue: 0xe) + + /// SYSCLK divided by 512 + public static let Div512 = Self(rawValue: 0xf) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CFGR { + public struct SWValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// HSI selected as system clock + public static let HSI = Self(rawValue: 0x0) + + /// HSE selected as system clock + public static let HSE = Self(rawValue: 0x1) + + /// PLL selected as system clock + public static let PLL = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CIR { + public struct LSIRDYIEValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Interrupt disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Interrupt enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1RSTR { + public struct GPIOARSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2RSTR { + public struct DCMIRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3RSTR { + public struct FMCRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1RSTR { + public struct TIM2RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2RSTR { + public struct TIM1RSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset the selected module + public static let Reset = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1ENR { + public struct GPIOAENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2ENR { + public struct DCMIENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3ENR { + public struct FMCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1ENR { + public struct TIM2ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2ENR { + public struct TIM1ENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// The selected clock is disabled + public static let Disabled = Self(rawValue: 0x0) + + /// The selected clock is enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB1LPENR { + public struct GPIOALPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB2LPENR { + public struct DCMILPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.AHB3LPENR { + public struct FMCLPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB1LPENR { + public struct TIM2LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.APB2LPENR { + public struct TIM1LPENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Selected module is disabled during Sleep mode + public static let DisabledInSleep = Self(rawValue: 0x0) + + /// Selected module is enabled during Sleep mode + public static let EnabledInSleep = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct BDRSTValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Reset not activated + public static let Disabled = Self(rawValue: 0x0) + + /// Reset the entire RTC domain + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct RTCENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// RTC clock disabled + public static let Disabled = Self(rawValue: 0x0) + + /// RTC clock enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct LSEBYPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSE crystal oscillator not bypassed + public static let NotBypassed = Self(rawValue: 0x0) + + /// LSE crystal oscillator bypassed with external clock + public static let Bypassed = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct LSEONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSE oscillator Off + public static let Off = Self(rawValue: 0x0) + + /// LSE oscillator On + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct LSEDRVValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// Low drive capacity + public static let Low = Self(rawValue: 0x0) + + /// Medium-high drive capacity + public static let MediumHigh = Self(rawValue: 0x1) + + /// Medium-low drive capacity + public static let MediumLow = Self(rawValue: 0x2) + + /// High drive capacity + public static let High = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.BDCR { + public struct RTCSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// No clock + public static let NoClock = Self(rawValue: 0x0) + + /// LSE oscillator clock used as RTC clock + public static let LSE = Self(rawValue: 0x1) + + /// LSI oscillator clock used as RTC clock + public static let LSI = Self(rawValue: 0x2) + + /// HSE oscillator clock divided by a prescaler used as RTC clock + public static let HSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.CSR { + public struct LSIONValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSI oscillator Off + public static let Off = Self(rawValue: 0x0) + + /// LSI oscillator On + public static let On = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + public struct SSCGENValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Spread spectrum modulation disabled + public static let Disabled = Self(rawValue: 0x0) + + /// Spread spectrum modulation enabled + public static let Enabled = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.SSCGR { + public struct SPREADSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// Center spread + public static let Center = Self(rawValue: 0x0) + + /// Down spread + public static let Down = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLI2SCFGR { + public struct PLLI2SPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLL*P=2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + public static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + public static let Div8 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.PLLSAICFGR { + public struct PLLSAIPValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLL*P=2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLL*P=4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLL*P=6 + public static let Div6 = Self(rawValue: 0x2) + + /// PLL*P=8 + public static let Div8 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct PLLI2SDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 + + /// PLLI2SDIVQ = /1 + public static let Div1 = Self(rawValue: 0x0) + + /// PLLI2SDIVQ = /2 + public static let Div2 = Self(rawValue: 0x1) + + /// PLLI2SDIVQ = /3 + public static let Div3 = Self(rawValue: 0x2) + + /// PLLI2SDIVQ = /4 + public static let Div4 = Self(rawValue: 0x3) + + /// PLLI2SDIVQ = /5 + public static let Div5 = Self(rawValue: 0x4) + + /// PLLI2SDIVQ = /6 + public static let Div6 = Self(rawValue: 0x5) + + /// PLLI2SDIVQ = /7 + public static let Div7 = Self(rawValue: 0x6) + + /// PLLI2SDIVQ = /8 + public static let Div8 = Self(rawValue: 0x7) + + /// PLLI2SDIVQ = /9 + public static let Div9 = Self(rawValue: 0x8) + + /// PLLI2SDIVQ = /10 + public static let Div10 = Self(rawValue: 0x9) + + /// PLLI2SDIVQ = /11 + public static let Div11 = Self(rawValue: 0xa) + + /// PLLI2SDIVQ = /12 + public static let Div12 = Self(rawValue: 0xb) + + /// PLLI2SDIVQ = /13 + public static let Div13 = Self(rawValue: 0xc) + + /// PLLI2SDIVQ = /14 + public static let Div14 = Self(rawValue: 0xd) + + /// PLLI2SDIVQ = /15 + public static let Div15 = Self(rawValue: 0xe) + + /// PLLI2SDIVQ = /16 + public static let Div16 = Self(rawValue: 0xf) + + /// PLLI2SDIVQ = /17 + public static let Div17 = Self(rawValue: 0x10) + + /// PLLI2SDIVQ = /18 + public static let Div18 = Self(rawValue: 0x11) + + /// PLLI2SDIVQ = /19 + public static let Div19 = Self(rawValue: 0x12) + + /// PLLI2SDIVQ = /20 + public static let Div20 = Self(rawValue: 0x13) + + /// PLLI2SDIVQ = /21 + public static let Div21 = Self(rawValue: 0x14) + + /// PLLI2SDIVQ = /22 + public static let Div22 = Self(rawValue: 0x15) + + /// PLLI2SDIVQ = /23 + public static let Div23 = Self(rawValue: 0x16) + + /// PLLI2SDIVQ = /24 + public static let Div24 = Self(rawValue: 0x17) + + /// PLLI2SDIVQ = /25 + public static let Div25 = Self(rawValue: 0x18) + + /// PLLI2SDIVQ = /26 + public static let Div26 = Self(rawValue: 0x19) + + /// PLLI2SDIVQ = /27 + public static let Div27 = Self(rawValue: 0x1a) + + /// PLLI2SDIVQ = /28 + public static let Div28 = Self(rawValue: 0x1b) + + /// PLLI2SDIVQ = /29 + public static let Div29 = Self(rawValue: 0x1c) + + /// PLLI2SDIVQ = /30 + public static let Div30 = Self(rawValue: 0x1d) + + /// PLLI2SDIVQ = /31 + public static let Div31 = Self(rawValue: 0x1e) + + /// PLLI2SDIVQ = /32 + public static let Div32 = Self(rawValue: 0x1f) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct PLLSAIDIVQValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 5 + + /// PLLSAIDIVQ = /1 + public static let Div1 = Self(rawValue: 0x0) + + /// PLLSAIDIVQ = /2 + public static let Div2 = Self(rawValue: 0x1) + + /// PLLSAIDIVQ = /3 + public static let Div3 = Self(rawValue: 0x2) + + /// PLLSAIDIVQ = /4 + public static let Div4 = Self(rawValue: 0x3) + + /// PLLSAIDIVQ = /5 + public static let Div5 = Self(rawValue: 0x4) + + /// PLLSAIDIVQ = /6 + public static let Div6 = Self(rawValue: 0x5) + + /// PLLSAIDIVQ = /7 + public static let Div7 = Self(rawValue: 0x6) + + /// PLLSAIDIVQ = /8 + public static let Div8 = Self(rawValue: 0x7) + + /// PLLSAIDIVQ = /9 + public static let Div9 = Self(rawValue: 0x8) + + /// PLLSAIDIVQ = /10 + public static let Div10 = Self(rawValue: 0x9) + + /// PLLSAIDIVQ = /11 + public static let Div11 = Self(rawValue: 0xa) + + /// PLLSAIDIVQ = /12 + public static let Div12 = Self(rawValue: 0xb) + + /// PLLSAIDIVQ = /13 + public static let Div13 = Self(rawValue: 0xc) + + /// PLLSAIDIVQ = /14 + public static let Div14 = Self(rawValue: 0xd) + + /// PLLSAIDIVQ = /15 + public static let Div15 = Self(rawValue: 0xe) + + /// PLLSAIDIVQ = /16 + public static let Div16 = Self(rawValue: 0xf) + + /// PLLSAIDIVQ = /17 + public static let Div17 = Self(rawValue: 0x10) + + /// PLLSAIDIVQ = /18 + public static let Div18 = Self(rawValue: 0x11) + + /// PLLSAIDIVQ = /19 + public static let Div19 = Self(rawValue: 0x12) + + /// PLLSAIDIVQ = /20 + public static let Div20 = Self(rawValue: 0x13) + + /// PLLSAIDIVQ = /21 + public static let Div21 = Self(rawValue: 0x14) + + /// PLLSAIDIVQ = /22 + public static let Div22 = Self(rawValue: 0x15) + + /// PLLSAIDIVQ = /23 + public static let Div23 = Self(rawValue: 0x16) + + /// PLLSAIDIVQ = /24 + public static let Div24 = Self(rawValue: 0x17) + + /// PLLSAIDIVQ = /25 + public static let Div25 = Self(rawValue: 0x18) + + /// PLLSAIDIVQ = /26 + public static let Div26 = Self(rawValue: 0x19) + + /// PLLSAIDIVQ = /27 + public static let Div27 = Self(rawValue: 0x1a) + + /// PLLSAIDIVQ = /28 + public static let Div28 = Self(rawValue: 0x1b) + + /// PLLSAIDIVQ = /29 + public static let Div29 = Self(rawValue: 0x1c) + + /// PLLSAIDIVQ = /30 + public static let Div30 = Self(rawValue: 0x1d) + + /// PLLSAIDIVQ = /31 + public static let Div31 = Self(rawValue: 0x1e) + + /// PLLSAIDIVQ = /32 + public static let Div32 = Self(rawValue: 0x1f) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct PLLSAIDIVRValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// PLLSAIDIVR = /2 + public static let Div2 = Self(rawValue: 0x0) + + /// PLLSAIDIVR = /4 + public static let Div4 = Self(rawValue: 0x1) + + /// PLLSAIDIVR = /8 + public static let Div8 = Self(rawValue: 0x2) + + /// PLLSAIDIVR = /16 + public static let Div16 = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct SAI1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SAI1 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + public static let PLLSAI = Self(rawValue: 0x0) + + /// SAI1 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + public static let PLLI2S = Self(rawValue: 0x1) + + /// SAI1 clock frequency = Alternate function input frequency + public static let AFIF = Self(rawValue: 0x2) + + /// SAI1 clock frequency = HSI or HSE + public static let HSI_HSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct SAI2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// SAI2 clock frequency = f(PLLSAI_Q) / PLLSAIDIVQ + public static let PLLSAI = Self(rawValue: 0x0) + + /// SAI2 clock frequency = f(PLLI2S_Q) / PLLI2SDIVQ + public static let PLLI2S = Self(rawValue: 0x1) + + /// SAI2 clock frequency = Alternate function input frequency + public static let AFIF = Self(rawValue: 0x2) + + /// SAI2 clock frequency = HSI or HSE + public static let HSI_HSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR1 { + public struct TIMPREValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// If the APB prescaler is configured 1, TIMxCLK = PCLKx. Otherwise, TIMxCLK = 2xPCLKx + public static let Mul1Or2 = Self(rawValue: 0x0) + + /// If the APB prescaler is configured 1, 2 or 4, TIMxCLK = HCLK. Otherwise, TIMxCLK = 4xPCLKx + public static let Mul1Or4 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct USART1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB2 clock (PCLK2) is selected as USART clock + public static let APB2 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + public static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + public static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + public static let LSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct USART2SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB1 clock (PCLK1) is selected as USART clock + public static let APB1 = Self(rawValue: 0x0) + + /// System clock is selected as USART clock + public static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock is selected as USART clock + public static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as USART clock + public static let LSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct I2C1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB clock selected as I2C clock + public static let APB = Self(rawValue: 0x0) + + /// System clock selected as I2C clock + public static let SYSCLK = Self(rawValue: 0x1) + + /// HSI clock selected as I2C clock + public static let HSI = Self(rawValue: 0x2) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct LPTIM1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 2 + + /// APB1 clock (PCLK1) selected as LPTILM1 clock + public static let APB1 = Self(rawValue: 0x0) + + /// LSI clock is selected as LPTILM1 clock + public static let LSI = Self(rawValue: 0x1) + + /// HSI clock is selected as LPTILM1 clock + public static let HSI = Self(rawValue: 0x2) + + /// LSE clock is selected as LPTILM1 clock + public static let LSE = Self(rawValue: 0x3) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct CECSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// LSE clock is selected as HDMI-CEC clock + public static let LSE = Self(rawValue: 0x0) + + /// HSI divided by 488 clock is selected as HDMI-CEC clock + public static let HSI_Div488 = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct CK48MSELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 48MHz clock from PLL is selected + public static let PLL = Self(rawValue: 0x0) + + /// 48MHz clock from PLLSAI is selected + public static let PLLSAI = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} + +extension RCC.DCKCFGR2 { + public struct SDMMC1SELValues: BitFieldProjectable, RawRepresentable { + public static let bitWidth = 1 + + /// 48 MHz clock is selected as SD clock + public static let CK48M = Self(rawValue: 0x0) + + /// System clock is selected as SD clock + public static let SYSCLK = Self(rawValue: 0x1) + + public var rawValue: UInt8 + + @inlinable @inline(__always) + public init(rawValue: Self.RawValue) { + self.rawValue = rawValue + } + } +} diff --git a/stm32-blink/Sources/STM32F7X6/stm32f7x6.patched.svd b/stm32-blink/Sources/STM32F7X6/stm32f7x6.patched.svd new file mode 120000 index 00000000..a6442b50 --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/stm32f7x6.patched.svd @@ -0,0 +1 @@ +../../../Tools/SVDs/stm32f7x6.patched.svd \ No newline at end of file diff --git a/stm32-blink/Sources/STM32F7X6/svd2swift.json b/stm32-blink/Sources/STM32F7X6/svd2swift.json new file mode 100644 index 00000000..19934776 --- /dev/null +++ b/stm32-blink/Sources/STM32F7X6/svd2swift.json @@ -0,0 +1,8 @@ +{ + "peripherals": [ + "GPIOA", + "GPIOI", + "RCC" + ], + "access-level": "public" +} diff --git a/stm32-blink/Sources/Support/Support.c b/stm32-blink/Sources/Support/Support.c new file mode 100644 index 00000000..fc3c1a13 --- /dev/null +++ b/stm32-blink/Sources/Support/Support.c @@ -0,0 +1,51 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2024 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + +#if defined(__arm__) + +#include +#include + +void *memset(void *b, int c, size_t len) { + for (int i = 0; i < len; i++) { + ((char *)b)[i] = c; + } + return b; +} + +void *memcpy(void *restrict dst, const void *restrict src, size_t n) { + for (int i = 0; i < n; i++) { + ((char *)dst)[i] = ((char *)src)[i]; + } + return dst; +} + +extern void reset(void); + +void interrupt(void) { + while (1) {} +} + +__attribute((used)) __attribute((section("__VECTORS,__text"))) +void *vector_table[114] = { + (void *)0x2000fffc, // initial SP + (void *)((uintptr_t)reset - (0x20010000 - 0x08000000)), // Reset + + (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // NMI + (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // HardFault + (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // MemManage + (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // BusFault + (void *)((uintptr_t)interrupt - (0x20010000 - 0x08000000)), // UsageFault + + 0 // NULL for all the other handlers +}; + +#endif diff --git a/stm32-blink/BridgingHeader.h b/stm32-blink/Sources/Support/include/Support.h similarity index 77% rename from stm32-blink/BridgingHeader.h rename to stm32-blink/Sources/Support/include/Support.h index 6b807332..dbc23864 100644 --- a/stm32-blink/BridgingHeader.h +++ b/stm32-blink/Sources/Support/include/Support.h @@ -2,7 +2,7 @@ // // This source file is part of the Swift open source project // -// Copyright (c) 2023 Apple Inc. and the Swift project authors. +// Copyright (c) 2024 Apple Inc. and the Swift project authors. // Licensed under Apache License v2.0 with Runtime Library Exception // // See https://swift.org/LICENSE.txt for license information @@ -11,6 +11,6 @@ #pragma once -static inline __attribute((always_inline)) void nop() { +static inline void nop(void) { asm volatile("nop"); } diff --git a/stm32-blink/Sources/Support/startup.S b/stm32-blink/Sources/Support/startup.S new file mode 100644 index 00000000..6e8c7c27 --- /dev/null +++ b/stm32-blink/Sources/Support/startup.S @@ -0,0 +1,45 @@ +//===----------------------------------------------------------------------===// +// +// This source file is part of the Swift open source project +// +// Copyright (c) 2023 Apple Inc. and the Swift project authors. +// Licensed under Apache License v2.0 with Runtime Library Exception +// +// See https://swift.org/LICENSE.txt for license information +// +//===----------------------------------------------------------------------===// + + .extern _memcpy + .extern _main + + .text + .thumb + .section __TEXT,__text,regular,pure_instructions + .syntax unified + +// reset handler, main entry point + .balign 4 + .global _reset + .thumb_func +_reset: + ldr r0, =0x20010000 // dst + ldr r1, =0x08000000 // src + ldr r2, =segment$start$__VECTORS + ldr r3, =segment$end$__DATA + subs r2, r3, r2 // size = segment$end$__DATA - segment$start$__TEXT + + // memcpy (r0: dst = 0x20010000, r1: src = 0x08000000, r2: size = ...) + // Relocate ourselves: copy the entire image (VECTORS, TEXT, DATA segments) + // from flash memory (non-writable) to RAM (writable), so that globals can be + // written to. + bl _memcpy + + // Cannot jump to main normally, because that would call main using a relative + // offset, which would result in a call to the pre-relocation address. + // Loading address of main into a register will give us the post-relocation + // address. + ldr r0, =_main + blx r0 + + // Loop forever if main returns. + b . diff --git a/stm32-blink/Startup.c b/stm32-blink/Startup.c deleted file mode 100644 index 9237afb1..00000000 --- a/stm32-blink/Startup.c +++ /dev/null @@ -1,44 +0,0 @@ -//===----------------------------------------------------------------------===// -// -// This source file is part of the Swift open source project -// -// Copyright (c) 2023 Apple Inc. and the Swift project authors. -// Licensed under Apache License v2.0 with Runtime Library Exception -// -// See https://swift.org/LICENSE.txt for license information -// -//===----------------------------------------------------------------------===// - -#include -#include - -extern int main(int argc, char *argv[]); - -void reset(void) { - main(0, NULL); -} - -void interrupt(void) { - while (1) {} -} - -__attribute((used)) -#if defined(__ELF__) -__attribute((section(".vectors"))) -#elif defined(__MACH__) -__attribute((section("__VECTORS,__text"))) -#else -#error Unknown file format -#endif -void *vector_table[114] = { - (void *)0x20001ffc, // initial SP, assume we have 8 KB of SRAM - reset, // Reset - - interrupt, // NMI - interrupt, // HardFault - interrupt, // MemManage - interrupt, // BusFault - interrupt, // UsageFault - - 0 // NULL for all the other handlers -}; diff --git a/stm32-blink/build-elf.sh b/stm32-blink/build-elf.sh deleted file mode 100755 index afd9413e..00000000 --- a/stm32-blink/build-elf.sh +++ /dev/null @@ -1,52 +0,0 @@ -#!/bin/bash - -set -vex - -# Determine file paths -REPOROOT=$(realpath -- "$(dirname "${BASH_SOURCE[0]}")")/.. -TOOLSROOT="$REPOROOT/Tools" -SRCROOT="$REPOROOT/stm32-blink" -BUILDROOT="$SRCROOT/.build" - -# Clean the build directory -rm -r "$BUILDROOT" || true - -# Setup tools and build flags -TARGET=armv7em-none-none-eabi - -if [[ ! "$STM_BOARD" ]] ; then - echo "STM_BOARD must be set to STM32F746G_DISCOVERY or NUCLEO_F103RB" - exit 1 -fi - -SWIFT_EXEC=${SWIFT_EXEC:-$(which swiftc)} -SWIFT_FLAGS="-target $TARGET -Osize" -SWIFT_FLAGS+=" -import-bridging-header $SRCROOT/BridgingHeader.h -wmo -enable-experimental-feature Embedded" -SWIFT_FLAGS+=" -Xfrontend -function-sections -D${STM_BOARD}" - -CLANG_EXEC=${CLANG_EXEC:-$(which clang)} -CLANG_FLAGS="-target $TARGET -Oz" - -LD_EXEC=${LD_EXEC:-$CLANG_EXEC} -LD_FLAGS="-target $TARGET -fuse-ld=lld -nostdlib -static -Wl,-e,vector_table -Wl,--gc-sections -Wl,-T,$SRCROOT/elf-linkerscript.ld" - -# Create build directory -mkdir -p "$BUILDROOT" - -# Build Swift sources -# shellcheck disable=SC2086 # intentional splitting -"$SWIFT_EXEC" $SWIFT_FLAGS -c $SRCROOT/*.swift -o "$BUILDROOT/blink.o" - -# Build C sources -# shellcheck disable=SC2086 # intentional splitting -"$CLANG_EXEC" $CLANG_FLAGS -c "$SRCROOT/Startup.c" -o "$BUILDROOT/Startup.o" - -# Link objects into executable -# shellcheck disable=SC2086 # intentional splitting -"$LD_EXEC" $LD_FLAGS "$BUILDROOT/blink.o" "$BUILDROOT/Startup.o" -o "$BUILDROOT/blink.elf" - -# Convert to Intel HEX for flashing -"$TOOLSROOT"/elf2hex.py "$BUILDROOT/blink.elf" "$BUILDROOT/blink.hex" - -# Echo final binary path -ls -al "$BUILDROOT/blink.hex" diff --git a/stm32-blink/build-macho.sh b/stm32-blink/build-macho.sh deleted file mode 100755 index 7e9fa3d4..00000000 --- a/stm32-blink/build-macho.sh +++ /dev/null @@ -1,56 +0,0 @@ -#!/bin/bash - -set -vex - -# Determine file paths -REPOROOT=$(git rev-parse --show-toplevel) -TOOLSROOT="$REPOROOT/Tools" -SRCROOT="$REPOROOT/stm32-blink" -BUILDROOT="$SRCROOT/.build" - -# Clean the build directory -rm -r "$BUILDROOT" || true - -# Setup tools and build flags -TARGET=armv7em-apple-none-macho - -if [[ ! "$STM_BOARD" ]] ; then - echo "STM_BOARD must be set to STM32F746G_DISCOVERY or NUCLEO_F103RB" - exit 1 -fi - -SWIFT_EXEC=${SWIFT_EXEC:-$(xcrun -f swiftc)} -SWIFT_FLAGS="-target $TARGET -Osize" -SWIFT_FLAGS+=" -import-bridging-header $SRCROOT/BridgingHeader.h -wmo -enable-experimental-feature Embedded" -SWIFT_FLAGS+=" -Xcc -ffreestanding" -SWIFT_FLAGS+=" -D${STM_BOARD}" - -CLANG_EXEC=${CLANG_EXEC:-$(xcrun -f clang)} -CLANG_FLAGS="-target $TARGET -Oz" - -LD_EXEC=${LD_EXEC:-$CLANG_EXEC} -LD_FLAGS="-target $TARGET -nostdlib -static -Wl,-e,_reset -dead_strip -Wl,-no_zero_fill_sections -Wl,-segalign,4 -Wl,-segaddr,__VECTORS,0x08000000 -Wl,-seg1addr,0x08000200 -Wl,-pagezero_size,0" - -PYTHON_EXEC=${PYTHON_EXEC:-$(xcrun -f python3)} -MACHO2BIN="$TOOLSROOT/macho2bin.py" - -# Create build directory -mkdir -p "$BUILDROOT" - -# Build Swift sources -# shellcheck disable=SC2086 # intentional splitting -"$SWIFT_EXEC" $SWIFT_FLAGS -c "$SRCROOT/"*.swift -o "$BUILDROOT/blink.o" - -# Build C sources -# shellcheck disable=SC2086 # intentional splitting -"$CLANG_EXEC" $CLANG_FLAGS -c "$SRCROOT/Startup.c" -o "$BUILDROOT/Startup.o" - -# Link objects into executable -# shellcheck disable=SC2086 # intentional splitting -"$LD_EXEC" $LD_FLAGS "$BUILDROOT/blink.o" "$BUILDROOT/Startup.o" -o "$BUILDROOT/blink" - -# Extract sections from executable into flashable binary -"$PYTHON_EXEC" "$MACHO2BIN" "$BUILDROOT/blink" "$BUILDROOT/blink.bin" --base-address 0x08000000 --segments '__TEXT,__DATA,__VECTORS' - -# Echo final binary path -ls -al "$BUILDROOT/blink.bin" diff --git a/stm32-blink/elf-linkerscript.ld b/stm32-blink/elf-linkerscript.ld deleted file mode 100644 index 98d5f00a..00000000 --- a/stm32-blink/elf-linkerscript.ld +++ /dev/null @@ -1,13 +0,0 @@ -MEMORY -{ - flash : ORIGIN = 0x08000000, LENGTH = 32K - sram : ORIGIN = 0x20000000, LENGTH = 8K -} - -SECTIONS -{ - .text : { *(.vectors*) ; *(.text*) } > flash - .bss : { *(.bss*) } > sram - .data : { *(.data*) } > sram - /DISCARD/ : { *(.swift_modhash*) } -} From 885ffa88eedd0a8433032b0029271893bdd039f1 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Sat, 21 Jun 2025 15:47:21 -0700 Subject: [PATCH 02/20] ignore register format --- .swiftformatignore | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/.swiftformatignore b/.swiftformatignore index cec22c76..2617ab2e 100644 --- a/.swiftformatignore +++ b/.swiftformatignore @@ -1,6 +1,7 @@ ./harmony/* -./stm32-lvgl/* +./stm32-blink/Sources/STM32F7X6/* ./stm32-lcd-logo/Sources/STM32F7X6/* +./stm32-lvgl/* ./stm32-lvgl/Sources/Registers/* ./stm32-neopixel/Sources/STM32F7X6/* ./stm32-uart-echo/Sources/STM32F7X6/* From 8e10a61e6fd3ea16ad83b1ac3f4aac65ff6d7fcf Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Sat, 21 Jun 2025 16:38:58 -0700 Subject: [PATCH 03/20] format --- stm32-blink/Sources/Application/Application.swift | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/stm32-blink/Sources/Application/Application.swift b/stm32-blink/Sources/Application/Application.swift index 34727b84..797ed2ff 100644 --- a/stm32-blink/Sources/Application/Application.swift +++ b/stm32-blink/Sources/Application/Application.swift @@ -9,8 +9,8 @@ // //===----------------------------------------------------------------------===// -import Support import STM32F7X6 +import Support // I1 pin aka "Arduino D13" pin on STM32F746 Discovery Board // https://www.st.com/resource/en/schematic_pack/mb1191-f746ngh6-c01_schematic.pdf From 25c3e6a30c2322559ae589fa2c0391e9d564e7a5 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Sat, 21 Jun 2025 16:53:51 -0700 Subject: [PATCH 04/20] macOS-runner --- .github/workflows/build-stm32-macho.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index 4f93be1a..929642f5 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -10,7 +10,7 @@ on: jobs: build: name: Build - runs-on: [self-hosted, macos] + runs-on: [self-hosted, macos, sequoia, ARM64] strategy: fail-fast: false From 314f46b16467784e6da8dce26ab6eb6deeb3ecb7 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Sat, 21 Jun 2025 18:47:26 -0700 Subject: [PATCH 05/20] udpate install swift workflow --- .github/actions/install-swift/action.yml | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index 6ca607fa..3852da52 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -4,13 +4,6 @@ description: Installs the Swift specified by a .swift-version file runs: using: "composite" steps: - # - name: "Cache: Swift" - # id: cache-swift - # uses: actions/cache@v4 - # with: - # path: "$HOME/.local/share/swiftly" - # key: swift-${{ hashFiles('.swift-version') }} - - name: Setup Environment shell: bash run: | @@ -22,6 +15,10 @@ runs: echo "SWIFTLY_BIN_DIR=$SWIFTLY_BIN_DIR" >> $GITHUB_ENV echo "SWIFTLY_BIN_DIR=$SWIFTLY_BIN_DIR" >> $HOME/.bashrc + export SWIFTLY_TOOLCHAINS_DIR="$HOME/.local/share/swiftly/toolchains" + echo "SWIFTLY_TOOLCHAINS_DIR=$SWIFTLY_TOOLCHAINS_DIR" >> $GITHUB_ENV + echo "SWIFTLY_TOOLCHAINS_DIR=$SWIFTLY_TOOLCHAINS_DIR" >> $HOME/.bashrc + echo "PATH=$SWIFTLY_BIN_DIR:$PATH" >> $GITHUB_ENV echo "PATH=\$SWIFTLY_BIN_DIR:\$PATH" >> $HOME/.bashrc @@ -30,7 +27,7 @@ runs: id: cache-swift with: path: "~/.local/share/swiftly" - key: swift-${{ hashFiles('**/.swift-version') }} + key: swift-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} - name: Install `apt` Dependencies if: steps.cache-swift.outputs.cache-hit != 'true' @@ -46,9 +43,11 @@ runs: if: steps.cache-swift.outputs.cache-hit != 'true' shell: bash run: | + SWIFTLY_VERSION=1.0.1 UNAME=$(uname -m) - curl -O "https://download.swift.org/swiftly/linux/swiftly-$UNAME.tar.gz" - tar zxf "swiftly-$UNAME.tar.gz" + SWIFTLY_TGZ=swiftly-$SWIFTLY_VERSION-$UNAME.tar.gz + curl -O "https://download.swift.org/swiftly/linux/$SWIFTLY_TGZ" + tar zxf "$SWIFTLY_TGZ" ./swiftly init \ --skip-install \ --assume-yes \ @@ -65,7 +64,7 @@ runs: uses: actions/cache/save@v4 with: path: "~/.local/share/swiftly" - key: swift-${{ hashFiles('**/.swift-version') }} + key: swift-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} - name: Print Swift Version shell: bash From 9f7ca4f2cd237ef81f55699aa41d2dfe15effae1 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:07:31 -0700 Subject: [PATCH 06/20] update workflow --- .github/workflows/build-stm32-macho.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index 929642f5..c0517e01 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -18,6 +18,9 @@ jobs: example: [stm32-blink, stm32-lcd-logo, stm32-neopixel, stm32-uart-echo] steps: + - name: Checkout repo + uses: actions/checkout@v4 + - name: Install Swift uses: ./.github/actions/install-swift From cd9ce4fe866d2620f856c250ecf890cd377e3784 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:11:29 -0700 Subject: [PATCH 07/20] update workflow --- .github/workflows/build-stm32-macho.yml | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index c0517e01..1d2f899d 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -24,6 +24,18 @@ jobs: - name: Install Swift uses: ./.github/actions/install-swift + - name: Validate Swiftly Paths + run: | + echo "Swiftly Path: $SWIFTLY_HOME_DIR" + echo "Swiftly Bin Path: $SWIFTLY_BIN_DIR" + echo "Swiftly Lib Path: $SWIFTLY_TOOLCHAINS_DIR" + + ls -asl $SWIFTLY_HOME_DIR + ls -asl $SWIFTLY_BIN_DIR + ls -asl $SWIFTLY_TOOLCHAINS_DIR + + ls -asl $HOME/.local/share/swiftly + - name: Build ${{ matrix.example }} working-directory: ${{ matrix.example }} run: make From 4d0ed09dfb09bd8540bc080a0c765b86d8112aa3 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:14:37 -0700 Subject: [PATCH 08/20] update workflow --- .github/workflows/build-stm32-macho.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index 1d2f899d..7f55fcb4 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -26,6 +26,9 @@ jobs: - name: Validate Swiftly Paths run: | + set -ex + set +x + echo "Swiftly Path: $SWIFTLY_HOME_DIR" echo "Swiftly Bin Path: $SWIFTLY_BIN_DIR" echo "Swiftly Lib Path: $SWIFTLY_TOOLCHAINS_DIR" From e5f219aad2319f112641bdd0e9f9de622056245c Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:17:19 -0700 Subject: [PATCH 09/20] update workflow --- .github/workflows/build-stm32-macho.yml | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index 7f55fcb4..bd017d96 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -26,8 +26,12 @@ jobs: - name: Validate Swiftly Paths run: | - set -ex - set +x + set -x + set +e + + env + + cat $HOME/.bashrc echo "Swiftly Path: $SWIFTLY_HOME_DIR" echo "Swiftly Bin Path: $SWIFTLY_BIN_DIR" From ce962748bd109450f53c2f9f60968b62b143851a Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:23:47 -0700 Subject: [PATCH 10/20] update workflow --- .github/workflows/build-stm32-macho.yml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index bd017d96..507cff51 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -21,6 +21,11 @@ jobs: - name: Checkout repo uses: actions/checkout@v4 + - name: Setup Environment + run: + swiftly --version + exit 1 + - name: Install Swift uses: ./.github/actions/install-swift From 121b210594f01410c917eebcca1720156e4724d1 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:37:47 -0700 Subject: [PATCH 11/20] update workflow --- .github/actions/install-swift/action.yml | 4 ++-- .github/workflows/build-stm32-macho.yml | 5 ----- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index 3852da52..ac6da83e 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -27,7 +27,7 @@ runs: id: cache-swift with: path: "~/.local/share/swiftly" - key: swift-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} + key: swift-${{ runner.os }}-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} - name: Install `apt` Dependencies if: steps.cache-swift.outputs.cache-hit != 'true' @@ -64,7 +64,7 @@ runs: uses: actions/cache/save@v4 with: path: "~/.local/share/swiftly" - key: swift-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} + key: swift-${{ runner.os }}-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} - name: Print Swift Version shell: bash diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index 507cff51..bd017d96 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -21,11 +21,6 @@ jobs: - name: Checkout repo uses: actions/checkout@v4 - - name: Setup Environment - run: - swiftly --version - exit 1 - - name: Install Swift uses: ./.github/actions/install-swift From 86701c14b5171ce531dffd998265634099ef4899 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 10:53:52 -0700 Subject: [PATCH 12/20] update workflow --- .github/actions/install-swift/action.yml | 19 +++++++++++++++++-- 1 file changed, 17 insertions(+), 2 deletions(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index ac6da83e..eeb37dce 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -30,7 +30,7 @@ runs: key: swift-${{ runner.os }}-${{ hashFiles('**/.swift-version', '.github/actions/install-swift/action.yml') }} - name: Install `apt` Dependencies - if: steps.cache-swift.outputs.cache-hit != 'true' + if: runner.os == 'Linux' && steps.cache-swift.outputs.cache-hit != 'true' shell: bash run: | SUDO=$(if [[ $EUID -ne 0 ]]; then echo sudo; fi) @@ -40,7 +40,7 @@ runs: DEBIAN_FRONTEND: noninteractive - name: Install Swiftly - if: steps.cache-swift.outputs.cache-hit != 'true' + if: runner.os == 'Linux' && steps.cache-swift.outputs.cache-hit != 'true' shell: bash run: | SWIFTLY_VERSION=1.0.1 @@ -54,6 +54,21 @@ runs: --quiet-shell-followup \ --no-modify-profile + - name: Install Swiftly + if: runner.os == 'macOS' && steps.cache-swift.outputs.cache-hit != 'true' + shell: bash + run: | + SWIFTLY_VERSION=1.0.1 + UNAME=$(uname -m) + SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg + curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" + installer -pkg $SWIFTLY_PKG -target CurrentUserHomeDirectory + ./swiftly init \ + --skip-install \ + --assume-yes \ + --quiet-shell-followup \ + --no-modify-profile + - name: Install Swift if: steps.cache-swift.outputs.cache-hit != 'true' shell: bash From e50352dcde6e032cccaef746e428bf845708e2ec Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 11:13:44 -0700 Subject: [PATCH 13/20] update workflow --- .github/actions/install-swift/action.yml | 1 - .github/workflows/build-esp.yml | 4 ++-- .github/workflows/build-nuttx.yml | 4 ++-- .github/workflows/build-rpi-baremetal.yml | 4 ++-- .github/workflows/build-rpi-pico-sdk.yml | 4 ++-- .github/workflows/build-stm32-elf.yml | 4 ++-- .github/workflows/build-stm32-macho.yml | 2 +- .github/workflows/build-zephyr.yml | 4 ++-- .github/workflows/lint.yml | 4 ++-- 9 files changed, 15 insertions(+), 16 deletions(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index eeb37dce..f488901b 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -59,7 +59,6 @@ runs: shell: bash run: | SWIFTLY_VERSION=1.0.1 - UNAME=$(uname -m) SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" installer -pkg $SWIFTLY_PKG -target CurrentUserHomeDirectory diff --git a/.github/workflows/build-esp.yml b/.github/workflows/build-esp.yml index 34325add..650f1c0e 100644 --- a/.github/workflows/build-esp.yml +++ b/.github/workflows/build-esp.yml @@ -3,8 +3,8 @@ name: ESP on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: diff --git a/.github/workflows/build-nuttx.yml b/.github/workflows/build-nuttx.yml index 554cd5f7..901a6450 100644 --- a/.github/workflows/build-nuttx.yml +++ b/.github/workflows/build-nuttx.yml @@ -3,8 +3,8 @@ name: NuttX on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: diff --git a/.github/workflows/build-rpi-baremetal.yml b/.github/workflows/build-rpi-baremetal.yml index eadc725d..33aedc00 100644 --- a/.github/workflows/build-rpi-baremetal.yml +++ b/.github/workflows/build-rpi-baremetal.yml @@ -3,8 +3,8 @@ name: Raspberry Pi Baremetal on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: diff --git a/.github/workflows/build-rpi-pico-sdk.yml b/.github/workflows/build-rpi-pico-sdk.yml index 258c65c3..e70f66ab 100644 --- a/.github/workflows/build-rpi-pico-sdk.yml +++ b/.github/workflows/build-rpi-pico-sdk.yml @@ -3,8 +3,8 @@ name: Raspberry Pi Pico SDK on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: diff --git a/.github/workflows/build-stm32-elf.yml b/.github/workflows/build-stm32-elf.yml index c423e11e..b0c9d076 100644 --- a/.github/workflows/build-stm32-elf.yml +++ b/.github/workflows/build-stm32-elf.yml @@ -3,8 +3,8 @@ name: STM32 ELF on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index bd017d96..53359209 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -15,7 +15,7 @@ jobs: strategy: fail-fast: false matrix: - example: [stm32-blink, stm32-lcd-logo, stm32-neopixel, stm32-uart-echo] + example: [stm32-blink] #, stm32-lcd-logo, stm32-neopixel, stm32-uart-echo] steps: - name: Checkout repo diff --git a/.github/workflows/build-zephyr.yml b/.github/workflows/build-zephyr.yml index 96c83b1c..6e6501b4 100644 --- a/.github/workflows/build-zephyr.yml +++ b/.github/workflows/build-zephyr.yml @@ -3,8 +3,8 @@ name: Zephyr on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index 11ad1aec..6bd4987c 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -3,8 +3,8 @@ name: Lint on: push: branches: ["main"] - pull_request: - types: [opened, reopened, synchronize, ready_for_review] + # pull_request: + # types: [opened, reopened, synchronize, ready_for_review] workflow_dispatch: jobs: From c5ad78ed4baf14fd9ef506a17a01d5cd310da7b0 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 11:16:23 -0700 Subject: [PATCH 14/20] update workflow --- .github/actions/install-swift/action.yml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index f488901b..7d47326c 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -61,7 +61,7 @@ runs: SWIFTLY_VERSION=1.0.1 SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" - installer -pkg $SWIFTLY_PKG -target CurrentUserHomeDirectory + installer -pkg $SWIFTLY_PKG -target CurrentUserHomeDirectory -verbose ./swiftly init \ --skip-install \ --assume-yes \ From 0f0e148021dafa3162796d30ad58962a96fa4c76 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 12:26:58 -0700 Subject: [PATCH 15/20] update workflow --- .github/actions/install-swift/action.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index 7d47326c..fe3fc657 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -62,6 +62,9 @@ runs: SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" installer -pkg $SWIFTLY_PKG -target CurrentUserHomeDirectory -verbose + pkgutil --check-signature $SWIFTLY_PKG + pkgutil --verbose --expand $SWIFTLY_PKG $SWIFTLY_HOME_DIR + tar -C $SWIFTLY_HOME_DIR -xvf $SWIFTLY_HOME_DIR/swiftly-*/Payload ./swiftly init \ --skip-install \ --assume-yes \ From 35898c207e1028e3a92959ed6a396053bb8b7efd Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 12:29:22 -0700 Subject: [PATCH 16/20] update workflow --- .github/actions/install-swift/action.yml | 1 - 1 file changed, 1 deletion(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index fe3fc657..e2e18c6a 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -61,7 +61,6 @@ runs: SWIFTLY_VERSION=1.0.1 SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" - installer -pkg $SWIFTLY_PKG -target CurrentUserHomeDirectory -verbose pkgutil --check-signature $SWIFTLY_PKG pkgutil --verbose --expand $SWIFTLY_PKG $SWIFTLY_HOME_DIR tar -C $SWIFTLY_HOME_DIR -xvf $SWIFTLY_HOME_DIR/swiftly-*/Payload From e68ea20d5ed038b404187a150b181c5400fe913c Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 12:32:06 -0700 Subject: [PATCH 17/20] update workflow --- .github/actions/install-swift/action.yml | 3 +++ 1 file changed, 3 insertions(+) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index e2e18c6a..1e6dbef6 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -8,14 +8,17 @@ runs: shell: bash run: | export SWIFTLY_HOME_DIR="$HOME/.local/share/swiftly" + mkdir -p "$SWIFTLY_HOME_DIR" echo "SWIFTLY_HOME_DIR=$SWIFTLY_HOME_DIR" >> $GITHUB_ENV echo "SWIFTLY_HOME_DIR=$SWIFTLY_HOME_DIR" >> $HOME/.bashrc export SWIFTLY_BIN_DIR="$HOME/.local/share/swiftly/bin" + mkdir -p "$SWIFTLY_BIN_DIR" echo "SWIFTLY_BIN_DIR=$SWIFTLY_BIN_DIR" >> $GITHUB_ENV echo "SWIFTLY_BIN_DIR=$SWIFTLY_BIN_DIR" >> $HOME/.bashrc export SWIFTLY_TOOLCHAINS_DIR="$HOME/.local/share/swiftly/toolchains" + mkdir -p "$SWIFTLY_TOOLCHAINS_DIR" echo "SWIFTLY_TOOLCHAINS_DIR=$SWIFTLY_TOOLCHAINS_DIR" >> $GITHUB_ENV echo "SWIFTLY_TOOLCHAINS_DIR=$SWIFTLY_TOOLCHAINS_DIR" >> $HOME/.bashrc From 359ea58c9e91a68866f246432bc6b8f3f1e1c1c2 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 12:33:12 -0700 Subject: [PATCH 18/20] update workflow --- .github/actions/install-swift/action.yml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index 1e6dbef6..f846edaf 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -7,25 +7,24 @@ runs: - name: Setup Environment shell: bash run: | + mkdir -p "$HOME/.local/share" + export SWIFTLY_HOME_DIR="$HOME/.local/share/swiftly" - mkdir -p "$SWIFTLY_HOME_DIR" echo "SWIFTLY_HOME_DIR=$SWIFTLY_HOME_DIR" >> $GITHUB_ENV echo "SWIFTLY_HOME_DIR=$SWIFTLY_HOME_DIR" >> $HOME/.bashrc export SWIFTLY_BIN_DIR="$HOME/.local/share/swiftly/bin" - mkdir -p "$SWIFTLY_BIN_DIR" echo "SWIFTLY_BIN_DIR=$SWIFTLY_BIN_DIR" >> $GITHUB_ENV echo "SWIFTLY_BIN_DIR=$SWIFTLY_BIN_DIR" >> $HOME/.bashrc export SWIFTLY_TOOLCHAINS_DIR="$HOME/.local/share/swiftly/toolchains" - mkdir -p "$SWIFTLY_TOOLCHAINS_DIR" echo "SWIFTLY_TOOLCHAINS_DIR=$SWIFTLY_TOOLCHAINS_DIR" >> $GITHUB_ENV echo "SWIFTLY_TOOLCHAINS_DIR=$SWIFTLY_TOOLCHAINS_DIR" >> $HOME/.bashrc echo "PATH=$SWIFTLY_BIN_DIR:$PATH" >> $GITHUB_ENV echo "PATH=\$SWIFTLY_BIN_DIR:\$PATH" >> $HOME/.bashrc - - name: "Restore: Swift" + - name: Restore Swift uses: actions/cache/restore@v4 id: cache-swift with: @@ -78,7 +77,7 @@ runs: shell: bash run: swiftly install --post-install-file ./out.sh - - name: "Save: Swift" + - name: Save Swift if: steps.cache-swift.outputs.cache-hit != 'true' uses: actions/cache/save@v4 with: From 600e5bca3e61ee6c3a8c5b7020a1b33de47d57c2 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 12:34:38 -0700 Subject: [PATCH 19/20] update workflow --- .github/actions/install-swift/action.yml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index f846edaf..4f528d4c 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -60,13 +60,15 @@ runs: if: runner.os == 'macOS' && steps.cache-swift.outputs.cache-hit != 'true' shell: bash run: | + set -ex + SWIFTLY_VERSION=1.0.1 SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" pkgutil --check-signature $SWIFTLY_PKG pkgutil --verbose --expand $SWIFTLY_PKG $SWIFTLY_HOME_DIR tar -C $SWIFTLY_HOME_DIR -xvf $SWIFTLY_HOME_DIR/swiftly-*/Payload - ./swiftly init \ + "$SWIFTLY_BIN_DIR/swiftly" init \ --skip-install \ --assume-yes \ --quiet-shell-followup \ From 49fadb0ccdee39b7e4f8b11aa5aac50647352c55 Mon Sep 17 00:00:00 2001 From: Rauhul Varma Date: Mon, 23 Jun 2025 12:47:04 -0700 Subject: [PATCH 20/20] update workflow --- .github/actions/install-swift/action.yml | 2 -- .github/workflows/build-stm32-elf.yml | 4 ---- .github/workflows/build-stm32-macho.yml | 27 +++++++----------------- 3 files changed, 8 insertions(+), 25 deletions(-) diff --git a/.github/actions/install-swift/action.yml b/.github/actions/install-swift/action.yml index 4f528d4c..2d1af791 100644 --- a/.github/actions/install-swift/action.yml +++ b/.github/actions/install-swift/action.yml @@ -60,8 +60,6 @@ runs: if: runner.os == 'macOS' && steps.cache-swift.outputs.cache-hit != 'true' shell: bash run: | - set -ex - SWIFTLY_VERSION=1.0.1 SWIFTLY_PKG=swiftly-$SWIFTLY_VERSION.pkg curl -O "https://download.swift.org/swiftly/darwin/$SWIFTLY_PKG" diff --git a/.github/workflows/build-stm32-elf.yml b/.github/workflows/build-stm32-elf.yml index b0c9d076..17cba14a 100644 --- a/.github/workflows/build-stm32-elf.yml +++ b/.github/workflows/build-stm32-elf.yml @@ -21,10 +21,6 @@ jobs: - name: Checkout repo uses: actions/checkout@v4 - - name: Fixup for running locally in act - if: ${{ env.ACT }} - run: echo /opt/acttoolcache/node/18.20.8/x64/bin >> $GITHUB_PATH - - name: Set up Python uses: actions/setup-python@v5 with: diff --git a/.github/workflows/build-stm32-macho.yml b/.github/workflows/build-stm32-macho.yml index 53359209..04264b5f 100644 --- a/.github/workflows/build-stm32-macho.yml +++ b/.github/workflows/build-stm32-macho.yml @@ -21,27 +21,16 @@ jobs: - name: Checkout repo uses: actions/checkout@v4 - - name: Install Swift - uses: ./.github/actions/install-swift - - - name: Validate Swiftly Paths - run: | - set -x - set +e - - env + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: 3.11 - cat $HOME/.bashrc + - name: Install uv + uses: astral-sh/setup-uv@v5 - echo "Swiftly Path: $SWIFTLY_HOME_DIR" - echo "Swiftly Bin Path: $SWIFTLY_BIN_DIR" - echo "Swiftly Lib Path: $SWIFTLY_TOOLCHAINS_DIR" - - ls -asl $SWIFTLY_HOME_DIR - ls -asl $SWIFTLY_BIN_DIR - ls -asl $SWIFTLY_TOOLCHAINS_DIR - - ls -asl $HOME/.local/share/swiftly + - name: Install Swift + uses: ./.github/actions/install-swift - name: Build ${{ matrix.example }} working-directory: ${{ matrix.example }}