diff --git a/app/boards/mt8188_mt8188_adsp.conf b/app/boards/mt8188_mt8188_adsp.conf
index 0d44864b6144..0b77906a891f 100644
--- a/app/boards/mt8188_mt8188_adsp.conf
+++ b/app/boards/mt8188_mt8188_adsp.conf
@@ -4,3 +4,7 @@
 # Board-level config goes in Zephyr (and ideally in DTS).  App-level
 # config goes in prj.conf.
 CONFIG_MTK=y
+
+# Override project default setting so 1 millisecond is exactly
+# represented by an integral number of ticks.
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=13000
diff --git a/app/boards/mt8195_mt8195_adsp.conf b/app/boards/mt8195_mt8195_adsp.conf
index 0d44864b6144..0b77906a891f 100644
--- a/app/boards/mt8195_mt8195_adsp.conf
+++ b/app/boards/mt8195_mt8195_adsp.conf
@@ -4,3 +4,7 @@
 # Board-level config goes in Zephyr (and ideally in DTS).  App-level
 # config goes in prj.conf.
 CONFIG_MTK=y
+
+# Override project default setting so 1 millisecond is exactly
+# represented by an integral number of ticks.
+CONFIG_SYS_CLOCK_TICKS_PER_SEC=13000
diff --git a/src/drivers/mediatek/afe/afe-memif.c b/src/drivers/mediatek/afe/afe-memif.c
index 5ca7d201757f..233eaec63748 100644
--- a/src/drivers/mediatek/afe/afe-memif.c
+++ b/src/drivers/mediatek/afe/afe-memif.c
@@ -437,7 +437,11 @@ static int memif_get_attribute(struct dma *dma, uint32_t type, uint32_t *value)
 		*value = 4;
 		break;
 	case DMA_ATTR_BUFFER_ADDRESS_ALIGNMENT:
+#if defined(CONFIG_SOC_SERIES_MT818X) || defined(CONFIG_SOC_MT8195)
+		*value = 64;
+#else
 		*value = 16;
+#endif
 		break;
 	case DMA_ATTR_BUFFER_PERIOD_COUNT:
 		*value = 4;
diff --git a/src/platform/mtk/dai.c b/src/platform/mtk/dai.c
index 0cc22445ca2f..cb6ebc144624 100644
--- a/src/platform/mtk/dai.c
+++ b/src/platform/mtk/dai.c
@@ -12,16 +12,25 @@
  */
 #if defined(CONFIG_SOC_MT8186)
 #define MTK_AFE_BASE 0x11210000
+#define SRAM_CPU_START 0x10800000
 #elif defined(CONFIG_SOC_SERIES_MT818X)
 #define MTK_AFE_BASE 0x10b10000
+#define SRAM_CPU_START 0x10d00000
 #elif defined(CONFIG_SOC_MT8195)
 #define MTK_AFE_BASE 0x10890000
+#define SRAM_CPU_START 0x10840000
 #elif defined(CONFIG_SOC_MT8196)
 #define MTK_AFE_BASE 0x1a110000
+#define SRAM_CPU_START 0x1a210000
 #else
 #error Unrecognized device
 #endif
 
+#define SRAM_ADSP_START	DT_REG_ADDR(DT_NODELABEL(sram0))
+#define SRAM_SIZE		DT_REG_SIZE(DT_NODELABEL(sram0))
+#define SRAM_ADSP_END	(SRAM_ADSP_START + SRAM_SIZE)
+#define SRAM_CPU_END	(SRAM_CPU_START + SRAM_SIZE)
+
 /* Bitfield register: address, left shift amount, and number of bits */
 struct afe_bitfld {
 	uint32_t reg;
@@ -70,7 +79,7 @@ struct afe_cfg {
  */
 static void cfg_convert(const struct afe_cfg *src, struct mtk_base_memif_data *dst)
 {
-#define REGCVT(R) (((R) > 0) ? ((R) - MTK_AFE_BASE) : -1)
+#define REGCVT(R) (((R) > 0) ? ((R) - MTK_AFE_BASE) : 0)
 
 #define COPYBIT(S, Dr, Ds) do {		\
 	dst->Dr = REGCVT(src->S.reg);	\
@@ -199,10 +208,68 @@ static const struct dai_info mtk_dai_info = {
 	.num_dai_types = ARRAY_SIZE(mtk_dai_types),
 };
 
+#if defined(CONFIG_SOC_SERIES_MT818X) || defined(CONFIG_SOC_MT8195)
+static unsigned int mtk_afe2adsp_addr(unsigned int addr)
+{
+	/* CPU -> ADSP address remap */
+	if ((addr >=  SRAM_CPU_START) && (addr <  SRAM_CPU_END)) {
+		addr = SRAM_ADSP_START + (addr -  SRAM_CPU_START);
+	}
+
+	return addr;
+}
+
+static unsigned int mtk_adsp2afe_addr(unsigned int addr)
+{
+	/* ADSP -> CPU address remap */
+	if ((addr >=  SRAM_ADSP_START) && (addr <  SRAM_ADSP_END)) {
+		addr = SRAM_CPU_START + (addr -  SRAM_ADSP_START);
+	}
+
+	return addr;
+}
+#endif
+
 /* Static table of fs register values.  TODO: binary search */
 static unsigned int mtk_afe_fs_timing(unsigned int rate)
 {
 	static const struct { int hz, reg; } rate2reg[] = {
+#if defined(CONFIG_SOC_MT8188) || defined(CONFIG_SOC_MT8195)
+		{   7350, 16 },
+		{   8000,  0 },
+		{  11025, 17 },
+		{  12000,  1 },
+		{  14700, 18 },
+		{  16000,  2 },
+		{  22050, 19 },
+		{  24000,  3 },
+		{  29400, 20 },
+		{  32000,  4 },
+		{  44100, 21 },
+		{  48000,  5 },
+		{  88200, 22 },
+		{  96000,  6 },
+		{ 176400, 23 },
+		{ 192000,  7 },
+		{ 352800, 24 },
+		{ 384000,  8 },
+#elif defined(CONFIG_SOC_MT8186)
+		{   8000,  0 },
+		{  11025,  1 },
+		{  12000,  2 },
+		{  16000,  4 },
+		{  22050,  5 },
+		{  24000,  6 },
+		{  32000,  8 },
+		{  44100,  9 },
+		{  48000, 10 },
+		{  88200, 11 },
+		{  96000, 12 },
+		{ 176400, 13 },
+		{ 192000, 14 },
+		{ 352800,  7 },
+		{ 384000,  3 },
+#else
 		{   8000,  0 },
 		{  11025,  1 },
 		{  12000,  2 },
@@ -218,6 +285,7 @@ static unsigned int mtk_afe_fs_timing(unsigned int rate)
 		{ 192000, 18 },
 		{ 352800, 21 },
 		{ 384000, 22 },
+#endif
 	};
 
 	for (int i = 0; i < ARRAY_SIZE(rate2reg); i++)
@@ -242,6 +310,10 @@ struct mtk_base_afe_platform mtk_afe_platform = {
 	.dais_size = ARRAY_SIZE(mtk_dais),
 	.afe_fs = mtk_afe_fs,
 	.irq_fs = mtk_afe_fs_timing,
+#if defined(CONFIG_SOC_SERIES_MT818X) || defined(CONFIG_SOC_MT8195)
+	.afe2adsp_addr = mtk_afe2adsp_addr,
+	.adsp2afe_addr = mtk_adsp2afe_addr,
+#endif
 };
 
 int mtk_dai_init(struct sof *sof)
diff --git a/zephyr/include/sof/lib/dma.h b/zephyr/include/sof/lib/dma.h
index 1b384412b123..3c7f56d7b5f5 100644
--- a/zephyr/include/sof/lib/dma.h
+++ b/zephyr/include/sof/lib/dma.h
@@ -122,7 +122,11 @@ enum sof_dma_cb_status {
 /* Attributes have been ported to Zephyr. This condition is necessary until full support of
  * CONFIG_SOF_ZEPHYR_STRICT_HEADERS.
  */
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 struct sof_dma;
+#else
+struct dma;
+#endif
 
 /**
  *  \brief Element of SG list (as array item).
@@ -194,7 +198,11 @@ struct dma_plat_data {
 	uint32_t period_count;
 };
 
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 struct sof_dma {
+#else
+struct dma {
+#endif
 	struct dma_plat_data plat_data;
 	struct k_spinlock lock;	/**< locking mechanism */
 	int sref;		/**< simple ref counter, guarded by lock */
@@ -206,7 +214,11 @@ struct sof_dma {
 };
 
 struct dma_chan_data {
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 	struct sof_dma *dma;
+#else
+	struct dma *dma;
+#endif
 
 	uint32_t status;
 	uint32_t direction;
@@ -224,14 +236,22 @@ struct dma_chan_data {
 };
 
 struct dma_info {
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 	struct sof_dma *dma_array;
+#else
+	struct dma *dma_array;
+#endif
 	size_t num_dmas;
 };
 
 /* generic DMA DSP <-> Host copier */
 struct dma_copy {
 	struct dma_chan_data *chan;
+#ifdef CONFIG_ZEPHYR_NATIVE_DRIVERS
 	struct sof_dma *dmac;
+#else
+	struct dma *dmac;
+#endif
 };
 
 struct audio_stream;
diff --git a/zephyr/lib/alloc.c b/zephyr/lib/alloc.c
index 77c5aaeccf3e..b81de8e3ea61 100644
--- a/zephyr/lib/alloc.c
+++ b/zephyr/lib/alloc.c
@@ -113,7 +113,13 @@ extern char _mtk_adsp_sram_end;
 #define SRAM_SIZE  DT_REG_SIZE(DT_NODELABEL(sram0))
 #define SRAM_END   (SRAM_START + SRAM_SIZE)
 #define heapmem ((uint8_t *)ALIGN_UP((uintptr_t)&_mtk_adsp_sram_end, PLATFORM_DCACHE_ALIGN))
+
+/* Heap size is limited to 0x7fffU chunk units when CONFIG_SYS_HEAP_SMALL_ONLY is set */
+#if defined(CONFIG_SYS_HEAP_SMALL_ONLY)
+#define HEAPMEM_SIZE MIN(((uint8_t *)SRAM_END - heapmem), 0x7fff * 8)
+#else
 #define HEAPMEM_SIZE ((uint8_t *)SRAM_END - heapmem)
+#endif /* CONFIG_SYS_HEAP_SMALL_ONLY */
 
 #else