diff --git a/app/boards/intel_adsp_ace40_nvl.conf b/app/boards/intel_adsp_ace40_nvl.conf new file mode 100644 index 000000000000..896456e37f4d --- /dev/null +++ b/app/boards/intel_adsp_ace40_nvl.conf @@ -0,0 +1,88 @@ +CONFIG_NOVALAKE=y +CONFIG_RIMAGE_SIGNING_SCHEMA="nvl" + +# SOF / IPC configuration +CONFIG_IPC_MAJOR_4=y +CONFIG_IPC4_BASE_FW_INTEL=y + +# SOF / audio pipeline and module settings +CONFIG_COMP_SRC=y +CONFIG_MM_DRV=y +CONFIG_COMP_ARIA=y +CONFIG_COMP_CHAIN_DMA=y +CONFIG_COMP_DRC=y +CONFIG_COMP_KPB=y +CONFIG_COMP_SRC_IPC4_FULL_MATRIX=y +CONFIG_COMP_UP_DOWN_MIXER=y +CONFIG_COMP_VOLUME_WINDOWS_FADE=y +CONFIG_FORMAT_CONVERT_HIFI3=n +CONFIG_FORMAT_U8=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C16_AND_S16_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S32_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C24_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C32_AND_S24_C24=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S16_C32=y +CONFIG_PCM_CONVERTER_FORMAT_U8=y +CONFIG_PIPELINE_2_0=y + +# SOF / infrastructure +CONFIG_PROBE=y +CONFIG_PROBE_DMA_MAX=2 +CONFIG_ZEPHYR_DP_SCHEDULER=y +CONFIG_ZEPHYR_NATIVE_DRIVERS=y + +# SOF / loadable modules +CONFIG_INTEL_MODULES=y +CONFIG_LIBRARY_MANAGER=y + +# SOF / logging +CONFIG_TRACE=n +CONFIG_SOF_LOG_LEVEL_INF=y +CONFIG_ZEPHYR_LOG=y + +# Zephyr / OS features +CONFIG_HEAP_MEM_POOL_SIZE=8192 +CONFIG_L3_HEAP=y + +# Zephyr / device drivers +CONFIG_CLOCK_CONTROL=y +CONFIG_CLOCK_CONTROL_ADSP=y +CONFIG_DAI=y +CONFIG_DAI_INIT_PRIORITY=70 +CONFIG_DAI_INTEL_DMIC=y +CONFIG_DAI_DMIC_HW_IOCLK=38400000 +CONFIG_DAI_INTEL_DMIC_NHLT=y +CONFIG_DAI_DMIC_HAS_OWNERSHIP=n +CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC=y +CONFIG_DAI_INTEL_SSP=y +CONFIG_DMA=y +CONFIG_DMA_INTEL_ADSP_GPDMA=n +CONFIG_INTEL_ADSP_IPC=y +CONFIG_INTEL_ADSP_TIMER=y +CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000 + +# Zephyr / power settings +CONFIG_ADSP_IMR_CONTEXT_SAVE=y +CONFIG_PM=y +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=y +CONFIG_PM_DEVICE_POWER_DOMAIN=y +CONFIG_PM_DEVICE_SYSTEM_MANAGED=y +CONFIG_PM_POLICY_CUSTOM=y +CONFIG_PM_PREWAKEUP_CONV_MODE_CEIL=y +CONFIG_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN_INTEL_ADSP=y +CONFIG_SRAM_RETENTION_MODE=n + +# Zephyr / logging +CONFIG_LOG=y +CONFIG_LOG_BACKEND_ADSP=n +CONFIG_LOG_BACKEND_ADSP_MTRACE=y +CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y +CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y +CONFIG_LOG_FUNC_NAME_PREFIX_INF=y +CONFIG_LOG_FUNC_NAME_PREFIX_DBG=y +CONFIG_LOG_MODE_DEFERRED=y +CONFIG_WINSTREAM_CONSOLE=n diff --git a/app/boards/intel_adsp_ace40_nvls.conf b/app/boards/intel_adsp_ace40_nvls.conf new file mode 100644 index 000000000000..896456e37f4d --- /dev/null +++ b/app/boards/intel_adsp_ace40_nvls.conf @@ -0,0 +1,88 @@ +CONFIG_NOVALAKE=y +CONFIG_RIMAGE_SIGNING_SCHEMA="nvl" + +# SOF / IPC configuration +CONFIG_IPC_MAJOR_4=y +CONFIG_IPC4_BASE_FW_INTEL=y + +# SOF / audio pipeline and module settings +CONFIG_COMP_SRC=y +CONFIG_MM_DRV=y +CONFIG_COMP_ARIA=y +CONFIG_COMP_CHAIN_DMA=y +CONFIG_COMP_DRC=y +CONFIG_COMP_KPB=y +CONFIG_COMP_SRC_IPC4_FULL_MATRIX=y +CONFIG_COMP_UP_DOWN_MIXER=y +CONFIG_COMP_VOLUME_WINDOWS_FADE=y +CONFIG_FORMAT_CONVERT_HIFI3=n +CONFIG_FORMAT_U8=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C16_AND_S16_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S32_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C24_AND_S24_C32=y +CONFIG_PCM_CONVERTER_FORMAT_S24_C32_AND_S24_C24=y +CONFIG_PCM_CONVERTER_FORMAT_S16_C32_AND_S16_C32=y +CONFIG_PCM_CONVERTER_FORMAT_U8=y +CONFIG_PIPELINE_2_0=y + +# SOF / infrastructure +CONFIG_PROBE=y +CONFIG_PROBE_DMA_MAX=2 +CONFIG_ZEPHYR_DP_SCHEDULER=y +CONFIG_ZEPHYR_NATIVE_DRIVERS=y + +# SOF / loadable modules +CONFIG_INTEL_MODULES=y +CONFIG_LIBRARY_MANAGER=y + +# SOF / logging +CONFIG_TRACE=n +CONFIG_SOF_LOG_LEVEL_INF=y +CONFIG_ZEPHYR_LOG=y + +# Zephyr / OS features +CONFIG_HEAP_MEM_POOL_SIZE=8192 +CONFIG_L3_HEAP=y + +# Zephyr / device drivers +CONFIG_CLOCK_CONTROL=y +CONFIG_CLOCK_CONTROL_ADSP=y +CONFIG_DAI=y +CONFIG_DAI_INIT_PRIORITY=70 +CONFIG_DAI_INTEL_DMIC=y +CONFIG_DAI_DMIC_HW_IOCLK=38400000 +CONFIG_DAI_INTEL_DMIC_NHLT=y +CONFIG_DAI_DMIC_HAS_OWNERSHIP=n +CONFIG_DAI_DMIC_HAS_MULTIPLE_LINE_SYNC=y +CONFIG_DAI_INTEL_SSP=y +CONFIG_DMA=y +CONFIG_DMA_INTEL_ADSP_GPDMA=n +CONFIG_INTEL_ADSP_IPC=y +CONFIG_INTEL_ADSP_TIMER=y +CONFIG_MM_DRV_INTEL_ADSP_TLB_REMAP_UNUSED_RAM=y +CONFIG_SYS_CLOCK_TICKS_PER_SEC=12000 + +# Zephyr / power settings +CONFIG_ADSP_IMR_CONTEXT_SAVE=y +CONFIG_PM=y +CONFIG_PM_DEVICE=y +CONFIG_PM_DEVICE_RUNTIME=y +CONFIG_PM_DEVICE_POWER_DOMAIN=y +CONFIG_PM_DEVICE_SYSTEM_MANAGED=y +CONFIG_PM_POLICY_CUSTOM=y +CONFIG_PM_PREWAKEUP_CONV_MODE_CEIL=y +CONFIG_POWER_DOMAIN=y +CONFIG_POWER_DOMAIN_INTEL_ADSP=y +CONFIG_SRAM_RETENTION_MODE=n + +# Zephyr / logging +CONFIG_LOG=y +CONFIG_LOG_BACKEND_ADSP=n +CONFIG_LOG_BACKEND_ADSP_MTRACE=y +CONFIG_LOG_FUNC_NAME_PREFIX_ERR=y +CONFIG_LOG_FUNC_NAME_PREFIX_WRN=y +CONFIG_LOG_FUNC_NAME_PREFIX_INF=y +CONFIG_LOG_FUNC_NAME_PREFIX_DBG=y +CONFIG_LOG_MODE_DEFERRED=y +CONFIG_WINSTREAM_CONSOLE=n diff --git a/app/overlays/nvl/fpga_overlay.conf b/app/overlays/nvl/fpga_overlay.conf new file mode 100644 index 000000000000..265e86579c59 --- /dev/null +++ b/app/overlays/nvl/fpga_overlay.conf @@ -0,0 +1,6 @@ +CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=19200000 +CONFIG_DAI_DMIC_HW_IOCLK=19200000 +CONFIG_XTENSA_CCOUNT_HZ=40105000 + +# limit logs to minimize runtime overhead of logging +CONFIG_SOF_LOG_LEVEL_ERR=y diff --git a/app/sample.yaml b/app/sample.yaml index 0098ece281a3..e40ad5cc4902 100644 --- a/app/sample.yaml +++ b/app/sample.yaml @@ -18,6 +18,8 @@ tests: - intel_adsp/ace30/ptl/sim - intel_adsp/ace30/wcl - intel_adsp/ace30/wcl/sim + - intel_adsp/ace40/nvl + - intel_adsp/ace40/nvls - imx8qm_mek/mimx8qm6/adsp - imx8qxp_mek/mimx8qx6/adsp - imx8mp_evk/mimx8ml8/adsp diff --git a/scripts/xtensa-build-zephyr.py b/scripts/xtensa-build-zephyr.py index ea266fab7166..bfb63d53de5e 100755 --- a/scripts/xtensa-build-zephyr.py +++ b/scripts/xtensa-build-zephyr.py @@ -180,6 +180,18 @@ class PlatformConfig: "ace30_LX7HiFi4_PIF", ipc4 = True ), + "nvl" : PlatformConfig( + "intel", "intel_adsp/ace40/nvl", + f"RI-2022.10{xtensa_tools_version_postfix}", + "ace4px_HiFi5MMU_PIF_nlib", + ipc4 = True + ), + "nvl-s" : PlatformConfig( + "intel", "intel_adsp/ace40/nvls", + f"RI-2022.10{xtensa_tools_version_postfix}", + "ace4px_HiFi5MMU_PIF_nlib", + ipc4 = True + ), # NXP platforms "imx8" : PlatformConfig( diff --git a/src/audio/asrc/asrc.toml b/src/audio/asrc/asrc.toml index 75bd79878c94..946842d13811 100644 --- a/src/audio/asrc/asrc.toml +++ b/src/audio/asrc/asrc.toml @@ -49,7 +49,7 @@ 12, 0, 0, 0, 20480, 30050000, 384, 192, 0, 30050, 0, 13, 0, 0, 0, 20480, 35152000, 384, 256, 0, 35152, 0, 14, 0, 0, 0, 20480, 81647000, 1536, 1440, 0, 81647, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 20480, 29755000, 64, 192, 0, 29755, 0, 1, 0, 0, 0, 20480, 58017000, 64, 384, 0, 58017, 0, 2, 0, 0, 0, 20480, 103471000, 512, 1440, 0, 103471, 0, diff --git a/src/audio/base_fw_intel.c b/src/audio/base_fw_intel.c index 2642fd3f7368..e50f66e764f9 100644 --- a/src/audio/base_fw_intel.c +++ b/src/audio/base_fw_intel.c @@ -103,7 +103,7 @@ __cold int basefw_vendor_hw_config(uint32_t *data_offset, char *data) tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_LP_EBB_COUNT_HW_CFG, PLATFORM_LPSRAM_EBB_COUNT); -#ifdef CONFIG_SOC_INTEL_ACE30 +#if defined(CONFIG_SOC_INTEL_ACE30) || defined(CONFIG_SOC_INTEL_ACE40) tuple = tlv_next(tuple); tlv_value_uint32_set(tuple, IPC4_I2S_CAPS_HW_CFG, I2S_VER_30_PTL); #endif diff --git a/src/audio/copier/copier.toml b/src/audio/copier/copier.toml index d28d9e77aa4e..3f3b0ac17899 100644 --- a/src/audio/copier/copier.toml +++ b/src/audio/copier/copier.toml @@ -92,7 +92,7 @@ 28, 0, 0, 0, 280, 6058000, 64, 64, 0, 6058, 0, 29, 0, 0, 0, 280, 6198000, 64, 64, 0, 6198, 0, 30, 0, 0, 0, 280, 6034000, 32, 32, 0, 6034, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 280, 7915000, 768, 768, 0, 7915, 0, 1, 0, 0, 0, 280, 9487000, 768, 768, 0, 9487, 0, 2, 0, 0, 0, 280, 7363000, 384, 384, 0, 7363, 0, diff --git a/src/audio/eq_iir/eq_iir.toml b/src/audio/eq_iir/eq_iir.toml index 593ac1cab21b..b02eeb360395 100644 --- a/src/audio/eq_iir/eq_iir.toml +++ b/src/audio/eq_iir/eq_iir.toml @@ -23,7 +23,8 @@ mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 1000, 0, 0, 0, 0, 0, 4096, 20663000, 768, 768, 0, 20663, 0, 0, 0, 0, 0, 4096, 11357000, 384, 384, 0, 11357, 0] -#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_SOC_INTEL_ACE30) +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_SOC_INTEL_ACE30) || \ + defined(CONFIG_SOC_INTEL_ACE40) mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] #endif diff --git a/src/audio/mixin_mixout/mixin_mixout.toml b/src/audio/mixin_mixout/mixin_mixout.toml index 2fd8fcd30c04..812505b19fa8 100644 --- a/src/audio/mixin_mixout/mixin_mixout.toml +++ b/src/audio/mixin_mixout/mixin_mixout.toml @@ -32,7 +32,7 @@ 2, 0, 0, 0, 296, 2448000, 512, 512, 0, 2448, 0, 3, 0, 0, 0, 296, 2160000, 128, 128, 0, 2160, 0, 4, 0, 0, 0, 296, 3268000, 1536, 1536, 0, 3268, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 296, 5091000, 384, 384, 0, 5091, 0, 1, 0, 0, 0, 296, 5111000, 384, 384, 0, 5111, 0, 2, 0, 0, 0, 296, 5195000, 512, 512, 0, 5195, 0, @@ -77,7 +77,7 @@ 2, 0, 0, 0, 520, 7631000, 512, 512, 0, 0, 0, 3, 0, 0, 0, 520, 1953000, 128, 128, 0, 0, 0, 4, 0, 0, 0, 520, 2301000, 1536, 1536, 0, 0, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 520, 3999000, 384, 384, 0, 3999, 0, 1, 0, 0, 0, 520, 3999000, 384, 384, 0, 3999, 0, 2, 0, 0, 0, 520, 4055000, 512, 512, 0, 4055, 0, diff --git a/src/audio/selector/selector.toml b/src/audio/selector/selector.toml index 1341931af7c9..69256573033f 100644 --- a/src/audio/selector/selector.toml +++ b/src/audio/selector/selector.toml @@ -39,7 +39,7 @@ 13, 0, 0, 0, 216, 8818000, 384, 1152, 0, 8818, 0, 14, 0, 0, 0, 216, 12274000, 768, 1152, 0, 12274, 0, 15, 0, 0, 0, 216, 19186000, 1536, 1152, 0, 19186, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 216, 2952000, 384, 192, 0, 2952, 0, 1, 0, 0, 0, 216, 4720000, 384, 384, 0, 4720, 0, 2, 0, 0, 0, 216, 5705000, 576, 384, 0, 5705, 0, diff --git a/src/audio/src/src.toml b/src/audio/src/src.toml index 30c42adc0907..4cf472b27641 100644 --- a/src/audio/src/src.toml +++ b/src/audio/src/src.toml @@ -72,7 +72,7 @@ 23, 0, 0, 0, 12832, 21852000, 180, 256, 0, 21852, 0, 24, 0, 0, 0, 12832, 12629000, 256, 512, 0, 12629, 0, 25, 0, 0, 0, 12832, 13996000, 128, 256, 0, 13996, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 12832, 30633000, 128, 512, 0, 30633, 0, 1, 0, 0, 0, 12832, 28143000, 64, 256, 0, 28143, 0, 2, 0, 0, 0, 12832, 33513000, 96, 512, 0, 33513, 0, diff --git a/src/audio/up_down_mixer/up_down_mixer.toml b/src/audio/up_down_mixer/up_down_mixer.toml index 5f5104037321..f233e44fa6aa 100644 --- a/src/audio/up_down_mixer/up_down_mixer.toml +++ b/src/audio/up_down_mixer/up_down_mixer.toml @@ -65,7 +65,7 @@ 16, 0, 0, 0, 216, 4596000, 768, 1152, 0, 4596, 0, 17, 0, 0, 0, 216, 5572000, 1536, 1152, 0, 5572, 0, 18, 0, 0, 0, 216, 4896000, 384, 1536, 0, 4896, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 216, 4841000, 384, 192, 0, 4841, 0, 1, 0, 0, 0, 216, 4355000, 384, 384, 0, 4355, 0, 2, 0, 0, 0, 216, 5079000, 576, 384, 0, 5079, 0, diff --git a/src/audio/volume/volume.toml b/src/audio/volume/volume.toml index 98aab232ac54..fed4defb37de 100644 --- a/src/audio/volume/volume.toml +++ b/src/audio/volume/volume.toml @@ -31,7 +31,7 @@ 2, 0, 0, 0, 480, 6846000, 720, 720, 0, 6846, 0, 3, 0, 0, 0, 480, 7212000, 768, 768, 0, 7212, 0, 4, 0, 0, 0, 480, 9532000, 1536, 1536, 0, 9532, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 480, 6993000, 384, 384, 0, 6993, 0, 1, 0, 0, 0, 480, 6385000, 192, 192, 0, 6385, 0, 2, 0, 0, 0, 480, 10887000, 720, 720, 0, 10887, 0, @@ -71,7 +71,7 @@ 2, 0, 0, 0, 416, 7882000, 512, 512, 0, 7882, 0, 3, 0, 0, 0, 416, 5170000, 128, 128, 0, 5170, 0, 4, 0, 0, 0, 416, 5908000, 768, 768, 0, 0, 0] -#elif CONFIG_SOC_INTEL_ACE30 +#elif CONFIG_SOC_INTEL_ACE30 || CONFIG_SOC_INTEL_ACE40 mod_cfg = [0, 0, 0, 0, 416, 11865000, 1536, 1536, 0, 11865, 0, 1, 0, 0, 0, 416, 7797000, 384, 384, 1, 7797, 1, 2, 0, 0, 0, 416, 12083000, 512, 512, 2, 12083, 2, diff --git a/src/debug/tester/tester.toml b/src/debug/tester/tester.toml index 415383eca039..a8c233166608 100644 --- a/src/debug/tester/tester.toml +++ b/src/debug/tester/tester.toml @@ -45,7 +45,8 @@ 23, 0, 0, 0, 12832, 27696000, 180, 256, 0, 27696, 0, 24, 0, 0, 0, 12832, 18368000, 256, 512, 0, 18368, 0, 25, 0, 0, 0, 12832, 15204000, 128, 256, 0, 15204, 0] -#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_SOC_INTEL_ACE30) +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_SOC_INTEL_ACE30) || \ + defined(CONFIG_SOC_INTEL_ACE40) mod_cfg = [0, 0, 0, 0, 12832, 1365500, 0, 0, 0, 1365, 0, 1, 0, 0, 0, 12832, 2302300, 0, 0, 0, 2302, 0, 2, 0, 0, 0, 12832, 3218200, 0, 0, 0, 3218, 0, diff --git a/src/platform/Kconfig b/src/platform/Kconfig index b72b36447f24..c19cf72f97c1 100644 --- a/src/platform/Kconfig +++ b/src/platform/Kconfig @@ -44,6 +44,13 @@ config WILDCATLAKE help Select if your target platform is Wildcatlake-compatible +config NOVALAKE + bool "Build for Novalake" + select ACE + select ACE_VERSION_4_0 + help + Select if your target platform is Novalake-compatible + config LIBRARY bool "Build Library" help @@ -327,9 +334,8 @@ endchoice config MAX_CORE_COUNT int - default 5 if LUNARLAKE - default 5 if PANTHERLAKE - default 4 if TIGERLAKE + default 5 if LUNARLAKE || PANTHERLAKE + default 4 if TIGERLAKE || NOVALAKE default 3 if METEORLAKE default 3 if WILDCATLAKE default 1 @@ -421,6 +427,12 @@ config ACE_VERSION_3_0 help Select for ACE version 3.0 +config ACE_VERSION_4_0 + depends on ACE + bool + help + Select for ACE version 4.0 + config HP_MEMORY_BANKS int "HP memory banks count" depends on CAVS diff --git a/src/platform/intel/ace/include/ace/version.h b/src/platform/intel/ace/include/ace/version.h index 1a1aa52381d7..c2df425307e6 100644 --- a/src/platform/intel/ace/include/ace/version.h +++ b/src/platform/intel/ace/include/ace/version.h @@ -11,6 +11,7 @@ #define ACE_VERSION_1_5 0x10500 /* MTL */ #define ACE_VERSION_2_0 0x20000 /* LNL */ #define ACE_VERSION_3_0 0x30000 /* PTL */ +#define ACE_VERSION_4_0 0x40000 /* NVL */ /* ACE version defined by CONFIG_ACE_VER_*/ #if defined(CONFIG_ACE_VERSION_1_5) @@ -19,6 +20,8 @@ #define ACE_VERSION ACE_VERSION_2_0 #elif defined(CONFIG_ACE_VERSION_3_0) #define ACE_VERSION ACE_VERSION_3_0 +#elif defined(CONFIG_ACE_VERSION_4_0) +#define ACE_VERSION ACE_VERSION_4_0 #endif #define HW_CFG_VERSION ACE_VERSION diff --git a/src/platform/novalake/include/platform/lib/clk.h b/src/platform/novalake/include/platform/lib/clk.h new file mode 100644 index 000000000000..e4017efcf329 --- /dev/null +++ b/src/platform/novalake/include/platform/lib/clk.h @@ -0,0 +1,37 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + */ + +#ifdef __SOF_LIB_CLK_H__ + +#ifndef __PLATFORM_LIB_CLK_H__ +#define __PLATFORM_LIB_CLK_H__ + +#include + +#define CLK_MAX_CPU_HZ CONFIG_XTENSA_CCOUNT_HZ + +#define CPU_WOVCRO_FREQ_IDX 0 + +#define CPU_LPRO_FREQ_IDX 1 + +#define CPU_HPRO_FREQ_IDX 2 + +#define CPU_LOWEST_FREQ_IDX CPU_WOVCRO_FREQ_IDX + +#define CPU_DEFAULT_IDX CPU_HPRO_FREQ_IDX + +#define NUM_CPU_FREQ 3 + +#endif /* __PLATFORM_LIB_CLK_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/clk.h" + +#endif /* __SOF_LIB_CLK_H__ */ diff --git a/src/platform/novalake/include/platform/lib/mailbox.h b/src/platform/novalake/include/platform/lib/mailbox.h new file mode 100644 index 000000000000..7d253fd9327e --- /dev/null +++ b/src/platform/novalake/include/platform/lib/mailbox.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + */ + +#ifdef __SOF_LIB_MAILBOX_H__ + +#ifndef __PLATFORM_LIB_MAILBOX_H__ +#define __PLATFORM_LIB_MAILBOX_H__ + +#include + +#endif /* __PLATFORM_LIB_MAILBOX_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/mailbox.h" + +#endif /* __SOF_LIB_MAILBOX_H__ */ diff --git a/src/platform/novalake/include/platform/lib/memory.h b/src/platform/novalake/include/platform/lib/memory.h new file mode 100644 index 000000000000..19ade62dfb2b --- /dev/null +++ b/src/platform/novalake/include/platform/lib/memory.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Marcin Rajwa + */ + +#ifdef __SOF_LIB_MEMORY_H__ + +#ifndef __PLATFORM_LIB_MEMORY_H__ +#define __PLATFORM_LIB_MEMORY_H__ + +/* prioritize definitions in Zephyr SoC layer */ +#include + +#include +#include +#include + +/* HP SRAM windows */ +#define WIN_BASE(n) DT_REG_ADDR(DT_PHANDLE(MEM_WINDOW_NODE(n), memory)) + +/* window 0 */ +#define SRAM_SW_REG_BASE ((uint32_t)(WIN_BASE(0) + WIN0_OFFSET)) +#define SRAM_SW_REG_SIZE 0x1000 + +#define SRAM_OUTBOX_BASE (SRAM_SW_REG_BASE + SRAM_SW_REG_SIZE) +#define SRAM_OUTBOX_SIZE 0x1000 + +/* window 1 */ +#define SRAM_INBOX_BASE ((uint32_t)(WIN_BASE(1) + WIN1_OFFSET)) +#define SRAM_INBOX_SIZE ((uint32_t)WIN_SIZE(1)) + +/* window 2 */ +#define SRAM_DEBUG_BASE ((uint32_t)(WIN_BASE(2) + WIN2_OFFSET)) +#define SRAM_DEBUG_SIZE 0x800 + +#define SRAM_EXCEPT_BASE (SRAM_DEBUG_BASE + SRAM_DEBUG_SIZE) +#define SRAM_EXCEPT_SIZE 0x800 + +#define SRAM_STREAM_BASE (SRAM_EXCEPT_BASE + SRAM_EXCEPT_SIZE) +#define SRAM_STREAM_SIZE 0x1000 + +/* Stack configuration */ +#define SOF_STACK_SIZE (CONFIG_SOF_STACK_SIZE) + +#define PLATFORM_HEAP_SYSTEM CONFIG_CORE_COUNT /* one per core */ +#define PLATFORM_HEAP_SYSTEM_RUNTIME CONFIG_CORE_COUNT /* one per core */ +#define PLATFORM_HEAP_RUNTIME 1 +#define PLATFORM_HEAP_RUNTIME_SHARED 1 +#define PLATFORM_HEAP_SYSTEM_SHARED 1 +#define PLATFORM_HEAP_BUFFER 2 + +/** + * size of HPSRAM system heap + */ +#define HEAPMEM_SIZE CONFIG_SOF_ZEPHYR_HEAP_SIZE + +#endif /* __PLATFORM_LIB_MEMORY_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/lib/memory.h" + +#endif /* __SOF_LIB_MEMORY_H__ */ diff --git a/src/platform/novalake/include/platform/platform.h b/src/platform/novalake/include/platform/platform.h new file mode 100644 index 000000000000..62ba6a24fe97 --- /dev/null +++ b/src/platform/novalake/include/platform/platform.h @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + * + * Author: Liam Girdwood + * Keyon Jie + * Rander Wang + * Xiuli Pan + */ + +#ifdef __SOF_PLATFORM_H__ + +#ifndef __PLATFORM_PLATFORM_H__ +#define __PLATFORM_PLATFORM_H__ + +#include + +/*! \def PLATFORM_DEFAULT_CLOCK + * \brief clock source for audio pipeline + * + * There are two types of clock: cpu clock which is a internal clock in + * xtensa core, and ssp clock which is provided by external HW IP. + * The choice depends on HW features on different platform + */ +#define PLATFORM_DEFAULT_CLOCK CLK_SSP + +/* Host page size */ +#define HOST_PAGE_SIZE 4096 + +/* Platform stream capabilities */ +#define PLATFORM_MAX_CHANNELS 8 +#define PLATFORM_MAX_STREAMS 16 + +/* local buffer size of DMA tracing */ +#define DMA_TRACE_LOCAL_SIZE (HOST_PAGE_SIZE * 2) + +#endif /* __PLATFORM_PLATFORM_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/platform.h" + +#endif /* __SOF_PLATFORM_H__ */ diff --git a/src/platform/novalake/include/platform/trace/trace.h b/src/platform/novalake/include/platform/trace/trace.h new file mode 100644 index 000000000000..2e1e6022854f --- /dev/null +++ b/src/platform/novalake/include/platform/trace/trace.h @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: BSD-3-Clause + * + * Copyright(c) 2022-2024 Intel Corporation. + */ + +#ifdef __SOF_TRACE_TRACE_H__ + +#ifndef __PLATFORM_TRACE_TRACE_H__ +#define __PLATFORM_TRACE_TRACE_H__ + +#include +#include +#include +#include + +/* Platform defined trace code */ +static inline void platform_trace_point(uint32_t x) +{ } + +#endif /* __PLATFORM_TRACE_TRACE_H__ */ + +#else + +#error "This file shouldn't be included from outside of sof/trace/trace.h" + +#endif /* __SOF_TRACE_TRACE_H__ */ diff --git a/src/platform/novalake/lib/clk.c b/src/platform/novalake/lib/clk.c new file mode 100644 index 000000000000..29a69aaab1d3 --- /dev/null +++ b/src/platform/novalake/lib/clk.c @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: BSD-3-Clause +// +// Copyright(c) 2022-2024 Intel Corporation. +// +// Author: Tomasz Lauda +// Janusz Jankowski + +#include +#include + +static const struct freq_table platform_cpu_freq[] = { + { 38400000, 38400 }, + { 120000000, 120000 }, + { CLK_MAX_CPU_HZ, CLK_MAX_CPU_HZ / 1000 } +}; + +STATIC_ASSERT(ARRAY_SIZE(platform_cpu_freq) == NUM_CPU_FREQ, invalid_number_of_cpu_frequencies); + +const struct freq_table *cpu_freq = platform_cpu_freq; diff --git a/src/samples/audio/smart_amp_test.toml b/src/samples/audio/smart_amp_test.toml index f7ac87a9ab1a..f0f4fa9339dc 100644 --- a/src/samples/audio/smart_amp_test.toml +++ b/src/samples/audio/smart_amp_test.toml @@ -23,7 +23,8 @@ REM # mod_cfg [PAR_0 PAR_1 PAR_2 PAR_3 IS_BYTES CPS IBS OBS MOD_FLAGS CPC OBLS] #ifdef CONFIG_METEORLAKE mod_cfg = [0, 0, 0, 0, 296, 5000000, 384, 384, 0, 5000, 0] -#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_SOC_INTEL_ACE30) +#elif defined(CONFIG_LUNARLAKE) || defined(CONFIG_SOC_INTEL_ACE30) || \ + defined(CONFIG_SOC_INTEL_ACE40) mod_cfg = [0, 0, 0, 0, 4096, 1000000, 128, 128, 0, 0, 0] #endif diff --git a/tools/rimage/config/nvl.toml.h b/tools/rimage/config/nvl.toml.h new file mode 100644 index 000000000000..a14029ff3fe5 --- /dev/null +++ b/tools/rimage/config/nvl.toml.h @@ -0,0 +1,124 @@ +#include "platform-nvl.toml" + +[[module.entry]] +name = "BRNGUP" +uuid = "2B79E4F3-4675-F649-89DF-3BC194A91AEB" +affinity_mask = "0x1" +instance_count = "1" +domain_types = "0" +load_type = "0" +module_type = "0" +auto_start = "0" + +index = __COUNTER__ + +[[module.entry]] +name = "BASEFW" +uuid = "0E398C32-5ADE-BA4B-93B1-C50432280EE4" +affinity_mask = "3" +instance_count = "1" +domain_types = "0" +load_type = "0" +module_type = "0" +auto_start = "0" + +index = __COUNTER__ + +#ifdef CONFIG_COMP_MIXIN_MIXOUT +#include