diff --git a/app/overlays/lnl/fpga_overlay.conf b/app/overlays/lnl/fpga_overlay.conf
index 5338ad654a66..0cc927a119ee 100644
--- a/app/overlays/lnl/fpga_overlay.conf
+++ b/app/overlays/lnl/fpga_overlay.conf
@@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/mtl/fpga_overlay.conf b/app/overlays/mtl/fpga_overlay.conf
index 5338ad654a66..0cc927a119ee 100644
--- a/app/overlays/mtl/fpga_overlay.conf
+++ b/app/overlays/mtl/fpga_overlay.conf
@@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/nvl/fpga_overlay.conf b/app/overlays/nvl/fpga_overlay.conf
index 265e86579c59..176598376be0 100644
--- a/app/overlays/nvl/fpga_overlay.conf
+++ b/app/overlays/nvl/fpga_overlay.conf
@@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40105000
 
 # limit logs to minimize runtime overhead of logging
 CONFIG_SOF_LOG_LEVEL_ERR=y
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/ptl/fpga_overlay.conf b/app/overlays/ptl/fpga_overlay.conf
index bfcb7eae8819..f2f0eee4ab2d 100644
--- a/app/overlays/ptl/fpga_overlay.conf
+++ b/app/overlays/ptl/fpga_overlay.conf
@@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/app/overlays/wcl/fpga_overlay.conf b/app/overlays/wcl/fpga_overlay.conf
index bfcb7eae8819..f2f0eee4ab2d 100644
--- a/app/overlays/wcl/fpga_overlay.conf
+++ b/app/overlays/wcl/fpga_overlay.conf
@@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y
 
 # improves LPSRAM and HPSRAM access time
 CONFIG_SRAM_RETENTION_MODE=n
+
+CONFIG_IDC_TIMEOUT_US=50000
diff --git a/posix/include/rtos/idc.h b/posix/include/rtos/idc.h
index 5cbe8ea73a7f..a9a03258712f 100644
--- a/posix/include/rtos/idc.h
+++ b/posix/include/rtos/idc.h
@@ -34,9 +34,6 @@
 /** \brief IDC send core power down flag. */
 #define IDC_POWER_DOWN		3
 
-/** \brief IDC send timeout in microseconds. */
-#define IDC_TIMEOUT	10000
-
 /** \brief IDC task deadline. */
 #define IDC_DEADLINE	100
 
diff --git a/src/Kconfig b/src/Kconfig
index a9df53c787d5..0ad749042db8 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -17,6 +17,8 @@ rsource "samples/Kconfig"
 rsource "schedule/Kconfig"
 rsource "schedule/Kconfig.threads_prio"
 
+rsource "idc/Kconfig"
+
 rsource "ipc/Kconfig"
 
 rsource "math/Kconfig"
diff --git a/src/idc/Kconfig b/src/idc/Kconfig
new file mode 100644
index 000000000000..d2e74c066b4d
--- /dev/null
+++ b/src/idc/Kconfig
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: BSD-3-Clause
+
+config IDC_TIMEOUT_US
+	int "Timeout for blocking IDC call, microseconds"
+	default 15000
+	help
+	  It may be beneficial to have different timeout values
+	  for fast platforms (manufactured silicon) and at least
+	  10 times slower FPGA platforms.
diff --git a/src/idc/zephyr_idc.c b/src/idc/zephyr_idc.c
index a0b2840f4ca2..afd30628a5d3 100644
--- a/src/idc/zephyr_idc.c
+++ b/src/idc/zephyr_idc.c
@@ -165,7 +165,7 @@ int idc_send_msg(struct idc_msg *msg, uint32_t mode)
 
 	switch (mode) {
 	case IDC_BLOCKING:
-		ret = k_p4wq_wait(work, K_USEC(IDC_TIMEOUT));
+		ret = k_p4wq_wait(work, K_USEC(CONFIG_IDC_TIMEOUT_US));
 		if (!ret)
 			/* message was sent and executed successfully, get status code */
 			ret = idc_msg_status_get(msg->core);
diff --git a/zephyr/include/rtos/idc.h b/zephyr/include/rtos/idc.h
index e5b1e5f59cbc..a8616d9e2a11 100644
--- a/zephyr/include/rtos/idc.h
+++ b/zephyr/include/rtos/idc.h
@@ -34,9 +34,6 @@
 /** \brief IDC send core power down flag. */
 #define IDC_POWER_DOWN		3
 
-/** \brief IDC send timeout in microseconds. */
-#define IDC_TIMEOUT	10000
-
 /** \brief IDC task deadline. */
 #define IDC_DEADLINE	100