From ce5e7316023b3ea1432386e74b0d309c93f49079 Mon Sep 17 00:00:00 2001 From: Serhiy Katsyuba Date: Fri, 19 Sep 2025 16:18:41 +0200 Subject: [PATCH 1/3] idc: Make IDC timeout value configurable It may be beneficial to have different timeout values for fast platforms (manufactured silicon) and at least 10 times slower FPGA platforms. Signed-off-by: Serhiy Katsyuba --- posix/include/rtos/idc.h | 3 --- src/Kconfig | 2 ++ src/idc/Kconfig | 9 +++++++++ src/idc/zephyr_idc.c | 2 +- zephyr/include/rtos/idc.h | 3 --- 5 files changed, 12 insertions(+), 7 deletions(-) create mode 100644 src/idc/Kconfig diff --git a/posix/include/rtos/idc.h b/posix/include/rtos/idc.h index 5cbe8ea73a7f..a9a03258712f 100644 --- a/posix/include/rtos/idc.h +++ b/posix/include/rtos/idc.h @@ -34,9 +34,6 @@ /** \brief IDC send core power down flag. */ #define IDC_POWER_DOWN 3 -/** \brief IDC send timeout in microseconds. */ -#define IDC_TIMEOUT 10000 - /** \brief IDC task deadline. */ #define IDC_DEADLINE 100 diff --git a/src/Kconfig b/src/Kconfig index a9df53c787d5..0ad749042db8 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -17,6 +17,8 @@ rsource "samples/Kconfig" rsource "schedule/Kconfig" rsource "schedule/Kconfig.threads_prio" +rsource "idc/Kconfig" + rsource "ipc/Kconfig" rsource "math/Kconfig" diff --git a/src/idc/Kconfig b/src/idc/Kconfig new file mode 100644 index 000000000000..d9e1383f1f8a --- /dev/null +++ b/src/idc/Kconfig @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: BSD-3-Clause + +config IDC_TIMEOUT_US + int "Timeout for blocking IDC call, microseconds" + default 10000 + help + It may be beneficial to have different timeout values + for fast platforms (manufactured silicon) and at least + 10 times slower FPGA platforms. diff --git a/src/idc/zephyr_idc.c b/src/idc/zephyr_idc.c index a0b2840f4ca2..afd30628a5d3 100644 --- a/src/idc/zephyr_idc.c +++ b/src/idc/zephyr_idc.c @@ -165,7 +165,7 @@ int idc_send_msg(struct idc_msg *msg, uint32_t mode) switch (mode) { case IDC_BLOCKING: - ret = k_p4wq_wait(work, K_USEC(IDC_TIMEOUT)); + ret = k_p4wq_wait(work, K_USEC(CONFIG_IDC_TIMEOUT_US)); if (!ret) /* message was sent and executed successfully, get status code */ ret = idc_msg_status_get(msg->core); diff --git a/zephyr/include/rtos/idc.h b/zephyr/include/rtos/idc.h index e5b1e5f59cbc..a8616d9e2a11 100644 --- a/zephyr/include/rtos/idc.h +++ b/zephyr/include/rtos/idc.h @@ -34,9 +34,6 @@ /** \brief IDC send core power down flag. */ #define IDC_POWER_DOWN 3 -/** \brief IDC send timeout in microseconds. */ -#define IDC_TIMEOUT 10000 - /** \brief IDC task deadline. */ #define IDC_DEADLINE 100 From 93adac656c1cdb4dc10d9fe117fc7a86204f7ce1 Mon Sep 17 00:00:00 2001 From: Serhiy Katsyuba Date: Mon, 22 Sep 2025 10:49:17 +0200 Subject: [PATCH 2/3] idc: Increase default IDC timeout With the introduction of LLEXT modules, the time to free a module increased as log_flush() is called as part of module unloading. log_flush() takes 5 ms if at least one line of logs has to be flushed. Let's add these 5 ms to the previous 10 ms IDC timeout to have a default timeout of 15 ms. Signed-off-by: Serhiy Katsyuba --- src/idc/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/idc/Kconfig b/src/idc/Kconfig index d9e1383f1f8a..d2e74c066b4d 100644 --- a/src/idc/Kconfig +++ b/src/idc/Kconfig @@ -2,7 +2,7 @@ config IDC_TIMEOUT_US int "Timeout for blocking IDC call, microseconds" - default 10000 + default 15000 help It may be beneficial to have different timeout values for fast platforms (manufactured silicon) and at least From 844b21a94e470ac7b7f1c00ab284fd06116567a4 Mon Sep 17 00:00:00 2001 From: Serhiy Katsyuba Date: Fri, 19 Sep 2025 16:32:29 +0200 Subject: [PATCH 3/3] intel: Increase IDC timeout for FPGAs Blocking IDC is used to call comp_free() for a DP component instantiated on a different core than its pipeline. On FPGA, unloading an LLEXT module takes almost 10 ms (for the SRC module, which has a lot of rodata). In addition, log_flush() takes at least 5 ms if there are some logs to flush. However, FPGA seems to have a tendency to have more deferred logs, and log_flush() could take even more time. Let's increase the IDC timeout for FPGA to 50 ms, compared to 15 ms on silicon. Signed-off-by: Serhiy Katsyuba --- app/overlays/lnl/fpga_overlay.conf | 2 ++ app/overlays/mtl/fpga_overlay.conf | 2 ++ app/overlays/nvl/fpga_overlay.conf | 2 ++ app/overlays/ptl/fpga_overlay.conf | 2 ++ app/overlays/wcl/fpga_overlay.conf | 2 ++ 5 files changed, 10 insertions(+) diff --git a/app/overlays/lnl/fpga_overlay.conf b/app/overlays/lnl/fpga_overlay.conf index 5338ad654a66..0cc927a119ee 100644 --- a/app/overlays/lnl/fpga_overlay.conf +++ b/app/overlays/lnl/fpga_overlay.conf @@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000 # improves LPSRAM and HPSRAM access time CONFIG_SRAM_RETENTION_MODE=n + +CONFIG_IDC_TIMEOUT_US=50000 diff --git a/app/overlays/mtl/fpga_overlay.conf b/app/overlays/mtl/fpga_overlay.conf index 5338ad654a66..0cc927a119ee 100644 --- a/app/overlays/mtl/fpga_overlay.conf +++ b/app/overlays/mtl/fpga_overlay.conf @@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40000000 # improves LPSRAM and HPSRAM access time CONFIG_SRAM_RETENTION_MODE=n + +CONFIG_IDC_TIMEOUT_US=50000 diff --git a/app/overlays/nvl/fpga_overlay.conf b/app/overlays/nvl/fpga_overlay.conf index 265e86579c59..176598376be0 100644 --- a/app/overlays/nvl/fpga_overlay.conf +++ b/app/overlays/nvl/fpga_overlay.conf @@ -4,3 +4,5 @@ CONFIG_XTENSA_CCOUNT_HZ=40105000 # limit logs to minimize runtime overhead of logging CONFIG_SOF_LOG_LEVEL_ERR=y + +CONFIG_IDC_TIMEOUT_US=50000 diff --git a/app/overlays/ptl/fpga_overlay.conf b/app/overlays/ptl/fpga_overlay.conf index bfcb7eae8819..f2f0eee4ab2d 100644 --- a/app/overlays/ptl/fpga_overlay.conf +++ b/app/overlays/ptl/fpga_overlay.conf @@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y # improves LPSRAM and HPSRAM access time CONFIG_SRAM_RETENTION_MODE=n + +CONFIG_IDC_TIMEOUT_US=50000 diff --git a/app/overlays/wcl/fpga_overlay.conf b/app/overlays/wcl/fpga_overlay.conf index bfcb7eae8819..f2f0eee4ab2d 100644 --- a/app/overlays/wcl/fpga_overlay.conf +++ b/app/overlays/wcl/fpga_overlay.conf @@ -6,3 +6,5 @@ CONFIG_SOF_LOG_LEVEL_ERR=y # improves LPSRAM and HPSRAM access time CONFIG_SRAM_RETENTION_MODE=n + +CONFIG_IDC_TIMEOUT_US=50000