A C-like hardware description language (HDL) adding high level synthesis(HLS)-like automatic pipelining as a language construct/compiler feature.

Vitis_Accel_Examples

Intermediate Language (IL) for Hardware Accelerator Generators

HeteroCL: A Multi-Paradigm Programming Infrastructure for Software-Defined Heterogeneous Computing (FPGA'19 Best Paper)

A curated collection of technical documentation for Arcades, Handhelds, Consoles, Computers and MCU’s.

Time-sensitive affine types for predictable hardware generation

A new Hardware Design Language that keeps you in the driver's seat

assorted library of utility cores for amaranth HDL

High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS

riffpga -- write FPGA bitstreams through a USB drive, get USB serial and dynamic clocking in a platform independent way

Intel Quartus Prime Synthesis Engine for Docker

A graph linear algebra overlay

HeteroCL-MLIR dialect for accelerator design

This is BISS-C FPGA IP and It's Driver Repo

Verilog Implementation of Run Length Encoding for RGB Image Compression

learn the combinational and sequential logic circuit.

上海交通大学软件学院🍭操作系统课程🍦实验

FPGA Hardware Simulation Framework

Příklady ke knize Data, čipy, procesory

基于易灵思Ti60F225开发板和MT9M001双目摄像头，使用Verilog语言完成的双目拼接项目。摄像头输入图像数据后，在使用FAST计算图像特征点的同时，构建滑动窗口计算图像各个像素点的BRIEF描述符，完成后根据BRIEF描述符对两幅图像上的特征点进行暴力匹配，最后通过匹配结果计算拼接参数，完成图像的拼接。