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scottwcpgnashif
scottwcpg
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nashif
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modules : hal : microchip Add remaining MEC1501 HAL headers
Updates the MEC1501 peripheral headers to version 0.2. Added the missing peripheral header files to the MEC1501 HAL. The added peripherals are: ACPI PM1, ADC, HDMI_CEC, PECI, PROCHOT, PWM, RTC, SPI slave, TACH, VBAT VCI. Modified headers are ACPI EC, ECIA, ECS, QMSPI, VBAT, and WDT. Origin: Peripheral-MEC1501 License: Apache 2.0 URL: https://github.com/MicrochipTech/Peripheral-MEC1501 Purpose: Provide device header files for MEC1501 Maintained-by: External Signed-off-by: Scott Worley <scott.worley@microchip.com>
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16 files changed

+1956
-75
lines changed

16 files changed

+1956
-75
lines changed

‎mec/common/mec_cpu.h‎

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Original file line numberDiff line numberDiff line change
@@ -283,6 +283,10 @@ static __always_inline void write_read_back32(volatile uint32_t* addr, uint32_t
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#endif
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286+
#ifdef __cplusplus
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}
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#endif
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#endif /* #ifndef _CPU_H */
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/** @}
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*/

‎mec/mec1501/MEC1501hsz.h‎

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@@ -431,6 +431,7 @@ typedef enum IRQn {
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/** @} *//* End of group Device_Peripheral_peripheralAddr */
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#include "component/acpi_ec.h"
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#include "component/adc.h"
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#include "component/dma.h"
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#include "component/ecia.h"
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#include "component/ecs.h"
@@ -440,16 +441,24 @@ typedef enum IRQn {
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#include "component/espi_mem.h"
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#include "component/espi_vw.h"
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#include "component/global_cfg.h"
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#include "component/hdmi_cec.h"
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#include "component/i2c.h"
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#include "component/kbc.h"
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#include "component/keyscan.h"
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#include "component/led.h"
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#include "component/mailbox.h"
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#include "component/pcr.h"
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#include "component/peci.h"
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#include "component/port80cap.h"
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#include "component/port92.h"
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#include "component/prochot.h"
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#include "component/ps2_ctrl.h"
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#include "component/pwm.h"
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#include "component/qmspi.h"
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#include "component/rtc.h"
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#include "component/smb.h"
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#include "component/spi_slave.h"
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#include "component/tach.h"
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#include "component/tfdp.h"
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#include "component/timer.h"
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#include "component/uart.h"
@@ -486,14 +495,39 @@ typedef enum IRQn {
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#define DMA10_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(10)))
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#define DMA11_REGS ((DMA_CHAN_Type *)(DMA_CHAN_BASE(11)))
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#define PROCHOT_REGS ((PROCHOT_Type *) PROCHOT_BASE)
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#define SMB0_REGS ((I2C_SMB_Type *) SMB0_BASE)
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#define SMB1_REGS ((I2C_SMB_Type *) SMB1_BASE)
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#define SMB2_REGS ((I2C_SMB_Type *) SMB2_BASE)
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#define SMB3_REGS ((I2C_SMB_Type *) SMB3_BASE)
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#define SMB4_REGS ((I2C_SMB_Type *) SMB4_BASE)
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#define PWM0_REGS ((PWM_Type *) PWM0_BASE)
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#define PWM1_REGS ((PWM_Type *) PWM1_BASE)
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#define PWM2_REGS ((PWM_Type *) PWM2_BASE)
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#define PWM3_REGS ((PWM_Type *) PWM3_BASE)
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#define PWM4_REGS ((PWM_Type *) PWM4_BASE)
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#define PWM5_REGS ((PWM_Type *) PWM5_BASE)
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#define PWM6_REGS ((PWM_Type *) PWM6_BASE)
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#define PWM7_REGS ((PWM_Type *) PWM7_BASE)
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#define PWM8_REGS ((PWM_Type *) PWM8_BASE)
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#define TACH0_REGS ((TACH_Type *) TACH0_BASE)
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#define TACH1_REGS ((TACH_Type *) TACH1_BASE)
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#define TACH2_REGS ((TACH_Type *) TACH2_BASE)
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#define TACH3_REGS ((TACH_Type *) TACH3_BASE)
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#define PECI_REGS ((PECI_Type *) PECI_BASE)
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#define HDMI_CEC_REGS ((HDMI_CEC_Type *) HDMI_CEC_BASE)
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#define SPISLV_REGS ((SPISLV_Type *) SPISLV_BASE)
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#define RTMR_REGS ((RTMR_Type *) RTMR_BASE)
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#define ADC_REGS ((ADC_Type *) ADC_BASE)
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#define TFDP_REGS ((TFDP_Type *) TFDP_BASE)
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#define PS2_0_REGS ((PS2_Type *) PS2_0_BASE)
@@ -508,6 +542,8 @@ typedef enum IRQn {
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#define VBATM_REGS ((VBATM_Type *) VBATM_BASE)
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#define WKTMR_REGS ((WKTMR_Type *) WKTMR_BASE)
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#define VCI_REGS ((VCI_Type *) VCI_BASE)
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#define LED0_REGS ((LED_Type *) LED0_BASE)
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#define LED1_REGS ((LED_Type *) LED1_BASE)
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#define LED2_REGS ((LED_Type *) LED2_BASE)
@@ -554,6 +590,8 @@ typedef enum IRQn {
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#define ACPI_EC_2_REGS ((ACPI_EC_Type *)(ACPI_EC_2_BASE))
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#define ACPI_EC_3_REGS ((ACPI_EC_Type *)(ACPI_EC_3_BASE))
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#define ACPI_PM1_REGS ((ACPI_PM1_Type *) ACPI_PM1_BASE)
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#define PORT92_REGS ((PORT92_Type *)(PORT92_BASE))
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#define UART0_REGS ((UART_Type *) UART0_BASE)
@@ -586,6 +624,8 @@ typedef enum IRQn {
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#define EMI0_REGS ((EMI_Type *)(EMI0_BASE))
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#define EMI1_REGS ((EMI_Type *)(EMI0_BASE))
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#define RTC_REGS ((RTC_Type *) RTC_BASE)
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#define PORT80_CAP0_REGS ((PORT80_CAP_Type *)(P80CAP0_BASE))
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#define PORT80_CAP1_REGS ((PORT80_CAP_Type *)(P80CAP1_BASE))
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‎mec/mec1501/component/acpi_ec.h‎

Lines changed: 117 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -39,7 +39,7 @@
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#include "regaccess.h"
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/* =========================================================================*/
42-
/* ================ ACPI_EC ================ */
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/* ================ ACPI_EC =================== */
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/* =========================================================================*/
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4545
#define MCHP_ACPI_EC_BASE_ADDR 0x400F0800ul
@@ -129,8 +129,7 @@
129129
/**
130130
* @brief ACPI EC Registers (ACPI_EC)
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*/
132-
typedef struct acpi_ec_regs
133-
{
132+
typedef struct acpi_ec_regs {
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__IOM uint32_t OS_DATA; /*!< (@ 0x0000) OS Data */
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__IOM uint8_t OS_CMD_STS; /*!< (@ 0x0004) OS Command(WO), Status(RO) */
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__IOM uint8_t OS_BYTE_CTRL; /*!< (@ 0x0005) OS Byte Control */
@@ -142,6 +141,121 @@ typedef struct acpi_ec_regs
142141
__IOM uint32_t OS2EC_DATA; /*!< (@ 0x0108) OS to EC Data */
143142
} ACPI_EC_Type;
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144+
/* =========================================================================*/
145+
/* ================ ACPI_PM1 =================== */
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/* =========================================================================*/
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148+
#define MCHP_ACPI_PM1_BASE_ADDR 0x400F1C00ul
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/*
151+
* ACPI_PM1 interrupts
152+
*/
153+
#define MCHP_ACPI_PM1_CTL_GIRQ 15u
154+
#define MCHP_ACPI_PM1_EN_GIRQ 15u
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#define MCHP_ACPI_PM1_STS_GIRQ 15u
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/* Bit position in GIRQ Source, Enable-Set/Clr, and Result registers */
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#define MCHP_ACPI_PM1_CTL_GIRQ_POS 15u
159+
#define MCHP_ACPI_PM1_EN_GIRQ_POS 16u
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#define MCHP_ACPI_PM1_STS_GIRQ_POS 17u
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162+
#define MCHP_ACPI_PM1_CTL_GIRQ_VAL (1ul << MCHP_ACPI_PM1_CTL_GIRQ_POS)
163+
#define MCHP_ACPI_PM1_EN_GIRQ_VAL (1ul << MCHP_ACPI_PM1_EN_GIRQ_POS)
164+
#define MCHP_ACPI_PM1_STS_GIRQ_VAL (1ul << MCHP_ACPI_PM1_STS_GIRQ_POS)
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166+
/* VCI GIRQ aggregated NVIC input */
167+
#define MCHP_ACPI_PM1_CTL_NVIC_AGGR 7u
168+
#define MCHP_ACPI_PM1_EN_NVIC_AGGR 7u
169+
#define MCHP_ACPI_PM1_STS_NVIC_AGGR 7u
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171+
/* VCI direct NVIC inputs */
172+
#define MCHP_ACPI_PM1_CTL_NVIC_DIRECT 55u
173+
#define MCHP_ACPI_PM1_EN_NVIC_DIRECT 56u
174+
#define MCHP_ACPI_PM1_STS_NVIC_DIRECT 57u
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176+
/* ACPI_PM1 RT/EC Status 1 */
177+
#define MCHP_ACPI_PM1_RT_STS1_REG_OFS 0x0000ul
178+
#define MCHP_ACPI_PM1_EC_STS1_REG_OFS 0x0100ul
179+
#define MCHP_ACPI_PM1_STS1_REG_MASK 0x0000ul
180+
181+
/* ACPI_PM1 RT/EC Status 2 */
182+
#define MCHP_ACPI_PM1_RT_STS2_REG_OFS 0x0001ul
183+
#define MCHP_ACPI_PM1_EC_STS2_REG_OFS 0x0101ul
184+
#define MCHP_ACPI_PM1_STS2_REG_MASK 0x008Ful
185+
#define MCHP_ACPI_PM1_STS2_PWRBTN (1ul << 0)
186+
#define MCHP_ACPI_PM1_STS2_SLPBTN (1ul << 1)
187+
#define MCHP_ACPI_PM1_STS2_RTC (1ul << 2)
188+
#define MCHP_ACPI_PM1_STS2_PWRBTNOR (1ul << 3)
189+
#define MCHP_ACPI_PM1_STS2_WAK (1ul << 7)
190+
191+
/* ACPI_PM1 RT/EC Enable 1 */
192+
#define MCHP_ACPI_PM1_RT_EN1_REG_OFS 0x0002ul
193+
#define MCHP_ACPI_PM1_EC_EN1_REG_OFS 0x0102ul
194+
#define MCHP_ACPI_PM1_EN1_REG_MASK 0x0000ul
195+
196+
/* ACPI_PM1 RT/EC Enable 2 */
197+
#define MCHP_ACPI_PM1_RT_EN2_REG_OFS 0x0003ul
198+
#define MCHP_ACPI_PM1_EC_EN2_REG_OFS 0x0103ul
199+
#define MCHP_ACPI_PM1_EN2_REG_MASK 0x0007ul
200+
#define MCHP_ACPI_PM1_EN2_PWRBTN (1ul << 0)
201+
#define MCHP_ACPI_PM1_EN2_SLPBTN (1ul << 1)
202+
#define MCHP_ACPI_PM1_EN2_RTC (1ul << 2)
203+
204+
/* ACPI_PM1 RT/EC Control 1 */
205+
#define MCHP_ACPI_PM1_RT_CTRL1_REG_OFS 0x0004ul
206+
#define MCHP_ACPI_PM1_EC_CTRL1_REG_OFS 0x0104ul
207+
#define MCHP_ACPI_PM1_CTRL1_REG_MASK 0x0000ul
208+
209+
/* ACPI_PM1 RT/EC Control 2 */
210+
#define MCHP_ACPI_PM1_RT_CTRL2_REG_OFS 0x0005ul
211+
#define MCHP_ACPI_PM1_EC_CTRL2_REG_OFS 0x0105ul
212+
#define MCHP_ACPI_PM1_CTRL2_REG_MASK 0x003Eul
213+
#define MCHP_ACPI_PM1_CTRL2_PWRBTNOR_EN (1ul << 1)
214+
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_POS 2
215+
#define MCHP_ACPI_PM1_CTRL2_SLP_TYPE_MASK (0x03ul << 2)
216+
#define MCHP_ACPI_PM1_CTRL2_SLP_EN (1ul << 5)
217+
218+
/* ACPI_PM1 RT/EC Control 21 */
219+
#define MCHP_ACPI_PM1_RT_CTRL21_REG_OFS 0x0006ul
220+
#define MCHP_ACPI_PM1_EC_CTRL21_REG_OFS 0x0106ul
221+
#define MCHP_ACPI_PM1_CTRL21_REG_MASK 0x0000ul
222+
223+
/* ACPI_PM1 RT/EC Control 22 */
224+
#define MCHP_ACPI_PM1_RT_CTRL22_REG_OFS 0x0007ul
225+
#define MCHP_ACPI_PM1_EC_CTRL22_REG_OFS 0x0107ul
226+
#define MCHP_ACPI_PM1_CTRL22_REG_MASK 0x0000ul
227+
228+
/* ACPI_PM1 EC PM Status register */
229+
#define MCHP_ACPI_PM1_EC_PM_STS_REG_OFS 0x0110ul
230+
#define MCHP_ACPI_PM1_EC_PM_STS_REG_MASK 0x0001ul
231+
#define MCHP_ACPI_PM1_EC_PM_STS_SCI 0x0001ul
232+
233+
/**
234+
* @brief ACPI PM1 Registers (ACPI_PM1)
235+
*/
236+
typedef struct acpi_pm1_regs {
237+
__IOM uint8_t RT_STS1; /*!< (@ 0x0000) */
238+
__IOM uint8_t RT_STS2; /*!< (@ 0x0001) */
239+
__IOM uint8_t RT_EN1; /*!< (@ 0x0002) */
240+
__IOM uint8_t RT_EN2; /*!< (@ 0x0003) */
241+
__IOM uint8_t RT_CTRL1; /*!< (@ 0x0004) */
242+
__IOM uint8_t RT_CTRL2; /*!< (@ 0x0005) */
243+
__IOM uint8_t RT_CTRL21; /*!< (@ 0x0006) */
244+
__IOM uint8_t RT_CTRL22; /*!< (@ 0x0007) */
245+
uint8_t RSVD1[(0x100u - 0x008u)];
246+
__IOM uint8_t EC_STS1; /*!< (@ 0x0100) */
247+
__IOM uint8_t EC_STS2; /*!< (@ 0x0101) */
248+
__IOM uint8_t EC_EN1; /*!< (@ 0x0102) */
249+
__IOM uint8_t EC_EN2; /*!< (@ 0x0103) */
250+
__IOM uint8_t EC_CTRL1; /*!< (@ 0x0104) */
251+
__IOM uint8_t EC_CTRL2; /*!< (@ 0x0105) */
252+
__IOM uint8_t EC_CTRL21; /*!< (@ 0x0106) */
253+
__IOM uint8_t EC_CTRL22; /*!< (@ 0x0107) */
254+
uint8_t RSVD2[(0x0110u - 0x0108u)];
255+
__IOM uint8_t EC_PM_STS; /*!< (@ 0x0110) */
256+
uint8_t RSVD3[3];
257+
} ACPI_PM1_Type;
258+
145259
#endif /* #ifndef _ACPI_EC_H */
146260
/* end acpi_ec.h */
147261
/** @}

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