hal: renesas: rx: Fix the build warning inside SCI driver

Fix the build warning related to variable declaration

Signed-off-by: Hau Ho <hau.ho.xc@bp.renesas.com>

Author: Hau Ho

drivers/rx/README

@@ -86,6 +86,7 @@ Patch List:
    Impacted files:
       drivers/rx/rdp/src/r_bsp/mcu/rx26t/mcu_clocks.c
       drivers/rx/rdp/src/r_sci_rx/src/targets/rx26t/r_sci_rx26t.c
+      drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140.c
 
    * Remove unnecessary include header files
    Impacted files:

drivers/rx/rdp/src/r_sci_rx/src/targets/rx140/r_sci_rx140.c

@@ -113,7 +113,7 @@ R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_eri12_isr(void);
 *                 (channel range, interrupt priority, etc...)
 * Arguments    : chan -
 *                    channel to check
-* Return Value : SCI_SUCCESS - 
+* Return Value : SCI_SUCCESS -
 *                    parameter check all successfully
 *                SCI_ERR_BAD_CHAN -
 *                    channel number invalid for part
@@ -162,7 +162,7 @@ void sci_init_register(sci_hdl_t const hdl)
 
     /* SCR register initialize */
     hdl->rom->regs->SCR.BYTE = 0x00;
-    
+
         /* SSR register initialize */
         if (1 == SCI_SSR_ORER)
         {
@@ -240,18 +240,18 @@ void sci_init_register(sci_hdl_t const hdl)
 * Function Name: sci_init_bit_rate
 * Description  : This function determines the best possible settings for the
 *                baud rate registers for the specified peripheral clock speed
-*                and baud rate. Note that this does not guarantee a low bit 
+*                and baud rate. Note that this does not guarantee a low bit
 *                error rate, just the best possible one. The bit rate error is
 *                returned in .1% increments. If the hardware cannot support
 *                the specified combination, a value of 1000 (100% error) is
 *                returned.
 *
-* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled 
+* NOTE: The transmitter and receiver (TE and RE bits in SCR) must be disabled
 *       prior to calling this function.
 *
 *       The application must pause for 1 bit time after the BRR register
 *       is loaded before transmitting/receiving to allow time for the clock
-*       to settle. 
+*       to settle.
 *
 * Arguments    : hdl -
 *                    Handle for channel (ptr to chan control block)
@@ -367,7 +367,7 @@ int32_t sci_init_bit_rate(sci_hdl_t const  hdl,
     error = ( ((float)pclk / ((baud * divisor) * tmp)) - 1) * 100;
     abs_error  = (error < 0) ? (-error) : error;
 
-    if ((abs_error <= 1.0) || (SCI_MODE_ASYNC != hdl->mode))
+    if ((abs_error <= 1.0f) || (SCI_MODE_ASYNC != hdl->mode))
     {
         hdl->rom->regs->SEMR.BIT.BRME = 0;          // disable MDDR
 
@@ -399,10 +399,10 @@ int32_t sci_init_bit_rate(sci_hdl_t const  hdl,
 
 /*****************************************************************************
 * Function Name: sci_initialize_ints
-* Description  : This function sets priority, clears flags, and sets 
-*                interrupts in both the ICU and SCI peripheral. These include 
+* Description  : This function sets priority, clears flags, and sets
+*                interrupts in both the ICU and SCI peripheral. These include
 *                RXI, TXI, TEI, and ERI/GROUP12 interrupts.
-* Arguments    : hdl - 
+* Arguments    : hdl -
 *                    handle for channel (ptr to chan control block)
 *                priority -
 *                    priority for interrupts
@@ -441,15 +441,15 @@ void sci_initialize_ints(sci_hdl_t const hdl,
     /* Note: Enable interrupts after xcvr or will get "extra" interrupt */
     hdl->rom->regs->SCR.BYTE |= SCI_EN_XCVR_MASK;    // enable TE, RE, TXI, and RXI/ERI
 
-    return;    
+    return;
 } /* End of function sci_initialize_ints() */
 
 /*****************************************************************************
 * Function Name: sci_disable_ints
-* Description  : This function disable interrupts in both the ICU and SCI 
+* Description  : This function disable interrupts in both the ICU and SCI
 *                peripheral. These include RXI, TXI, TEI, ERI, and group
 *                interrupts.
-* Arguments    : hdl - 
+* Arguments    : hdl -
 *                    handle for channel (ptr to chan control block)
 * Return Value : none
 ******************************************************************************/
@@ -466,7 +466,7 @@ void sci_disable_ints(sci_hdl_t const hdl)
 
     /* Disable ICU TEI interrupt */
     DISABLE_TEI_INT;
-    
+
     /* disable peripheral interrupts and xcvr (TE and RE) */
     hdl->rom->regs->SCR.BYTE = 0;
 
@@ -576,7 +576,7 @@ R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_txi12_isr(void)
     /* set bit PSW.I = 1 to allow nested interrupt */
     R_BSP_SETPSW_I();
 #endif
-    
+
     txi_handler(&ch12_ctrl);
 } /* End of function sci12_txi12_isr() */
 #endif /* End of SCI_CFG_CH12_INCLUDED  */
@@ -684,7 +684,7 @@ R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_tei12_isr(void)
     /* set bit PSW.I = 1 to allow nested interrupt */
     R_BSP_SETPSW_I();
 #endif
-    
+
     tei_handler(&ch12_ctrl);
 } /* End of function sci12_tei12_isr() */
 #endif /* End of SCI_CFG_CH12_INCLUDED */
@@ -787,7 +787,7 @@ R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_rxi12_isr(void)
     /* set bit PSW.I = 1 to allow nested interrupt */
     R_BSP_SETPSW_I();
 #endif
-    
+
     rxi_handler(&ch12_ctrl);
 } /* End of function sci12_rxi12_isr() */
 #endif /* End of SCI_CFG_CH12_INCLUDED */
@@ -891,7 +891,7 @@ R_BSP_ATTRIB_STATIC_INTERRUPT void sci12_eri12_isr(void)
     /* set bit PSW.I = 1 to allow nested interrupt */
     R_BSP_SETPSW_I();
 #endif
-    
+
     eri_handler(&ch12_ctrl);
 } /* End of function sci12_eri12_isr() */
 #endif /* End of SCI_CFG_CH12_INCLUDED */
@@ -1086,7 +1086,7 @@ sci_err_t sci_async_cmds(sci_hdl_t const hdl,
 #endif
         }
 #endif
-            
+
             ENABLE_TXI_INT;
 
             /* NOTE: the following steps will abort anything being sent */