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jerome-pouillerjhedberg
jerome-pouiller
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jhedberg
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wiseconnect: Leave Zephyr pinctrl managing the pin-muxing
The pin-muxing does not belong to the end-drivers. It belong to the pinctrl driver. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
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‎wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/inc/sl_si91x_psram_handle.h‎

Lines changed: 2 additions & 180 deletions
Original file line numberDiff line numberDiff line change
@@ -31,188 +31,10 @@
3131
#define __SL_SI91X_PSRAM_HANDLE_H_
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#include "sl_si91x_psram.h"
34-
#include "sl_si91x_psram_pin_config.h"
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#ifdef SLI_SI91X_MCU_PSRAM_APS1604M_SQR
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#include "sl_si91x_psram_aps1604m_sqr_config.h"
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#elif defined(SLI_SI91X_MCU_PSRAM_APS6404L_SQH)
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#include "sl_si91x_psram_aps6404l_sqh_config.h"
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#else
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#include "sl_si91x_psram_aps6404l_sqrh_config.h"
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#endif
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/**
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* @file sl_si91x_psram_handle.h
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* @brief Handle for PSRAM operations and configuration.
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*/
4734

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/**
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* @brief Handle for PSRAM Operations
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*/
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extern struct sl_psram_info_type_t PSRAM_Device;
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/**
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* @addtogroup PSRAM_GPIO_PIN_SET PSRAM GPIO Pin Sets
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* @ingroup PSRAM
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* @{
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*/
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#define PSRAM_GPIO_PIN_SET_52_TO_57 1 /**< GPIO Pin Set 52 to 57 */
59-
#define PSRAM_GPIO_PIN_SET_0_TO_5 2 /**< GPIO Pin Set 0 to 5 */
60-
#define PSRAM_GPIO_PIN_SET_46_TO_51_CS_0 3 /**< GPIO Pin Set 46 to 51 with Chip Select 0 */
61-
#define PSRAM_GPIO_PIN_SET_46_TO_51_CS_1 4 /**< GPIO Pin Set 46 to 51 with Chip Select 1 */
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#define PSRAM_GPIO_PIN_SET_46_TO_57_CS_0 5 /**< GPIO Pin Set 46 to 57 with Chip Select 0 */
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#define PSRAM_GPIO_PIN_SET_46_TO_57_CS_1 6 /**< GPIO Pin Set 46 to 57 with Chip Select 1 */
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/// @} end group PSRAM_GPIO_PIN_SET
65-
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/**
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* @addtogroup PSRAM_PIN_CONFIG PSRAM Pin Configuration
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* @ingroup PSRAM
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* @{
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*/
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#if (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_0_TO_5)
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#define M4SS_PSRAM_CLK_PORT (0) /**< Clock Port for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CLK_PIN (0) /**< Clock Pin for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CLK_MUX (2) /**< Clock Mux for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CLK_PAD (0) /**< Clock Pad for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CSN_PORT (0) /**< Chip Select Port for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CSN_PIN (1) /**< Chip Select Pin for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CSN_MUX (2) /**< Chip Select Mux for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_CSN_PAD (0) /**< Chip Select Pad for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D0_PORT (0) /**< Data 0 Port for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D0_PIN (2) /**< Data 0 Pin for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D0_MUX (2) /**< Data 0 Mux for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D0_PAD (0) /**< Data 0 Pad for GPIO Pin Set 0 to 5 */
87-
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#define M4SS_PSRAM_D1_PORT (0) /**< Data 1 Port for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D1_PIN (3) /**< Data 1 Pin for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D1_MUX (2) /**< Data 1 Mux for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D1_PAD (0) /**< Data 1 Pad for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D2_PORT (0) /**< Data 2 Port for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D2_PIN (4) /**< Data 2 Pin for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D2_MUX (2) /**< Data 2 Mux for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D2_PAD (0) /**< Data 2 Pad for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D3_PORT (0) /**< Data 3 Port for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D3_PIN (5) /**< Data 3 Pin for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D3_MUX (2) /**< Data 3 Mux for GPIO Pin Set 0 to 5 */
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#define M4SS_PSRAM_D3_PAD (0) /**< Data 3 Pad for GPIO Pin Set 0 to 5 */
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#define NUM_OF_PSRAM_PINS (6) /**< Number of PSRAM Pins for GPIO Pin Set 0 to 5 */
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#elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_0) \
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|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_1) \
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|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_0) \
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|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_1)
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#define M4SS_PSRAM_CLK_PORT (2) /**< Clock Port for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_CLK_PIN (14) /**< Clock Pin for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_CLK_MUX (11) /**< Clock Mux for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_CLK_PAD (10) /**< Clock Pad for GPIO Pin Set 46 to 57 */
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#if (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_0) \
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|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_0)
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#define M4SS_PSRAM_CSN_PORT (3) /**< Chip Select Port for GPIO Pin Set 46 to 51 with CS 0 */
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#define M4SS_PSRAM_CSN_PIN (01) /**< Chip Select Pin for GPIO Pin Set 46 to 51 with CS 0 */
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#define M4SS_PSRAM_CSN_MUX (11) /**< Chip Select Mux for GPIO Pin Set 46 to 51 with CS 0 */
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#define M4SS_PSRAM_CSN_PAD (13) /**< Chip Select Pad for GPIO Pin Set 46 to 51 with CS 0 */
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#elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_1) \
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|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_1)
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#define M4SS_PSRAM_CSN_PORT (3) /**< Chip Select Port for GPIO Pin Set 46 to 51 with CS 1 */
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#define M4SS_PSRAM_CSN_PIN (05) /**< Chip Select Pin for GPIO Pin Set 46 to 51 with CS 1 */
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#define M4SS_PSRAM_CSN_MUX (11) /**< Chip Select Mux for GPIO Pin Set 46 to 51 with CS 1 */
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#define M4SS_PSRAM_CSN_PAD (17) /**< Chip Select Pad for GPIO Pin Set 46 to 51 with CS 1 */
127-
#endif
128-
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#define M4SS_PSRAM_D0_PORT (2) /**< Data 0 Port for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D0_PIN (15) /**< Data 0 Pin for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D0_MUX (11) /**< Data 0 Mux for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D0_PAD (11) /**< Data 0 Pad for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D1_PORT (3) /**< Data 1 Port for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D1_PIN (0) /**< Data 1 Pin for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D1_MUX (11) /**< Data 1 Mux for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D1_PAD (12) /**< Data 1 Pad for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D2_PORT (3) /**< Data 2 Port for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D2_PIN (2) /**< Data 2 Pin for GPIO Pin Set 46 to 57 */
141-
#define M4SS_PSRAM_D2_MUX (11) /**< Data 2 Mux for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D2_PAD (14) /**< Data 2 Pad for GPIO Pin Set 46 to 57 */
143-
144-
#define M4SS_PSRAM_D3_PORT (3) /**< Data 3 Port for GPIO Pin Set 46 to 57 */
145-
#define M4SS_PSRAM_D3_PIN (3) /**< Data 3 Pin for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D3_MUX (11) /**< Data 3 Mux for GPIO Pin Set 46 to 57 */
147-
#define M4SS_PSRAM_D3_PAD (15) /**< Data 3 Pad for GPIO Pin Set 46 to 57 */
148-
149-
#if (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_0) \
150-
|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_1)
151-
152-
#define M4SS_PSRAM_D4_PORT (3) /**< Data 4 Port for GPIO Pin Set 46 to 57 */
153-
#define M4SS_PSRAM_D4_PIN (6) /**< Data 4 Pin for GPIO Pin Set 46 to 57 */
154-
#define M4SS_PSRAM_D4_MUX (11) /**< Data 4 Mux for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D4_PAD (11) /**< Data 4 Pad for GPIO Pin Set 46 to 57 */
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157-
#define M4SS_PSRAM_D5_PORT (3) /**< Data 5 Port for GPIO Pin Set 46 to 57 */
158-
#define M4SS_PSRAM_D5_PIN (7) /**< Data 5 Pin for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D5_MUX (11) /**< Data 5 Mux for GPIO Pin Set 46 to 57 */
160-
#define M4SS_PSRAM_D5_PAD (12) /**< Data 5 Pad for GPIO Pin Set 46 to 57 */
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162-
#define M4SS_PSRAM_D6_PORT (3) /**< Data 6 Port for GPIO Pin Set 46 to 57 */
163-
#define M4SS_PSRAM_D6_PIN (8) /**< Data 6 Pin for GPIO Pin Set 46 to 57 */
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#define M4SS_PSRAM_D6_MUX (11) /**< Data 6 Mux for GPIO Pin Set 46 to 57 */
165-
#define M4SS_PSRAM_D6_PAD (14) /**< Data 6 Pad for GPIO Pin Set 46 to 57 */
166-
167-
#define M4SS_PSRAM_D7_PORT (3) /**< Data 7 Port for GPIO Pin Set 46 to 57 */
168-
#define M4SS_PSRAM_D7_PIN (9) /**< Data 7 Pin for GPIO Pin Set 46 to 57 */
169-
#define M4SS_PSRAM_D7_MUX (11) /**< Data 7 Mux for GPIO Pin Set 46 to 57 */
170-
#define M4SS_PSRAM_D7_PAD (15) /**< Data 7 Pad for GPIO Pin Set 46 to 57 */
171-
172-
#endif
173-
174-
#if (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_0) \
175-
|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_51_CS_1)
176-
#define NUM_OF_PSRAM_PINS (6) /**< Number of PSRAM Pins for GPIO Pin Set 46 to 51 */
177-
#else
178-
#define NUM_OF_PSRAM_PINS (10) /**< Number of PSRAM Pins for GPIO Pin Set 46 to 57 */
179-
#endif
180-
181-
#elif (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_52_TO_57)
182-
183-
#define M4SS_PSRAM_CLK_PORT (3) /**< Clock Port for GPIO Pin Set 52 to 57 */
184-
#define M4SS_PSRAM_CLK_PIN (4) /**< Clock Pin for GPIO Pin Set 52 to 57 */
185-
#define M4SS_PSRAM_CLK_MUX (12) /**< Clock Mux for GPIO Pin Set 52 to 57 */
186-
#define M4SS_PSRAM_CLK_PAD (16) /**< Clock Pad for GPIO Pin Set 52 to 57 */
187-
188-
#define M4SS_PSRAM_CSN_PORT (3) /**< Chip Select Port for GPIO Pin Set 52 to 57 */
189-
#define M4SS_PSRAM_CSN_PIN (7) /**< Chip Select Pin for GPIO Pin Set 52 to 57 */
190-
#define M4SS_PSRAM_CSN_MUX (12) /**< Chip Select Mux for GPIO Pin Set 52 to 57 */
191-
#define M4SS_PSRAM_CSN_PAD (19) /**< Chip Select Pad for GPIO Pin Set 52 to 57 */
192-
193-
#define M4SS_PSRAM_D0_PORT (3) /**< Data 0 Port for GPIO Pin Set 52 to 57 */
194-
#define M4SS_PSRAM_D0_PIN (5) /**< Data 0 Pin for GPIO Pin Set 52 to 57 */
195-
#define M4SS_PSRAM_D0_MUX (12) /**< Data 0 Mux for GPIO Pin Set 52 to 57 */
196-
#define M4SS_PSRAM_D0_PAD (17) /**< Data 0 Pad for GPIO Pin Set 52 to 57 */
197-
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#define M4SS_PSRAM_D1_PORT (3) /**< Data 1 Port for GPIO Pin Set 52 to 57 */
199-
#define M4SS_PSRAM_D1_PIN (6) /**< Data 1 Pin for GPIO Pin Set 52 to 57 */
200-
#define M4SS_PSRAM_D1_MUX (12) /**< Data 1 Mux for GPIO Pin Set 52 to 57 */
201-
#define M4SS_PSRAM_D1_PAD (18) /**< Data 1 Pad for GPIO Pin Set 52 to 57 */
202-
203-
#define M4SS_PSRAM_D2_PORT (3) /**< Data 2 Port for GPIO Pin Set 52 to 57 */
204-
#define M4SS_PSRAM_D2_PIN (8) /**< Data 2 Pin for GPIO Pin Set 52 to 57 */
205-
#define M4SS_PSRAM_D2_MUX (12) /**< Data 2 Mux for GPIO Pin Set 52 to 57 */
206-
#define M4SS_PSRAM_D2_PAD (20) /**< Data 2 Pad for GPIO Pin Set 52 to 57 */
207-
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#define M4SS_PSRAM_D3_PORT (3) /**< Data 3 Port for GPIO Pin Set 52 to 57 */
209-
#define M4SS_PSRAM_D3_PIN (9) /**< Data 3 Pin for GPIO Pin Set 52 to 57 */
210-
#define M4SS_PSRAM_D3_MUX (12) /**< Data 3 Mux for GPIO Pin Set 52 to 57 */
211-
#define M4SS_PSRAM_D3_PAD (21) /**< Data 3 Pad for GPIO Pin Set 52 to 57 */
212-
213-
#define NUM_OF_PSRAM_PINS (6) /**< Number of PSRAM Pins for GPIO Pin Set 52 to 57 */
37+
/* Pinctrl is managed by Zephyr. Disable pinctrl in the HAL driver */
38+
#define NUM_OF_PSRAM_PINS 0
21439

21540
#endif
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/// @} end group PSRAM_PIN_CONFIG
217-
218-
#endif //__SL_SI91X_PSRAM_HANDLE_H_

‎wiseconnect/components/device/silabs/si91x/mcu/drivers/unified_api/src/sl_si91x_psram.c‎

Lines changed: 0 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -117,19 +117,6 @@ static struct PSRAMStatusType PSRAMStatus = {
117117
};
118118

119119
struct PSRAMPinConfigType PSRAMPinConfig[NUM_OF_PSRAM_PINS] = {
120-
{ M4SS_PSRAM_CLK_PORT, M4SS_PSRAM_CLK_PIN, M4SS_PSRAM_CLK_MUX, M4SS_PSRAM_CLK_PAD },
121-
{ M4SS_PSRAM_CSN_PORT, M4SS_PSRAM_CSN_PIN, M4SS_PSRAM_CSN_MUX, M4SS_PSRAM_CSN_PAD },
122-
{ M4SS_PSRAM_D0_PORT, M4SS_PSRAM_D0_PIN, M4SS_PSRAM_D0_MUX, M4SS_PSRAM_D0_PAD },
123-
{ M4SS_PSRAM_D1_PORT, M4SS_PSRAM_D1_PIN, M4SS_PSRAM_D1_MUX, M4SS_PSRAM_D1_PAD },
124-
{ M4SS_PSRAM_D2_PORT, M4SS_PSRAM_D2_PIN, M4SS_PSRAM_D2_MUX, M4SS_PSRAM_D2_PAD },
125-
{ M4SS_PSRAM_D3_PORT, M4SS_PSRAM_D3_PIN, M4SS_PSRAM_D3_MUX, M4SS_PSRAM_D3_PAD },
126-
#if (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_0) \
127-
|| (PSRAM_GPIO_PIN_SET_SEL == PSRAM_GPIO_PIN_SET_46_TO_57_CS_1)
128-
{ M4SS_PSRAM_D4_PORT, M4SS_PSRAM_D4_PIN, M4SS_PSRAM_D4_MUX, M4SS_PSRAM_D4_PAD },
129-
{ M4SS_PSRAM_D5_PORT, M4SS_PSRAM_D5_PIN, M4SS_PSRAM_D5_MUX, M4SS_PSRAM_D5_PAD },
130-
{ M4SS_PSRAM_D6_PORT, M4SS_PSRAM_D6_PIN, M4SS_PSRAM_D6_MUX, M4SS_PSRAM_D6_PAD },
131-
{ M4SS_PSRAM_D7_PORT, M4SS_PSRAM_D7_PIN, M4SS_PSRAM_D7_MUX, M4SS_PSRAM_D7_PAD },
132-
#endif
133120
};
134121

135122
/// DMA descriptors must be aligned to 16 bytes

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