Skip to content

Commit 681cf6d

Browse files
erwangolaurenmurphyx64
erwango
authored and
laurenmurphyx64
committed
dts: stm32: Configure SDMMC 48MHz domain clock
Provide SDMMC domain clock, when required (because it is common)use the same as the one selected by USB and RNG. Otherwise, when available use HSI48, otherwise use the most handy (MSI, sysclk ...). PLLSAI is not used as not implemented for now. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
1 parent 51cac9e commit 681cf6d

File tree

11 files changed

+38
-10
lines changed

11 files changed

+38
-10
lines changed

‎dts/arm/st/f4/stm32f4.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -536,7 +536,8 @@
536536
sdmmc1: sdmmc@40012c00 {
537537
compatible = "st,stm32-sdmmc";
538538
reg = <0x40012c00 0x400>;
539-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
539+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
540+
<&rcc STM32_SRC_PLL_Q NO_SEL>;
540541
resets = <&rctl STM32_RESET(APB2, 11U)>;
541542
interrupts = <49 0>;
542543
status = "disabled";

‎dts/arm/st/f4/stm32f412.dtsi‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -180,6 +180,11 @@
180180
num-bidir-endpoints = <6>;
181181
};
182182

183+
sdmmc1: sdmmc@40012c00 {
184+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
185+
<&rcc STM32_SRC_SYSCLK SDIO_SEL(1)>;
186+
};
187+
183188
quadspi: quadspi@a0001000 {
184189
compatible = "st,stm32-qspi";
185190
#address-cells = <0x1>;

‎dts/arm/st/f4/stm32f469.dtsi‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,11 @@
88

99
/ {
1010
soc {
11+
sdmmc1: sdmmc@40012c00 {
12+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
13+
<&rcc STM32_SRC_SYSCLK SDMMC_SEL(1)>;
14+
};
15+
1116
usbotg_fs: usb@50000000 {
1217
num-bidir-endpoints = <6>;
1318
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000080>,

‎dts/arm/st/f7/stm32f7.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -732,7 +732,8 @@
732732
sdmmc1: sdmmc@40012c00 {
733733
compatible = "st,stm32-sdmmc";
734734
reg = <0x40012c00 0x400>;
735-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>;
735+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000800>,
736+
<&rcc STM32_SRC_PLL_Q SDMMC1_SEL(0)>;
736737
resets = <&rctl STM32_RESET(APB2, 11U)>;
737738
interrupts = <49 0>;
738739
status = "disabled";

‎dts/arm/st/f7/stm32f723.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,8 @@
4141
sdmmc2: sdmmc@40011c00 {
4242
compatible = "st,stm32-sdmmc";
4343
reg = <0x40011c00 0x400>;
44-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
44+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
45+
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
4546
resets = <&rctl STM32_RESET(APB2, 7U)>;
4647
interrupts = <103 0>;
4748
status = "disabled";

‎dts/arm/st/f7/stm32f767.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,7 +82,8 @@
8282
sdmmc2: sdmmc@40011c00 {
8383
compatible = "st,stm32-sdmmc";
8484
reg = <0x40011c00 0x400>;
85-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>;
85+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000080>,
86+
<&rcc STM32_SRC_PLL_Q SDMMC2_SEL(0)>;
8687
resets = <&rctl STM32_RESET(APB2, 7U)>;
8788
interrupts = <103 0>;
8889
status = "disabled";

‎dts/arm/st/h7/stm32h7.dtsi‎

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -823,7 +823,8 @@
823823
sdmmc1: sdmmc@52007000 {
824824
compatible = "st,stm32-sdmmc";
825825
reg = <0x52007000 0x400>;
826-
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>;
826+
clocks = <&rcc STM32_CLOCK_BUS_AHB3 0x00010000>,
827+
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
827828
resets = <&rctl STM32_RESET(AHB3, 16U)>;
828829
interrupts = <49 0>;
829830
status = "disabled";
@@ -832,7 +833,8 @@
832833
sdmmc2: sdmmc@48022400 {
833834
compatible = "st,stm32-sdmmc";
834835
reg = <0x48022400 0x400>;
835-
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>;
836+
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x00000100>,
837+
<&rcc STM32_SRC_HSI48 SDMMC_SEL(0)>;
836838
resets = <&rctl STM32_RESET(AHB2, 8U)>;
837839
interrupts = <124 0>;
838840
status = "disabled";

‎dts/arm/st/l4/stm32l431.dtsi‎

Lines changed: 10 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,6 +8,14 @@
88

99
/ {
1010
soc {
11+
clocks {
12+
clk_hsi48: clk-hsi48 {
13+
#clock-cells = <0>;
14+
compatible = "fixed-clock";
15+
clock-frequency = <DT_FREQ_M(48)>;
16+
status = "disabled";
17+
};
18+
};
1119

1220
pinctrl: pin-controller@48000000 {
1321

@@ -111,7 +119,8 @@
111119
sdmmc1: sdmmc@40012800 {
112120
compatible = "st,stm32-sdmmc";
113121
reg = <0x40012800 0x400>;
114-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
122+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
123+
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
115124
interrupts = <49 0>;
116125
status = "disabled";
117126
};

‎dts/arm/st/l4/stm32l471.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -237,7 +237,8 @@
237237
sdmmc1: sdmmc@40012800 {
238238
compatible = "st,stm32-sdmmc";
239239
reg = <0x40012800 0x400>;
240-
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>;
240+
clocks = <&rcc STM32_CLOCK_BUS_APB2 0x00000400>,
241+
<&rcc STM32_SRC_MSI CLK48_SEL(3)>;
241242
resets = <&rctl STM32_RESET(APB2, 10U)>;
242243
interrupts = <49 0>;
243244
status = "disabled";

‎dts/arm/st/l4/stm32l4r5.dtsi‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -320,7 +320,8 @@
320320
sdmmc1: sdmmc@50062400 {
321321
compatible = "st,stm32-sdmmc";
322322
reg = <0x50062400 0x400>;
323-
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>;
323+
clocks = <&rcc STM32_CLOCK_BUS_AHB2 0x400000>,
324+
<&rcc STM32_SRC_HSI48 CLK48_SEL(0)>;
324325
resets = <&rctl STM32_RESET(AHB2, 22U)>;
325326
interrupts = <49 0>;
326327
status = "disabled";

0 commit comments

Comments
 (0)