drivers: clock: ccm_rev2: add imx93 common clocks set support

Setup most clocks with common_clock_set_freq().
PLL and mux are preset.

Signed-off-by: Winteri Wang <dongjie.wang@nxp.com>

Author: WinteriWang

drivers/clock_control/clock_control_mcux_ccm_rev2.c

@@ -9,6 +9,9 @@
 #include <zephyr/drivers/clock_control.h>
 #include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
 #include <fsl_clock.h>
+#if defined(CONFIG_SOC_MIMX9352)
+#include <soc.h>
+#endif
 
 #define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
 #include <zephyr/logging/log.h>
@@ -182,6 +185,27 @@ static int mcux_ccm_get_subsys_rate(const struct device *dev,
 		break;
 #endif
 
+#if defined(CONFIG_SOC_MIMX9352)
+	case IMX_CCM_MEDIA_AXI_CLK:
+		clock_root = kCLOCK_Root_MediaAxi;
+		break;
+	case IMX_CCM_MEDIA_APB_CLK:
+		clock_root = kCLOCK_Root_MediaApb;
+		break;
+	case IMX_CCM_MEDIA_DISP_PIX_CLK:
+		clock_root = kCLOCK_Root_MediaDispPix;
+		break;
+	case IMX_CCM_MEDIA_LDB_CLK:
+		clock_root = kCLOCK_Root_MediaLdb;
+		break;
+	case IMX_CCM_MIPI_PHY_CFG_CLK:
+		clock_root = kCLOCK_Root_MipiPhyCfg;
+		break;
+	case IMX_CCM_CAM_PIX_CLK:
+		clock_root = kCLOCK_Root_CamPix;
+		break;
+#endif
+
 #if defined(CONFIG_SOC_MIMX9352) && defined(CONFIG_DAI_NXP_SAI)
 	case IMX_CCM_SAI1_CLK:
 	case IMX_CCM_SAI2_CLK:
@@ -372,6 +396,16 @@ static int CCM_SET_FUNC_ATTR mcux_ccm_set_subsys_rate(const struct device *dev,
 		return mipi_csi2rx_clock_set_freq(kCLOCK_Root_Csi2_Esc, clock_rate);
 #endif
 
+#if defined(CONFIG_SOC_MIMX9352)
+	case IMX_CCM_MEDIA_AXI_CLK:
+	case IMX_CCM_MEDIA_APB_CLK:
+	case IMX_CCM_MEDIA_DISP_PIX_CLK:
+	case IMX_CCM_MEDIA_LDB_CLK:
+	case IMX_CCM_MIPI_PHY_CFG_CLK:
+	case IMX_CCM_CAM_PIX_CLK:
+		return common_clock_set_freq(clock_name, (uint32_t)clock_rate);
+#endif
+
 	default:
 		/* Silence unused variable warning */
 		ARG_UNUSED(clock_rate);

include/zephyr/dt-bindings/clock/imx_ccm_rev2.h

@@ -166,4 +166,12 @@
 #define IMX_CCM_QTMR3_CLK              0x6002UL
 #define IMX_CCM_QTMR4_CLK              0x6003UL
 
+/* MEDIA */
+#define IMX_CCM_MEDIA_AXI_CLK          0x3000UL
+#define IMX_CCM_MEDIA_APB_CLK          0x3100UL
+#define IMX_CCM_MEDIA_DISP_PIX_CLK     0x3200UL
+#define IMX_CCM_MEDIA_LDB_CLK          0x3300UL
+#define IMX_CCM_MIPI_PHY_CFG_CLK       0x3400UL
+#define IMX_CCM_CAM_PIX_CLK            0x3500UL
+
 #endif /* ZEPHYR_INCLUDE_DT_BINDINGS_CLOCK_IMX_CCM_REV2_H_ */

soc/nxp/imx/imx9/imx93/CMakeLists.txt

@@ -5,6 +5,7 @@ if(CONFIG_SOC_MIMX9352_A55)
   zephyr_include_directories(a55)
 
   zephyr_sources_ifdef(CONFIG_ARM_MMU a55/mmu_regions.c)
+  zephyr_sources(common_clock_set.c)
 
   set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm64/scripts/linker.ld CACHE INTERNAL "")
 elseif(CONFIG_SOC_MIMX9352_M33)

soc/nxp/imx/imx9/imx93/a55/soc.h

@@ -7,5 +7,6 @@
 #ifndef _SOC_NXP_IMX_IMX93_A55_SOC_H_
 #define _SOC_NXP_IMX_IMX93_A55_SOC_H_
 
+uint32_t common_clock_set_freq(uint32_t clock_name, uint32_t rate);
 
 #endif /* _SOC_NXP_IMX_IMX93_A55_SOC_H_ */

soc/nxp/imx/imx9/imx93/common_clock_set.c

@@ -0,0 +1,81 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <fsl_clock.h>
+#include <soc.h>
+#include <errno.h>
+#include <zephyr/irq.h>
+#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_REGISTER(imx93_common_clock_set, CONFIG_SOC_LOG_LEVEL);
+
+uint32_t common_clock_set_freq(uint32_t clock_name, uint32_t rate)
+{
+	clock_name_t root;
+	uint32_t root_rate;
+	clock_root_t clk_root;
+	clock_lpcg_t clk_gate;
+	uint32_t divider;
+
+	switch (clock_name) {
+	case IMX_CCM_MEDIA_AXI_CLK:
+		clk_root = kCLOCK_Root_MediaAxi;
+		clk_gate = kCLOCK_IpInvalid;
+		CLOCK_SetRootClockMux(kCLOCK_Root_MediaAxi,
+				      kCLOCK_MEDIAAXI_ClockRoot_MuxSysPll1Pfd1);
+		break;
+	case IMX_CCM_MEDIA_APB_CLK:
+		clk_root = kCLOCK_Root_MediaApb;
+		clk_gate = kCLOCK_IpInvalid;
+		CLOCK_SetRootClockMux(kCLOCK_Root_MediaApb,
+				      kCLOCK_MEDIAAPB_ClockRoot_MuxSysPll1Pfd1Div2);
+		break;
+	case IMX_CCM_MEDIA_DISP_PIX_CLK:
+		clk_root = kCLOCK_Root_MediaDispPix;
+		clk_gate = kCLOCK_Lcdif;
+		CLOCK_SetRootClockMux(kCLOCK_Root_MediaDispPix,
+				      kCLOCK_MEDIADISPPIX_ClockRoot_MuxVideoPll1Out);
+		break;
+	case IMX_CCM_MEDIA_LDB_CLK:
+		clk_root = kCLOCK_Root_MediaLdb;
+		clk_gate = kCLOCK_Lvds;
+		CLOCK_SetRootClockMux(kCLOCK_Root_MediaLdb,
+				      kCLOCK_MEDIALDB_ClockRoot_MuxVideoPll1Out);
+		break;
+	case IMX_CCM_MIPI_PHY_CFG_CLK:
+		clk_root = kCLOCK_Root_MipiPhyCfg;
+		clk_gate = kCLOCK_Mipi_Dsi;
+		break;
+	case IMX_CCM_CAM_PIX_CLK:
+		clk_root = kCLOCK_Root_CamPix;
+		clk_gate = kCLOCK_Mipi_Csi;
+		CLOCK_SetRootClockMux(kCLOCK_Root_CamPix,
+				      kCLOCK_MEDIALDB_ClockRoot_MuxVideoPll1Out);
+		break;
+	default:
+		return -ENOTSUP;
+	}
+
+	root = CLOCK_GetRootClockSource(clk_root, CLOCK_GetRootClockMux(clk_root));
+	root_rate = g_clockSourceFreq[root];
+	divider = ((root_rate + (rate - 1)) / rate);
+
+	LOG_DBG("clock_name: 0x%x, root_rate: %d, divider: %d", clock_name, root_rate, divider);
+
+	if (clk_gate < kCLOCK_IpInvalid) {
+		CLOCK_DisableClock(clk_gate);
+	}
+
+	CLOCK_SetRootClockDiv(clk_root, divider);
+	CLOCK_PowerOnRootClock(clk_root);
+
+	if (clk_gate < kCLOCK_IpInvalid) {
+		CLOCK_EnableClock(clk_gate);
+	}
+
+	return 0;
+}