drivers! flash: stm32 xspi driver can read and write in mem map mode

Author: FRASTM

drivers/flash/flash_stm32_xspi.c

@@ -840,21 +840,22 @@ static int stm32_xspi_mem_reset(const struct device *dev)
 
 #ifdef CONFIG_STM32_MEMMAP
 /* Function to configure the octoflash in MemoryMapped mode for writing and reading */
-static int stm32_xspi_set_memorymap(const struct device *dev)
+static int stm32_xspi_set_memorymap(const struct device *dev, bool memmap_wr)
 {
 	HAL_StatusTypeDef ret;
 	const struct flash_stm32_xspi_config *dev_cfg = dev->config;
 	struct flash_stm32_xspi_data *dev_data = dev->data;
-	XSPI_RegularCmdTypeDef s_command = {0}; /* Non-zero values disturb the command */
+	XSPI_RegularCmdTypeDef s_command = xspi_prepare_cmd(dev_cfg->data_mode, dev_cfg->data_rate);
 	XSPI_MemoryMappedTypeDef s_MemMappedCfg;
 
 	/* Configure octoflash in MemoryMapped mode */
 	if ((dev_cfg->data_mode == XSPI_SPI_MODE) &&
 		(stm32_xspi_hal_address_size(dev) == HAL_XSPI_ADDRESS_24_BITS)) {
 		/* OPI mode and 3-bytes address size not supported by memory */
 		LOG_ERR("XSPI_SPI_MODE in 3Bytes addressing is not supported");
-		return -EIO;
+		return -ENOTSUP;
 	}
+
 	/* Enable write operation */
 	ret = stm32_xspi_write_enable(dev,
 		dev_cfg->data_mode, dev_cfg->data_rate);
@@ -865,94 +866,129 @@ static int stm32_xspi_set_memorymap(const struct device *dev)
 
 	/* Initialize the program command */
 	s_command.OperationType = HAL_XSPI_OPTYPE_WRITE_CFG;
-	if (dev_cfg->data_rate == XSPI_STR_TRANSFER) {
-		s_command.Instruction = (dev_cfg->data_mode == XSPI_SPI_MODE)
-					? ((stm32_xspi_hal_address_size(dev) ==
-					HAL_XSPI_ADDRESS_24_BITS)
-						? SPI_NOR_CMD_PP
-						: SPI_NOR_CMD_PP_4B)
-					: SPI_NOR_OCMD_PAGE_PRG;
-	} else {
-		s_command.Instruction = SPI_NOR_OCMD_PAGE_PRG;
-	}
-	s_command.InstructionMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? ((dev_cfg->data_mode == XSPI_SPI_MODE)
-					? HAL_XSPI_INSTRUCTION_1_LINE
-					: HAL_XSPI_INSTRUCTION_8_LINES)
-				: HAL_XSPI_INSTRUCTION_8_LINES;
-	s_command.InstructionDTRMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? HAL_XSPI_INSTRUCTION_DTR_DISABLE
-				: HAL_XSPI_INSTRUCTION_DTR_ENABLE;
+	s_command.Instruction = dev_data->write_opcode; /* Expecting SPI_NOR_OCMD_PAGE_PRG */
 	s_command.InstructionWidth = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
 				? ((dev_cfg->data_mode == XSPI_SPI_MODE)
 					? HAL_XSPI_INSTRUCTION_8_BITS
 					: HAL_XSPI_INSTRUCTION_16_BITS)
 				: HAL_XSPI_INSTRUCTION_16_BITS;
-	s_command.AddressMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? ((dev_cfg->data_mode == XSPI_SPI_MODE)
-					? HAL_XSPI_ADDRESS_1_LINE
-					: HAL_XSPI_ADDRESS_8_LINES)
-				: HAL_XSPI_ADDRESS_8_LINES;
-	s_command.AddressDTRMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? HAL_XSPI_ADDRESS_DTR_DISABLE
-				: HAL_XSPI_ADDRESS_DTR_ENABLE;
 	s_command.AddressWidth = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
 				? stm32_xspi_hal_address_size(dev)
 				: HAL_XSPI_ADDRESS_32_BITS;
-	s_command.DataMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? ((dev_cfg->data_mode == XSPI_SPI_MODE)
-					? HAL_XSPI_DATA_1_LINE
-					: HAL_XSPI_DATA_8_LINES)
-				: HAL_XSPI_DATA_8_LINES;
-	s_command.DataDTRMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? HAL_XSPI_DATA_DTR_DISABLE
-				: HAL_XSPI_DATA_DTR_ENABLE;
-	s_command.DQSMode = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? HAL_XSPI_DQS_DISABLE
-				: HAL_XSPI_DQS_ENABLE;
-#ifdef XSPI_CCR_SIOO
-	s_command.SIOOMode = HAL_XSPI_SIOO_INST_EVERY_CMD;
-#endif /* XSPI_CCR_SIOO */
+	s_command.DummyCycles = 0U;
+	/* Adapt lines based on write opcode */
+	switch (s_command.Instruction) {
+		case SPI_NOR_CMD_PP_4B:
+			__fallthrough;
+		case SPI_NOR_CMD_PP:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
+			s_command.DataMode = HAL_XSPI_DATA_1_LINE;
+			break;
+		case SPI_NOR_CMD_PP_1_1_2:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
+			s_command.DataMode = HAL_XSPI_DATA_2_LINES;
+			break;
+		case SPI_NOR_CMD_PP_1_1_4_4B:
+			__fallthrough;
+		case SPI_NOR_CMD_PP_1_1_4:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
+			s_command.DataMode = HAL_XSPI_DATA_4_LINES;
+			break;
+		case SPI_NOR_CMD_PP_1_4_4_4B:
+			__fallthrough;
+		case SPI_NOR_CMD_PP_1_4_4:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_4_LINES;
+			s_command.DataMode = HAL_XSPI_DATA_4_LINES;
+			break;
+		default:
+			/* Use lines based on data_mode set in ospi_prepare_cmd */
+			break;
+		}
 
 	ret = HAL_XSPI_Command(&dev_data->hxspi, &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
 	if (ret != HAL_OK) {
 		LOG_ERR("%d: Failed to set memory map wr", ret);
 		return -EIO;
 	}
 
-	/* Initialize the read command */
 	s_command.OperationType = HAL_XSPI_OPTYPE_READ_CFG;
-	s_command.Instruction = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? ((dev_cfg->data_mode == XSPI_SPI_MODE)
-					? ((stm32_xspi_hal_address_size(dev) ==
-					HAL_XSPI_ADDRESS_24_BITS)
-						? SPI_NOR_CMD_READ_FAST
-						: SPI_NOR_CMD_READ_FAST_4B)
-					: dev_data->read_opcode)
-				: SPI_NOR_OCMD_DTR_RD;
-	s_command.DummyCycles = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
-				? ((dev_cfg->data_mode == XSPI_SPI_MODE)
-					? SPI_NOR_DUMMY_RD
-					: SPI_NOR_DUMMY_RD_OCTAL)
-				: SPI_NOR_DUMMY_RD_OCTAL_DTR;
+	s_command.AddressWidth = (dev_cfg->data_rate == XSPI_STR_TRANSFER)
+				? stm32_xspi_hal_address_size(dev)
+				: HAL_XSPI_ADDRESS_32_BITS;
 	s_command.DQSMode = HAL_XSPI_DQS_DISABLE;
 
+	/* Adapt lines based on read_mode */
+	if (dev_cfg->data_mode != XSPI_OCTO_MODE) {
+		switch (dev_data->read_mode) {
+		case JESD216_MODE_112:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
+			s_command.DataMode = HAL_XSPI_DATA_2_LINES;
+			break;
+		case JESD216_MODE_122:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_2_LINES;
+			s_command.DataMode = HAL_XSPI_DATA_2_LINES;
+			break;
+		case JESD216_MODE_114:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_1_LINE;
+			s_command.DataMode = HAL_XSPI_DATA_4_LINES;
+			break;
+		case JESD216_MODE_144:
+			s_command.InstructionMode = HAL_XSPI_INSTRUCTION_1_LINE;
+			s_command.AddressMode = HAL_XSPI_ADDRESS_4_LINES;
+			s_command.DataMode = HAL_XSPI_DATA_4_LINES;
+			break;
+		default:
+			/* Use lines based on data_mode set in ospi_prepare_cmd */
+			break;
+		}
+	}
+
+	/* Set instruction and dummy cycles parameters */
+	if (dev_cfg->data_rate == XSPI_DTR_TRANSFER) {
+		/* DTR transfer rate (==> Octal mode) */
+		s_command.Instruction = SPI_NOR_OCMD_DTR_RD;
+		s_command.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL_DTR;
+	} else {
+		/* STR transfer rate */
+		if (dev_cfg->data_mode == XSPI_OCTO_MODE) {
+			/* OPI and STR */
+			s_command.Instruction = SPI_NOR_OCMD_RD;
+			s_command.DummyCycles = SPI_NOR_DUMMY_RD_OCTAL;
+		} else {
+			/* use SFDP:BFP read instruction */
+			s_command.Instruction = dev_data->read_opcode;
+			s_command.DummyCycles = dev_data->read_dummy;
+		}
+	}
+
 	ret = HAL_XSPI_Command(&dev_data->hxspi, &s_command, HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
 	if (ret != HAL_OK) {
 		LOG_ERR("%d: Failed to set memory map rd", ret);
 		return -EIO;
 	}
 
 	/* Enable the memory-mapping */
+	if (memmap_wr) {
 	s_MemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_ENABLE;
-	s_MemMappedCfg.TimeoutPeriodClock = 0x50;
+	s_MemMappedCfg.TimeoutPeriodClock = 0xffff;
+	} else {
+	s_MemMappedCfg.TimeOutActivation = HAL_XSPI_TIMEOUT_COUNTER_DISABLE;
+	}
+
 	ret = HAL_XSPI_MemoryMapped(&dev_data->hxspi, &s_MemMappedCfg);
 	if (ret != HAL_OK) {
 		LOG_ERR("%d: Failed to set memory map", ret);
 		return -EIO;
 	}
 
-	LOG_INF("MemoryMap mode enabled");
+	LOG_INF("Memory-mapped mode enabled");
 
 	return 0;
 }
@@ -1147,13 +1183,12 @@ static int flash_stm32_xspi_erase(const struct device *dev, off_t addr,
 			ret = stm32_xspi_mem_ready(dev, dev_cfg->data_mode,
 						dev_cfg->data_rate);
 		}
-
 	}
 	/* Ends the erase operation */
 
 erase_end:
 	xspi_unlock_thread(dev);
-
+	stm32_xspi_set_memorymap(dev, true);
 	return ret;
 }
 
@@ -1184,7 +1219,7 @@ static int flash_stm32_xspi_read(const struct device *dev, off_t addr,
 
 	/* Do reads through memory-mapping instead of indirect */
 	if (!stm32_xspi_is_memorymap(dev)) {
-		ret = stm32_xspi_set_memorymap(dev);
+		ret = stm32_xspi_set_memorymap(dev, false);
 		if (ret != 0) {
 			LOG_ERR("READ: failed to set memory mapped");
 			goto read_end;
@@ -1300,7 +1335,7 @@ static int flash_stm32_xspi_write(const struct device *dev, off_t addr,
 
 	/* Do writes through memory-mapping instead of indirect */
 	if (!stm32_xspi_is_memorymap(dev)) {
-		ret = stm32_xspi_set_memorymap(dev);
+		ret = stm32_xspi_set_memorymap(dev, false);
 		if (ret != 0) {
 			LOG_ERR("WRITE: failed to set memory mapped");
 			goto write_end;
@@ -1319,8 +1354,8 @@ static int flash_stm32_xspi_write(const struct device *dev, off_t addr,
 	* after the programming. So a delay corresponding to max page programming
 	* time is added */
 	k_busy_wait(HAL_XSPI_TIMEOUT_DEFAULT_VALUE);
+
 	goto write_end;
- 
 #endif /* CONFIG_STM32_MEMMAP */
 
 	/* page program for STR or DTR mode */
@@ -2364,7 +2399,7 @@ static int flash_stm32_xspi_init(const struct device *dev)
 #endif /* CONFIG_FLASH_PAGE_LAYOUT */
 
 #ifdef CONFIG_STM32_MEMMAP
-	ret = stm32_xspi_set_memorymap(dev);
+	ret = stm32_xspi_set_memorymap(dev, true);
 	if (ret != 0) {
 		LOG_ERR("Failed to enable memory-mapped mode: %d", ret);
 		return ret;