WIP: AMD Support and Watchdog #93
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kbumsik
requested changes
Oct 16, 2025
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| "using_extend": false, | ||
| "dense_layers": [0, 1, 2, 47, 46, 45], | ||
| "mask_refresh_interval": [96], | ||
| "mask_refresh_interval": [96, 32, 16], | ||
| "layers": [ | ||
| { | ||
| "sliding_window_size": 1024, | ||
| "sliding_window_size_for_masking_step": [1024, 1024, 1024], | ||
| "second_stage_k": 1024, | ||
| "second_stage_k": 2048, | ||
| "sink_token_size": 1024, | ||
| "sa_extend_backend": "self_extend", | ||
| "stages": [ { } ] | ||
| "stages": [ | ||
| { | ||
| "stage_block_size_q":128, | ||
| "stage_block_stride_q":4, | ||
| "stage_chunk_size":256, | ||
| "stage_k":null, | ||
| "stage_stride":1, | ||
| "using_landmark":false | ||
| }, | ||
| { | ||
| "stage_block_size_q":64, | ||
| "stage_block_stride_q":1, | ||
| "stage_chunk_size":32, | ||
| "stage_k":65536, | ||
| "stage_stride":1, | ||
| "using_landmark":false | ||
| }, | ||
| { | ||
| "stage_block_size_q":64, | ||
| "stage_block_stride_q":1, | ||
| "stage_chunk_size":8, | ||
| "stage_k":8192, | ||
| "stage_stride":1, | ||
| "using_landmark":false | ||
| } | ||
| ] | ||
| }, | ||
| { | ||
| "sliding_window_size": 1024, | ||
| "sliding_window_size_for_masking_step": [1024, 1024, 1024], | ||
| "second_stage_k": 1024, | ||
| "second_stage_k": 2048, | ||
| "sink_token_size": 1024, | ||
| "sa_extend_backend": "self_extend", | ||
| "scan_extend_backend": "none", | ||
| "stages": [ { } ] | ||
| "stages": [ | ||
| { | ||
| "stage_block_size_q":128, | ||
| "stage_block_stride_q":4, | ||
| "stage_chunk_size":256, | ||
| "stage_k":null, | ||
| "stage_stride":1, | ||
| "using_landmark":false | ||
| }, | ||
| { | ||
| "stage_block_size_q":64, | ||
| "stage_block_stride_q":1, | ||
| "stage_chunk_size":32, | ||
| "stage_k":65536, | ||
| "stage_stride":1, | ||
| "using_landmark":false | ||
| }, | ||
| { | ||
| "stage_block_size_q":64, | ||
| "stage_block_stride_q":1, | ||
| "stage_chunk_size":8, | ||
| "stage_k":8192, | ||
| "stage_stride":1, | ||
| "using_landmark":false | ||
| } | ||
| ] | ||
| } | ||
| ], |
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I suppose it is used for qwen3.
So is this PR also fixes our qwen3 + nvidia? To me this PR can't be ignored even if we don't need AMD.
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WIP: AMD Support and Watchdog