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1. rupambora_RISC-V-SoC-Reference-Tapout-Program_VSD rupambora_RISC-V-SoC-Reference-Tapout-Program_VSD Public

   This repository documents my journey in the RISC-V Reference SoC Tapeout Program. The first 10 weeks focus on RTL design, synthesis, simulation, and verification using open-source tools like Yosys,…

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2. week01-rupambora_RISC-V-SoC-Reference-Tapout-Program_VSD week01-rupambora_RISC-V-SoC-Reference-Tapout-Program_VSD Public

   Week 1 covers RTL design, synthesis, and gate-level simulation using open-source tools. Includes simulation with iverilog and GTKWave, synthesis with Yosys and SKY130 PDK, timing libraries, hierarc…