FPGA Field-Oriented Control (FOC) Project

Overview

This project implements a Field-Oriented Control (FOC) system for a PMSM motor control using FPGA. The design includes various modules for signal processing, control algorithms, and hardware interfacing. The project is structured to facilitate simulation, synthesis, and hardware implementation.

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Project Folder Structure

FPGA_FOC/
├── constrs_1/
│   └── new/
│       └── pynq_z2_pins.xdc
├── sim_1/
│   └── new/
│       ├── foc_testbench.v
│       ├── tb_clark_park_tr.sv
│       └── tb_svpwm.sv
├── sources_1/
│   ├── ip/
│   │   └── clk_wiz_0/
│   │       └── clk_wiz_0.xci
│   └── new/
│       ├── adc_ad7928.v
│       ├── cartesian2polar.v
│       ├── clark_tr.v
│       ├── foc_top.v
│       ├── fpga_top.v
│       ├── hold_detect.v
│       ├── i2c_register_read.v
│       ├── park_tr.v
│       ├── pi_controller.v
│       ├── sincos.v
│       ├── svpwm.v
│       └── uart_monitor.v
├── utils_1/
│   └── imports/
│       └── synth_1/
│           └── fpga_top.dcp

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File Descriptions

constrs_1/

File Name	Description
pynq_z2_pins.xdc	Pin constraints for the PYNQ-Z2 FPGA board.

sim_1/

File Name	Description
foc_testbench.v	Testbench for the FOC system.
tb_clark_park_tr.sv	Testbench for the Clark and Park transformations.
tb_svpwm.sv	Testbench for the Space Vector Pulse Width Modulation (SVPWM) module.

sources_1/

sources_1/ip/

File Name	Description
clk_wiz_0.xci	Clock wizard IP core for generating clock signals.

sources_1/new/

File Name	Description
adc_ad7928.v	ADC interface module for the AD7928.
cartesian2polar.v	Module for converting Cartesian coordinates to polar coordinates.
clark_tr.v	Clark transformation module.
foc_top.v	Top-level module for the FOC system.
fpga_top.v	Top-level module for the FPGA design.
hold_detect.v	Module for detecting hold conditions.
i2c_register_read.v	I2C register read module.
park_tr.v	Park transformation module.
pi_controller.v	Proportional-Integral (PI) controller module.
sincos.v	Sine and cosine computation module.
svpwm.v	Space Vector Pulse Width Modulation (SVPWM) module.
uart_monitor.v	UART monitoring module.

utils_1/

File Name	Description
fpga_top.dcp	Synthesized design checkpoint for the top-level FPGA module.

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Detailed File Descriptions

constrs_1/new/

File Name	Description
pynq_z2_pins.xdc	Specifies the pin constraints for the PYNQ-Z2 FPGA board, mapping FPGA pins to external hardware connections.

sim_1/new/

File Name	Description
foc_testbench.v	Verifies the overall functionality of the FOC system by simulating all major modules together. Calls clark_tr, park_tr, svpwm, and pi_controller modules.
tb_clark_park_tr.sv	Tests the Clark and Park transformations, ensuring correct coordinate transformations. Calls clark_tr and park_tr modules.
tb_svpwm.sv	Simulates the SVPWM module to verify PWM signal generation. Calls svpwm module.

sources_1/ip/clk_wiz_0/

File Name	Description
clk_wiz_0.xci	Generates clock signals required for the FPGA design. Provides clocking for modules like foc_top and fpga_top.

sources_1/new/

File Name	Description
adc_ad7928.v	Interfaces with the AD7928 ADC to read analog signals. Provides input data to the foc_top module.
cartesian2polar.v	Converts Cartesian coordinates to polar coordinates. Used in motor control calculations within foc_top.
clark_tr.v	Implements the Clark transformation to convert three-phase currents to a two-axis system. Called by foc_top.
foc_top.v	Top-level module for the FOC system, integrating all major components like clark_tr, park_tr, svpwm, and pi_controller.
fpga_top.v	Top-level module for the FPGA design, connecting external interfaces and the foc_top module.
hold_detect.v	Detects hold conditions in the motor. Provides feedback to the pi_controller.
i2c_register_read.v	Reads data from I2C registers. Used for configuration or monitoring purposes.
park_tr.v	Implements the Park transformation to convert currents to a rotating reference frame. Called by foc_top.
pi_controller.v	Implements a Proportional-Integral controller for regulating motor speed and torque. Called by foc_top.
sincos.v	Computes sine and cosine values for the Park transformation. Called by park_tr.
svpwm.v	Generates optimized PWM signals for motor control. Called by foc_top.
uart_monitor.v	Monitors UART communication for debugging and data logging. Interfaces with external systems.

utils_1/imports/synth_1/

File Name	Description
fpga_top.dcp	Synthesized design checkpoint for the top-level FPGA module. Used for implementation and bitstream generation.

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Key Modules

1. park_tr.v

Implements the Park transformation, which converts three-phase currents into a rotating reference frame. This is a critical step in FOC for simplifying the control of AC motors.

2. svpwm.v

Implements Space Vector Pulse Width Modulation, which generates optimized PWM signals for driving the motor.

3. pi_controller.v

Implements a Proportional-Integral controller for regulating motor speed and torque.

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Simulation

The simulation files in sim_1/new/ allow for verifying the functionality of individual modules and the overall system. Use a Verilog simulator to run the testbenches.

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Synthesis and Implementation

The project includes constraint files and synthesized design checkpoints for targeting the PYNQ-Z2 FPGA board. Use Vivado for synthesis, implementation, and bitstream generation.

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How to Use

1. Simulation

To verify the functionality of the design:

1. Navigate to the sim_1/new/ directory.
2. Use a Verilog simulator such as ModelSim or Vivado Simulator to run the testbenches:
   • foc_testbench.v: Tests the overall FOC system.
   • tb_clark_park_tr.sv: Tests the Clark and Park transformation modules.
   • tb_svpwm.sv: Tests the SVPWM module.
3. Analyze the simulation waveforms to ensure the modules behave as expected.

2. Synthesis

To synthesize the design for the PYNQ-Z2 FPGA board:

1. Open Xilinx Vivado.
2. Import the project files from the sources_1/new/ directory.
3. Apply the pin constraints from constrs_1/new/pynq_z2_pins.xdc.
4. Run the synthesis process to generate the netlist.

3. Implementation

To implement the design on the FPGA:

1. Use the synthesized netlist to perform place-and-route in Vivado.
2. Generate the bitstream file.
3. Program the FPGA using the generated bitstream.

4. Testing on Hardware

To test the design on the PYNQ-Z2 FPGA board:

1. Connect the FPGA board to your computer via USB.
2. Load the bitstream onto the FPGA.
3. Use a UART terminal (e.g., PuTTY) to monitor the output from the uart_monitor.v module.
4. Verify the motor control functionality by observing the motor's behavior.

5. Modifying the Design

To modify or extend the design:

1. Edit the Verilog source files in the sources_1/new/ directory.
2. Update the testbenches in sim_1/new/ to include new test cases.
3. Re-run the simulation, synthesis, and implementation steps to validate the changes.

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Tools and Requirements

• FPGA Board: PYNQ-Z2
• Simulation Tool: ModelSim or equivalent
• Synthesis Tool: Xilinx Vivado