flow: Inherit VERILOG_DEFINES in check_ports() #118
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The ASIC flow has config.json that a user can provide but Yosys can also need globals options, particularly with Verilog pre-processor defines so the Verilog source can be shared between ASIC and FPGA allowing for example ASIC/FPGA target specific cells to be added/removed from design.
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Thanks! I'm not sure we'll actually keep check ports the way it is - it will probably make more sense to implement it as a LibreLane step, or so. |
--create-user-config uses Yosys to extract ports, but did not inherit config.json VERILOG_DEFINES when it does this step. So the source view that is presented is completely different to that of the ASIC flow. Which would have otherwise worked successfully. This means if Verilog expressions not compatible or necessary for main flow were correctly ifdef/endif the flow would still fail due to the TT --create-user-config step bailing. It maybe necessary for users to manually add SYNTHESIS to their VERILOG_DEFINES list so that is added for this custom TT step. No attempt is made to mimic implicitly added defines, as that will always play catchup. It would be completely compatible with all systems to have the user just be explicit about it if that is needed for their project. This commit provides the option to achieve a good configuration without needing to customize verilog source code (by manually doing the task of ifdef/endif and committing what is left).
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Yes that would be a better solution, so it has the same project settings and source view as the actual flow. I'm just about to see if I can add a custom flow+yosys plugin to implement/ignore the $info/$warning by providing a no-operation callout etc... but also to remove/ignore by default the |
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Totally untested at PR time will update on status, after this has been tested.
Doing:
With config.json setup
VERILOG_DEFINES = [ "OPENLANE_SYNTHESIS" ]Causes the TT
check_ports()to fail. The flow itself works fine.