@@ -182,8 +182,7 @@ function AD9361_Filter_Wizard_OpeningFcn(hObject, eventdata, handles, varargin)
182182 end
183183end
184184
185- % sanity check the DAC divider value and alter it if necessary, note that if
186- % it's altered then the PLL and calibration dividers must be updated as well
185+ % sanity check the PLL rate and DAC divider values and alter them if necessary
187186if isfield(handles , ' input_tx' ) && isfield(handles , ' input_rx' )
188187 if (handles .input_rx .PLL_rate ~= handles .input_tx .PLL_rate )
189188 rhb1 = handles .input_tx .HB1 ;
@@ -204,7 +203,7 @@ function AD9361_Filter_Wizard_OpeningFcn(hObject, eventdata, handles, varargin)
204203 DAC_rate = handles .input_tx .Rdata * handles .input_tx .FIR * ...
205204 handles .input_tx .HB1 * handles .input_tx .HB2 * handles .input_tx .HB3 ;
206205 DAC_div = ADC_rate / DAC_rate ;
207- if ~ (handles .input_tx .DAC_div = = DAC_div )
206+ if (handles .input_tx .DAC_div ~ = DAC_div )
208207 if (DAC_div == 1 || DAC_div == 2 )
209208 handles.input_tx.DAC_div = DAC_div ;
210209 handles.input_tx.PLL_mult = handles .input_rx .PLL_mult ;
@@ -232,7 +231,7 @@ function AD9361_Filter_Wizard_OpeningFcn(hObject, eventdata, handles, varargin)
232231 DAC_rate = handles .input_tx .Rdata * handles .input_tx .FIR * ...
233232 handles .input_tx .HB1 * handles .input_tx .HB2 * handles .input_tx .HB3 ;
234233 DAC_div = ADC_rate / DAC_rate ;
235- if ~ (handles .input_tx .DAC_div = = DAC_div )
234+ if (handles .input_tx .DAC_div ~ = DAC_div )
236235 if (DAC_div == 1 || DAC_div == 2 )
237236 handles.input_tx.DAC_div = DAC_div ;
238237 handles.input_tx.PLL_mult = handles .input_rx .PLL_mult ;
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