Fix timing issues on FMCOMMS2 and AD9081/VCU118

docs/user_guide/build_hdl.rst

@@ -576,9 +576,37 @@ Running the command below will create a folder named **LVDSCMOSN1**.
 
    make LVDS_CMOS_N=1
 
-Enabling Out-of-Context synthesis
+Available build flags and parameters
 ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
 
+Below are some of the available parameters and system variables that can be used
+when building a project:
+
+- **ADI_EXTRACT_PORTS**: if set, extracts port properties from a predefined list
+  of IPs into 'ports_properties.txt'.
+- **ADI_GENERATE_BIN**: if set, generates a binary bitstream file (.bin)
+  in addition to the .xsa hardware platform.
+- **ADI_GENERATE_UTILIZATION**: if set, generates CSV and log files detailing
+  resource utilization for the design and specific IPs.
+- **ADI_GENERATE_XPA**: if set, runs a Xilinx Power Analysis (XPA) and generates
+  a summary report.
+- **ADI_MAX_OOC_JOBS**: specifies the number of parallel jobs to use for
+  Out-of-Context (OOC) synthesis.
+- **ADI_MAX_THREADS**: specifies the maximum number of threads for Vivado
+  operations. Default value is 8.
+- **ADI_NO_BITSTREAM_COMPRESSION**: if set, disables compression of the final
+  bitstream file.
+- **ADI_POST_ROUTE_SCRIPT**: specifies the path to a Tcl script to be executed
+  after the routing design step.
+- **ADI_POWER_OPTIMIZATION**: if set to 1, enables power optimization during the
+  implementation run.
+- **ADI_PROJECT_DIR**: specifies a base directory for output files such as logs
+  and reports.
+- **ADI_SKIP_SYNTHESIS**: if set, the entire procedure will exit before starting
+  synthesis.
+- **ADI_USE_OOC_SYNTHESIS**: if set to 1, launches synthesis for OOC IP modules
+  in parallel.
+
 You can opt in for out-of-context synthesis during the build by defining
 the ``ADI_USE_OOC_SYNTHESIS`` system variable. By setting the
 ``ADI_MAX_OOC_JOBS`` system variable you can adjust the number of

projects/ad9081_fmca_ebz/vcu118/system_project.tcl

@@ -6,6 +6,7 @@
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
 
 # get_env_param retrieves parameter value from the environment if exists,
 # other case use the default value
@@ -95,4 +96,6 @@ if {$ADI_USE_OOC_SYNTHESIS == 1} {
   set_property used_in_synthesis false [get_files timing_constr.xdc]
 }
 
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
+
 adi_project_run ad9081_fmca_ebz_vcu118

projects/daq2/kcu105/system_project.tcl

@@ -1,26 +1,28 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME kcu105
 
 # get_env_param retrieves parameter value from the environment if exists,
 # other case use the default value
 #
 #   Use over-writable parameters from the environment.
 #
 #    e.g.
-#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
 
 # Parameter description:
 #   [RX/TX]_JESD_M : Number of converters per link
 #   [RX/TX]_JESD_L : Number of lanes per link
 #   [RX/TX]_JESD_S : Number of samples per frame
 
-adi_project daq2_kcu105 0 [list \
+adi_project daq2_${BOARD_NAME} 0 [list \
   RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
   RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
   RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
@@ -29,14 +31,15 @@ adi_project daq2_kcu105 0 [list \
   TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
 ]
 
-adi_project_files daq2_kcu105 [list \
+adi_project_files daq2_${BOARD_NAME} [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
-## To improve timing in DDR4 MIG
-set_property strategy Performance_RefinePlacement [get_runs impl_1]
+## daq2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
 
-adi_project_run daq2_kcu105
+adi_project_run daq2_${BOARD_NAME}

projects/daq2/zc706/system_project.tcl

@@ -1,26 +1,28 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME zc706
 
 # get_env_param retrieves parameter value from the environment if exists,
 # other case use the default value
 #
 #   Use over-writable parameters from the environment.
 #
 #    e.g.
-#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
 
 # Parameter description:
 #   [RX/TX]_JESD_M : Number of converters per link
 #   [RX/TX]_JESD_L : Number of lanes per link
 #   [RX/TX]_JESD_S : Number of samples per frame
 
-adi_project daq2_zc706 0 [list \
+adi_project daq2_${BOARD_NAME} 0 [list \
   RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
   RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
   RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
@@ -29,17 +31,16 @@ adi_project daq2_zc706 0 [list \
   TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
 ]
 
-adi_project_files daq2_zc706 [list \
+adi_project_files daq2_${BOARD_NAME} [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_plddr3_constr.xdc" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
-
-adi_project_run daq2_zc706
-
-## To improve timing in the axi_ad9680_offload component
-set_property strategy Performance_Retiming [get_runs impl_1]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_plddr3_constr.xdc" \
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
+## daq2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
 
+adi_project_run daq2_${BOARD_NAME}

projects/daq2/zcu102/system_project.tcl

@@ -1,26 +1,28 @@
 ###############################################################################
-## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2016-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME zcu102
 
 # get_env_param retrieves parameter value from the environment if exists,
 # other case use the default value
 #
 #   Use over-writable parameters from the environment.
 #
 #    e.g.
-#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2 
+#      make RX_JESD_L=4 RX_JESD_M=2 TX_JESD_L=4 TX_JESD_M=2
 
 # Parameter description:
 #   [RX/TX]_JESD_M : Number of converters per link
 #   [RX/TX]_JESD_L : Number of lanes per link
 #   [RX/TX]_JESD_S : Number of samples per frame
 
-adi_project daq2_zcu102 0 [list \
+adi_project daq2_${BOARD_NAME} 0 [list \
   RX_JESD_M    [get_env_param RX_JESD_M    2 ] \
   RX_JESD_L    [get_env_param RX_JESD_L    4 ] \
   RX_JESD_S    [get_env_param RX_JESD_S    1 ] \
@@ -29,14 +31,15 @@ adi_project daq2_zcu102 0 [list \
   TX_JESD_S    [get_env_param TX_JESD_S    1 ] \
 ]
 
-adi_project_files daq2_zcu102 [list \
+adi_project_files daq2_${BOARD_NAME} [list \
   "../common/daq2_spi.v" \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
-adi_project_run daq2_zcu102
+## daq2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
 
-## To improve timing in the axi_ad9680_offload component
-set_property strategy Performance_Retiming [get_runs impl_1]
+adi_project_run daq2_${BOARD_NAME}

projects/fmcomms2/kcu105/system_project.tcl

@@ -6,18 +6,20 @@
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME kcu105
 
-adi_project fmcomms2_kcu105
-adi_project_files fmcomms2_kcu105 [list \
+adi_project fmcomms2_${BOARD_NAME}
+adi_project_files fmcomms2_${BOARD_NAME} [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/kcu105/kcu105_system_constr.xdc" \
-  "$ad_hdl_dir/projects/common/kcu105/kcu105_system_lutram_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" \
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_lutram_constr.xdc" ]
 
-## To improve timing in DDR4 MIG
-set_property strategy Performance_RefinePlacement [get_runs impl_1]
-set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE ExploreWithAggressiveHoldFix [get_runs impl_1]
+## fmcomms2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
 
-adi_project_run fmcomms2_kcu105
+adi_project_run fmcomms2_${BOARD_NAME}
 source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl

projects/fmcomms2/zc702/system_project.tcl

@@ -1,21 +1,25 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME zc702
 
-adi_project fmcomms2_zc702
-adi_project_files fmcomms2_zc702 [list \
+adi_project fmcomms2_${BOARD_NAME}
+adi_project_files fmcomms2_${BOARD_NAME} [list \
   "system_top.v" \
   "system_constr.xdc" \
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc702/zc702_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
-set_property strategy Performance_Explore [get_runs impl_1]
+## fmcomms2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
 
-adi_project_run fmcomms2_zc702
+adi_project_run fmcomms2_${BOARD_NAME}
 source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
 

projects/fmcomms2/zc706/system_project.tcl

@@ -1,19 +1,25 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME zc706
 
-adi_project fmcomms2_zc706
-adi_project_files fmcomms2_zc706 [list \
+adi_project fmcomms2_${BOARD_NAME}
+adi_project_files fmcomms2_${BOARD_NAME} [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zc706/zc706_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
-adi_project_run fmcomms2_zc706
+## fmcomms2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
+
+adi_project_run fmcomms2_${BOARD_NAME}
 source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
 

projects/fmcomms2/zcu102/system_project.tcl

@@ -1,19 +1,25 @@
 ###############################################################################
-## Copyright (C) 2016-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME zcu102
 
-adi_project fmcomms2_zcu102
-adi_project_files fmcomms2_zcu102 [list \
+adi_project fmcomms2_${BOARD_NAME}
+adi_project_files fmcomms2_${BOARD_NAME} [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zcu102/zcu102_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
-adi_project_run fmcomms2_zcu102
+## fmcomms2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
+
+adi_project_run fmcomms2_${BOARD_NAME}
 source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
 

projects/fmcomms2/zed/system_project.tcl

@@ -1,19 +1,24 @@
 ###############################################################################
-## Copyright (C) 2014-2023 Analog Devices, Inc. All rights reserved.
+## Copyright (C) 2014-2023, 2025 Analog Devices, Inc. All rights reserved.
 ### SPDX short identifier: ADIBSD
 ###############################################################################
 
 source ../../../scripts/adi_env.tcl
 source $ad_hdl_dir/projects/scripts/adi_project_xilinx.tcl
 source $ad_hdl_dir/projects/scripts/adi_board.tcl
+set ADI_POST_ROUTE_SCRIPT [file normalize $ad_hdl_dir/projects/scripts/auto_timing_fix_xilinx.tcl]
+set BOARD_NAME zed
 
-adi_project fmcomms2_zed
-adi_project_files fmcomms2_zed [list \
+adi_project fmcomms2_${BOARD_NAME}
+adi_project_files fmcomms2_${BOARD_NAME} [list \
   "system_top.v" \
   "system_constr.xdc"\
   "$ad_hdl_dir/library/common/ad_iobuf.v" \
-  "$ad_hdl_dir/projects/common/zed/zed_system_constr.xdc" ]
+  "$ad_hdl_dir/projects/common/${BOARD_NAME}/${BOARD_NAME}_system_constr.xdc" ]
 
-adi_project_run fmcomms2_zed
-source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl
+## fmcomms2 design is presenting hold time violations on some paths
+## set the strategy to spread logic and help with hold time fixes
+set_property strategy Congestion_SpreadLogic_high [get_runs impl_1]
 
+adi_project_run fmcomms2_${BOARD_NAME}
+source $ad_hdl_dir/library/axi_ad9361/axi_ad9361_delay.tcl