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library/util_axis_fifo_asym: fix behavior when tkeep=0 #1914
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I tested these changes with different tkeep masks on the SPI Engine and it works. I could not test different tkeep masks on the testbench here: https://github.com/analogdevicesinc/testbenches/tree/main/testbenches/ip/util_axis_fifo_asym |
Added a testbench for this (still a draft for now): analogdevicesinc/testbenches#246 |
Fix a bug where m_axis_valid waits on m_axis_ready to be asserted a few times in order to skip over data for which tkeep was all zeroes. This was a violation of the AXI Streaming protocol. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
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Fix tvalid low when tlast is present. Before this commit, util_axis_fifo would suppress all transfers with tkeep=0, even if tlast was asserted. This commit makes it so transfers with tlast asserted are preserved. The AXI-Streaming spec allows us to suppress transfers for which all tkeep bits are 0 (all bytes are null bytes), but only in the case when tlast=0 as well. Transfers where tlast is asserted can't be suppressed even when all bytes are null. Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
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Signed-off-by: Laez Barbosa <laez.barbosa@analog.com>
Moved to draft due to recent discussions on the FIFOs affecting this PR. |
AXI Streaming doesn't allow for tvalid to depend on tready (AMBA AXI-Stream Protocol Specification, 2.2 Handshake signaling).
The previous version of
util_axis_fifo_asym
relied on the downstream user asserting tready whenever there was data at the output that was invalid due to tkeep=0, even if tvalid was 0 in this case.In #1808 this forced us to introduce extra logic on the
spi_engine
as a workaround. With this PR, we can skip that extra logic. If this is merged after #1808, we'll need to add a commit removing the workaround logic.This FIFO is used only in the
spi_engine
(after #1808 ) anddata_offload
IPs. I tried to make the fix so it only affects theTKEEP_EN=1
case, which would only affectspi_engine
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