AXI DMAC fixes and higher than 32 bits support #2997
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If 'hw_cyclic' is false we should still be able to do cyclic transfers in "software". That was not working for the case where 'desc->num_sgs' is 1 because 'chan->next_desc' is never set with the current desc which means that the cyclic transfer only runs once and in the next SOT interrupt we do nothing since vchan_next_desc() will return NULL. Fix it by setting 'chan->next_desc' as soon as we get a new desc via vchan_next_desc(). Fixes: 0e3b67b ("dmaengine: Add support for the Analog Devices AXI-DMAC DMA controller") Signed-off-by: Nuno Sá <nuno.sa@analog.com>
For HW scatter gather transfers we still need to look for the queue. The HW is capable of queueing 3 concurrent transfers and if we try more than that we'll get the submit queue full and should return. Otherwise, if we go ahead and program the new transfer, we end up discarding it. Fixes: e97dc74 ("dmaengine: axi-dmac: Add support for scatter-gather transfers") Signed-off-by: Nuno Sá <nuno.sa@analog.com>
In some supported platforms as ARCH_ZYNQMP, part of the memory is mapped above 32bit addresses and since the DMA mask, by default, is set to 32bits, we would need to rely on swiotlb (which incurs a performance penalty) for the DMA mappings. Thus, we can write either the SRC or DEST high addresses with 1's and read them back. The last bit set on the return value will reflect the IP address bus width and so we can update the device DMA mask accordingly. While at it, support bigger that 32 bits transfers in IP without HW scatter gather support. Signed-off-by: Nuno Sá <nuno.sa@analog.com>
nunojsa
requested review from
CiprianRegus,
amiclaus,
btogorean,
buha,
chegbeli,
danmois,
dbogdan,
machschmitt,
mhennerich and
rbolboac
as code owners
mhennerich
approved these changes
Oct 23, 2025
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PR Description
This fixes some issues on the AXI DMAC IP driver. Most importantly, it allows to use higher than 32 bit bus addresses which is important for zynqMP. My expectation was for this to go upstream first but the dmaengine subsystem maintainer is pretty unresponsive (in the below link this maybe my 5/6th resend) so let's add it right away to our tree.
https://lore.kernel.org/dmaengine/20250923-b4-dev-axi-dmac-fixes-v1-0-5896dcbbd909@analog.com/
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