Refactoring the RISCV architecture to Auto-Sync on LLVM

CMakeLists.txt

@@ -596,23 +596,32 @@ endif()
 if(CAPSTONE_RISCV_SUPPORT)
     add_definitions(-DCAPSTONE_HAS_RISCV)
     set(SOURCES_RISCV
+        arch/RISCV/RISCVBaseInfo.c
         arch/RISCV/RISCVDisassembler.c
+        arch/RISCV/RISCVDisassemblerExtension.c
         arch/RISCV/RISCVInstPrinter.c
         arch/RISCV/RISCVMapping.c
         arch/RISCV/RISCVModule.c
     )
     set(HEADERS_RISCV
         arch/RISCV/RISCVBaseInfo.h
-        arch/RISCV/RISCVDisassembler.h
+        arch/RISCV/RISCVDisassemblerExtension.h
         arch/RISCV/RISCVInstPrinter.h
         arch/RISCV/RISCVMapping.h
         arch/RISCV/RISCVModule.h
         arch/RISCV/RISCVGenAsmWriter.inc
+        arch/RISCV/RISCVGenCSAliasMnemMap.inc
+        arch/RISCV/RISCVGenCSFeatureName.inc
+        arch/RISCV/RISCVGenCSMappingInsn.inc
+        arch/RISCV/RISCVGenCSMappingInsnName.inc
+        arch/RISCV/RISCVGenCSMappingInsnOp.inc
+        arch/RISCV/RISCVGenCSOpGroup.inc
+        arch/RISCV/RISCVGenCSSystemOperandsEnum.inc
         arch/RISCV/RISCVGenDisassemblerTables.inc
-        arch/RISCV/RISCVGenInsnNameMaps.inc
         arch/RISCV/RISCVGenInstrInfo.inc
         arch/RISCV/RISCVGenRegisterInfo.inc
         arch/RISCV/RISCVGenSubtargetInfo.inc
+        arch/RISCV/RISCVGenSystemOperands.inc
         arch/RISCV/RISCVMappingInsn.inc
         arch/RISCV/RISCVMappingInsnOp.inc
     )

MCInstPrinter.c

@@ -11,6 +11,7 @@ extern bool Mips_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool AArch64_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool TriCore_getFeatureBits(unsigned int mode, unsigned int feature);
 extern bool Sparc_getFeatureBits(unsigned int mode, unsigned int feature);
+extern bool RISCV_getFeatureBits(unsigned int mode, unsigned int feature);
 
 static bool testFeatureBits(const MCInst *MI, uint32_t Value)
 {
@@ -42,8 +43,13 @@ static bool testFeatureBits(const MCInst *MI, uint32_t Value)
 #ifdef CAPSTONE_HAS_SPARC
 	case CS_ARCH_SPARC:
 		return Sparc_getFeatureBits(MI->csh->mode, Value);
+#endif
+#ifdef CAPSTONE_HAS_RISCV
+	case CS_ARCH_RISCV:
+		return RISCV_getFeatureBits(MI->csh->mode, Value);
 #endif
 	}
+
 }
 
 static bool matchAliasCondition(MCInst *MI, const MCRegisterInfo *MRI,

MathExtras.h

@@ -57,6 +57,11 @@ static inline bool isIntN(unsigned N, int64_t x) {
   return N >= 64 || (-(INT64_C(1)<<(N-1)) <= x && x < (INT64_C(1)<<(N-1)));
 }
 
+/// isShiftedIntN - Checks if a signed integer is an N bit number shifted left by S.
+static inline bool isShiftedIntN(unsigned N, unsigned S, int64_t x) {
+  return isIntN(N + S, x) && (x % (UINT64_C(1) << S) == 0);
+}
+
 /// isMask_32 - This function returns true if the argument is a sequence of ones
 /// starting at the least significant bit with the remainder zero (32 bit
 /// version).   Ex. isMask_32(0x0000FFFFU) == true.

SStream.c

@@ -480,6 +480,13 @@ void printFloat(SStream *ss, float val)
 	SStream_concat(ss, "%e", val);
 }
 
+void printfFloat(SStream *ss, const char* fmt, float val) 
+{
+	assert(ss);
+	SSTREAM_RETURN_IF_CLOSED(ss);
+	SStream_concat(ss, fmt, val);
+}
+
 void printFloatBang(SStream *ss, float val)
 {
 	assert(ss);

SStream.h

@@ -92,6 +92,8 @@ void printInt32BangDec(SStream *O, int32_t val);
 
 void printFloat(SStream *O, float val);
 
+void printfFloat(SStream *ss, const char* fmt, float val);
+
 void printFloatBang(SStream *O, float val);
 
 void printExpr(SStream *O, uint64_t val);

arch/RISCV/RISCVBaseInfo.c

@@ -0,0 +1,143 @@
+/* Capstone Disassembly Engine, http://www.capstone-engine.org */
+/* By Nguyen Anh Quynh <aquynh@gmail.com>, 2013-2022, */
+/*    Rot127 <unisono@quyllur.org> 2022-2023 */
+/* Automatically translated source file from LLVM. */
+
+/* LLVM-commit: <commit> */
+/* LLVM-tag: <tag> */
+
+/* Only small edits allowed. */
+/* For multiple similar edits, please create a Patch for the translator. */
+
+/* Capstone's C++ file translator: */
+/* https://github.com/capstone-engine/capstone/tree/next/suite/auto-sync */
+
+//===-- RISCVBaseInfo.cpp - Top level definitions for RISC-V MC -----------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file contains small standalone enum definitions for the RISC-V target
+// useful for the compiler back-end and the MC libraries.
+//
+//===----------------------------------------------------------------------===//
+
+#include <stdio.h>
+#include <string.h>
+#include <stdlib.h>
+#include <capstone/platform.h>
+
+#include "RISCVBaseInfo.h"
+
+#define CONCAT(a, b) CONCAT_(a, b)
+#define CONCAT_(a, b) a##_##b
+
+typedef struct {
+	unsigned value;
+	bool isFractional;
+} VLMULDecodeResult;
+VLMULDecodeResult decodeVLMUL(RISCVII_VLMUL VLMUL)
+{
+	switch (VLMUL) {
+	default:
+		CS_ASSERT(0 && "Unexpected LMUL value!");
+	case RISCVII_LMUL_1:
+	case RISCVII_LMUL_2:
+	case RISCVII_LMUL_4:
+	case RISCVII_LMUL_8: {
+		VLMULDecodeResult result = {
+			.value = 1 << (unsigned)(VLMUL), 
+			.isFractional = false
+		};
+		return result;
+	}
+	case RISCVII_LMUL_F2:
+	case RISCVII_LMUL_F4:
+	case RISCVII_LMUL_F8: {
+	VLMULDecodeResult result = {
+			.value = 1 << (8 - (unsigned)(VLMUL)), 
+			.isFractional = true
+		};
+		return result;
+	}
+	}
+}
+
+void printVType(unsigned VType, SStream *OS)
+{
+	unsigned Sew = RISCVVType_getSEW(VType);
+	SStream_concat(OS, "%s", "e");
+	printUInt64(OS, Sew);
+
+	unsigned LMul;
+	bool Fractional;
+	VLMULDecodeResult result = decodeVLMUL(RISCVVType_getVLMUL(VType));
+	LMul = result.value;
+	Fractional = result.isFractional;
+
+	if (Fractional)
+		SStream_concat0(OS, ", mf");
+	else
+		SStream_concat0(OS, ", m");
+	printUInt64(OS, LMul);
+
+	if (RISCVVType_isTailAgnostic(VType))
+		SStream_concat0(OS, ", ta");
+	else
+		SStream_concat0(OS, ", tu");
+
+	if (RISCVVType_isMaskAgnostic(VType))
+		SStream_concat0(OS, ", ma");
+	else
+		SStream_concat0(OS, ", mu");
+}
+
+typedef struct {
+	uint8_t first;
+	uint8_t second;
+} LoadFP32ImmArrElement;
+
+// Lookup table for fli.s for entries 2-31.
+static const LoadFP32ImmArrElement LoadFP32ImmArr[] = {
+	{ 0b01101111, 0b00 }, { 0b01110000, 0b00 }, { 0b01110111, 0b00 },
+	{ 0b01111000, 0b00 }, { 0b01111011, 0b00 }, { 0b01111100, 0b00 },
+	{ 0b01111101, 0b00 }, { 0b01111101, 0b01 }, { 0b01111101, 0b10 },
+	{ 0b01111101, 0b11 }, { 0b01111110, 0b00 }, { 0b01111110, 0b01 },
+	{ 0b01111110, 0b10 }, { 0b01111110, 0b11 }, { 0b01111111, 0b00 },
+	{ 0b01111111, 0b01 }, { 0b01111111, 0b10 }, { 0b01111111, 0b11 },
+	{ 0b10000000, 0b00 }, { 0b10000000, 0b01 }, { 0b10000000, 0b10 },
+	{ 0b10000001, 0b00 }, { 0b10000010, 0b00 }, { 0b10000011, 0b00 },
+	{ 0b10000110, 0b00 }, { 0b10000111, 0b00 }, { 0b10001110, 0b00 },
+	{ 0b10001111, 0b00 }, { 0b11111111, 0b00 }, { 0b11111111, 0b10 },
+};
+
+float getFPImm(unsigned Imm)
+{
+	CS_ASSERT(Imm != 1 && Imm != 30 && Imm != 31 &&
+		  "Unsupported immediate");
+
+	// Entry 0 is -1.0, the only negative value. Entry 16 is 1.0.
+	uint32_t Sign = 0;
+	if (Imm == 0) {
+		Sign = 0b1;
+		Imm = 16;
+	}
+
+	uint32_t Exp = LoadFP32ImmArr[Imm - 2].first;
+	uint32_t Mantissa = LoadFP32ImmArr[Imm - 2].second;
+
+	uint32_t I = Sign << 31 | Exp << 23 | Mantissa << 21;
+	float result;
+  	memcpy(&result, &I, sizeof(float));
+  	return result;
+}
+
+void RISCVZC_printSpimm(int64_t Spimm, SStream *OS)
+{
+	printUInt64(OS, Spimm);
+}
+
+// namespace llvm