Skip to content

<reg[3] for special meaning.> <I new a project using IAR, and debug it with the IAR simulator. I modified the instruction byte code, and get strange assembles that are not documented. I draw a conclusion in my opinion, for the following instructions: [0 0 0 0 src 1 1 0 0 dst — MOVA Rsrc,Rdst], [0 0 0 0 src 1 1 0 1 dst — CMPA Rsrc,Rdst], [0 0 0 0 src 1 1 1 0 dst — ADDA Rsrc,Rdst], [0 0 0 0 src 1 1 1 1 dst — SUBA Rsrc,Rdst], when src is reg[3], it has special meanings. According to the oper, the Rsrc is MOVA: 0. CMPA: 0. ADDA: 2. SUBA: 2.> #105

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Open
zhaoleicpp wants to merge 1 commit into
base: master
Choose a base branch
from

reg[3] for special meaning.

5482bdf
Select commit
Loading
Failed to load commit list.

Workflow runs completed with no jobs