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@yueneiqi yueneiqi commented Nov 28, 2025

变更概览

  • 测试引入 rk3588-clk:新增关于 USB 的时钟门逻辑
  • 增加关于 USBDP PHY 的日志
  • 修改 xhci

测试

  • 在 orangepi5p 上运行,在 uboot 的启动命令中加入 usb start后,检测到两个 USB 端口,后续仍然卡在 WaitMap 处:
WaitMap: try_wait_for_result called with id 6282020, elem@0xffff9003ffe188d0 false
🔍 18.565s    [crab_usb::backend::xhci::root:565] assigned slot id: 1
🐛 18.566s    [crab_usb::backend::xhci::root:572] Slot 1 assigned
🐛 18.567s    [crab_usb::backend::xhci::root:581] Creating new context for slot 1, 64-bit
🔍 18.569s    [crab_usb::backend::xhci::device:203] Initializing device with ID: 1
🔍 18.570s    [crab_usb::backend::xhci::device:273] Addressing device with ID: 1
🔍 18.571s    [crab_usb::backend::xhci::device:281] ctrl ring: BusAddr(6282000), port speed: 3, max packet size: 64, route st0
🔍 18.573s    [crab_usb::backend::xhci::device:351] Input context bus address: 0x6281000
🔍 18.573s    [crab_usb::backend::xhci::ring:85] [CMD] >> AddressDevice(AddressDevice { input_context_pointer: 103288832, bl )
🔍 18.575s    [usb_if::transfer::wait:73] WaitMap: try_wait_for_result called with id 23FC010, elem@0xffff9003ffe0bc30 false
🐛 18.577s    [crab_usb::backend::xhci::device:361] Address slot ok CommandCompletion { completion_code: Ok(Success), command}🔍 18.579s    [crab_usb::backend::xhci::device:379] control_fetch_control_point_packet_size
🔍 18.580s    [crab_usb::backend::xhci::ring:96] [Transfer] >> SetupStage(SetupStage { interrupt_on_completion: false, reques)🔍 18.582s    [crab_usb::backend::xhci::ring:96] [Transfer] >> DataStage(DataStage { interrupt_on_completion: false, data_buf)🔍 18.586s    [crab_usb::backend::xhci::ring:96] [Transfer] >> StatusStage(StatusStage { interrupt_on_completion: true, inter)🔍 18.588s    [crab_usb::backend::xhci::endpoint:75] trb : BusAddr(
                                                                      0x6282020,
                                                                                ), addr: 0xffff9003ffe0b900, len: 8, In
🔍 18.589s    [crab_usb::backend::xhci::endpoint:83] ring doorbell: slot 1, doorbell::Register { doorbell_target: 1, doorbell}🔍 18.591s    [crab_usb::backend::xhci::endpoint:86] ring doorbell done
🔍 18.592s    [crab_usb::backend::xhci::root:608] wait_for_transfer: BusAddr(103292960)
🔍 18.593s    [usb_if::transfer::wait:73] WaitMap: try_wait_for_result called with id 6282020, elem@0xffff9003ffe188d0 false
  • 完整的 uboot bootcmd:
setenv bootcmd 'echo "Loading Kernel and DTB from TFTP..."; \
  setenv kernel_addr_r 0x02000000; \
  setenv fdt_addr_r 0x12000000; \
  pci enum; \
  mmc dev 1; \
  mmc part; \
  usb start; \
  tftp ${kernel_addr_r} Uimage; \
  tftp ${fdt_addr_r} rk3588-orangepi-5-plus.dtb; \
  bootm ${kernel_addr_r} - ${fdt_addr_r}'
  • 完整的日志:
Starting kernel ...

fdt                     : 0xecb89000
EL                      : 1
_start                  : 0xffff800000000000
stack                   : 0xffff8000001d6000
loader                  : [0x2183000, 0x21933c0)
BootTable space         : [0x221c000 --)
code                    : [0xffff800000000000, 0xffff800020000000) -> [0x2000000, 0x22000000)
ram                     : 0xffff900000200000-> 0x200000
ram                     : 0xffff900100000000-> 0x100000000
ram                     : 0xffff9003fc500000-> 0x3fc500000
ram                     : 0xffff9004f0000000-> 0x4f0000000
debug                   : 0xffff9000feb50000-> 0xfeb50000
eq                      : [0x0, 0x8000000000)
Table                   : 0x000000000221c000
Table size              : 0xc000
jump to                 : 0xffff8000000ccb24
SomeHAL booting...
Power management method : SMC
CPU 0x100 stack: [0x0000000002229000, 0x0000000002269000)
CPU 0x200 stack: [0x0000000002269000, 0x00000000022a9000)
CPU 0x300 stack: [0x00000000022a9000, 0x00000000022e9000)
CPU 0x400 stack: [0x00000000022e9000, 0x0000000002329000)
CPU 0x500 stack: [0x0000000002329000, 0x0000000002369000)
CPU 0x600 stack: [0x0000000002369000, 0x00000000023a9000)
CPU 0x700 stack: [0x00000000023a9000, 0x00000000023e9000)
Goto main...
FDT at 0x21d7000
boot regions:
  [reserved        ] [0x0, 0x0) Reserved        Normal  RWX
  [reserved        ] [0x0, 0x0) Reserved        Normal  RWX
  [reserved        ] [0x110000, 0x200000)       Reserved        Normal  RWX
  [ram             ] [0x200000, 0xf0000000)     Ram     Normal  RWX
  [reserved        ] [0x200000, 0x2000000)      Reserved        Normal  RWX
  [.text           ] [0x2001000, 0x2152000)     KImage  Normal  R-X
  [.rodata         ] [0x2152000, 0x2194000)     KImage  Normal  R-X
  [.data           ] [0x2194000, 0x2196000)     KImage  Normal  RWX
  [.stack0         ] [0x2196000, 0x21d6000)     KImage  PerCpu  RWX
  [.bss            ] [0x21d6000, 0x21d7000)     KImage  Normal  RWX
  [embedded loader ] [0x21d7000, 0x2229000)     KImage  Normal  RWX
  [reserved        ] [0x2229000, 0x23e9000)     Reserved        Normal  RWX
  [reserved        ] [0xa100000, 0xa145000)     Reserved        Normal  RWX
  [reserved        ] [0xa200040, 0xb65f000)     Reserved        Normal  RWX
  [reserved        ] [0x10000000, 0x20000000)   Reserved        Normal  RWX
  [debug           ] [0xfeb50000, 0xfeb51000)   Mmio    Device  RW-
  [ram             ] [0x100000000, 0x3fc000000) Ram     Normal  RWX
  [ram             ] [0x3fc500000, 0x3fff00000) Ram     Normal  RWX
  [ram             ] [0x4f0000000, 0x500000000) Ram     Normal  RWX
Kernel starting...
init tmp page table...
page table allocator 0x6280000, 0xa100000
map boot regions...
  [reserved        ] [0xffff900000000000, 0xffff900000000000) -> [0x0, 0x0),    RWX,    Normal
  [reserved        ] [0xffff900000000000, 0xffff900000000000) -> [0x0, 0x0),    RWX,    Normal
  [reserved        ] [0xffff900000110000, 0xffff900000200000) -> [0x110000, 0x200000),  RWX,    Normal
  [ram             ] [0xffff900000200000, 0xffff9000f0000000) -> [0x200000, 0xf0000000),        RWX,    Normal
  [reserved        ] [0xffff900000200000, 0xffff900002000000) -> [0x200000, 0x2000000), RWX,    Normal
  [.text           ] [0xffff800000001000, 0xffff800000152000) -> [0x2001000, 0x2152000),        R-X,    Normal
  [.rodata         ] [0xffff800000152000, 0xffff800000194000) -> [0x2152000, 0x2194000),        R-X,    Normal
  [.data           ] [0xffff800000194000, 0xffff800000196000) -> [0x2194000, 0x2196000),        RWX,    Normal
  [.stack0         ] [0xffff800000196000, 0xffff8000001d6000) -> [0x2196000, 0x21d6000),        RWX,    PerCpu
  [.bss            ] [0xffff8000001d6000, 0xffff8000001d7000) -> [0x21d6000, 0x21d7000),        RWX,    Normal
  [embedded loader ] [0xffff8000001d7000, 0xffff800000229000) -> [0x21d7000, 0x2229000),        RWX,    Normal
  [reserved        ] [0xffff900002229000, 0xffff9000023e9000) -> [0x2229000, 0x23e9000),        RWX,    Normal
  [reserved        ] [0xffff90000a100000, 0xffff90000a145000) -> [0xa100000, 0xa145000),        RWX,    Normal
  [reserved        ] [0xffff90000a200000, 0xffff90000b65f000) -> [0xa200000, 0xb65f000),        RWX,    Normal
  [reserved        ] [0xffff900010000000, 0xffff900020000000) -> [0x10000000, 0x20000000),      RWX,    Normal
  [debug           ] [0xffff9000feb50000, 0xffff9000feb51000) -> [0xfeb50000, 0xfeb51000),      RW-,    Device
  [ram             ] [0xffff900100000000, 0xffff9003fc000000) -> [0x100000000, 0x3fc000000),    RWX,    Normal
  [ram             ] [0xffff9003fc500000, 0xffff9003fff00000) -> [0x3fc500000, 0x3fff00000),    RWX,    Normal
  [ram             ] [0xffff9004f0000000, 0xffff900500000000) -> [0x4f0000000, 0x500000000),    RWX,    Normal
Table: PageTableRef { id: 0, addr: 0x6280000 }
heap add memory [0xffff9000023e9000, 0xffff900006280000)
heap initialized
init page table...
map boot regions...
  [reserved        ] [0xffff900000000000, 0xffff900000000000) -> [0x0, 0x0),    RWX,    Normal
  [reserved        ] [0xffff900000000000, 0xffff900000000000) -> [0x0, 0x0),    RWX,    Normal
  [reserved        ] [0xffff900000110000, 0xffff900000200000) -> [0x110000, 0x200000),  RWX,    Normal
  [ram             ] [0xffff900000200000, 0xffff9000f0000000) -> [0x200000, 0xf0000000),        RWX,    Normal
  [reserved        ] [0xffff900000200000, 0xffff900002000000) -> [0x200000, 0x2000000), RWX,    Normal
  [.text           ] [0xffff800000001000, 0xffff800000152000) -> [0x2001000, 0x2152000),        R-X,    Normal
  [.rodata         ] [0xffff800000152000, 0xffff800000194000) -> [0x2152000, 0x2194000),        R-X,    Normal
  [.data           ] [0xffff800000194000, 0xffff800000196000) -> [0x2194000, 0x2196000),        RWX,    Normal
  [.stack0         ] [0xffff800000196000, 0xffff8000001d6000) -> [0x2196000, 0x21d6000),        RWX,    PerCpu
  [.bss            ] [0xffff8000001d6000, 0xffff8000001d7000) -> [0x21d6000, 0x21d7000),        RWX,    Normal
  [embedded loader ] [0xffff8000001d7000, 0xffff800000229000) -> [0x21d7000, 0x2229000),        RWX,    Normal
  [reserved        ] [0xffff900002229000, 0xffff9000023e9000) -> [0x2229000, 0x23e9000),        RWX,    Normal
  [reserved        ] [0xffff90000a100000, 0xffff90000a145000) -> [0xa100000, 0xa145000),        RWX,    Normal
  [reserved        ] [0xffff90000a200000, 0xffff90000b65f000) -> [0xa200000, 0xb65f000),        RWX,    Normal
  [reserved        ] [0xffff900010000000, 0xffff900020000000) -> [0x10000000, 0x20000000),      RWX,    Normal
  [debug           ] [0xffff9000feb50000, 0xffff9000feb51000) -> [0xfeb50000, 0xfeb51000),      RW-,    Device
  [ram             ] [0xffff900100000000, 0xffff9003fc000000) -> [0x100000000, 0x3fc000000),    RWX,    Normal
  [ram             ] [0xffff9003fc500000, 0xffff9003fff00000) -> [0x3fc500000, 0x3fff00000),    RWX,    Normal
  [ram             ] [0xffff9004f0000000, 0xffff900500000000) -> [0x4f0000000, 0x500000000),    RWX,    Normal
Table: PageTableRef { id: 0, addr: 0x23e9000 }
expand heap [0xffff900006280000, 0xffff90000a100000)
Heap add memory [0xffff900100000000, 0xffff9003fc000000)
Heap add memory [0xffff9003fc500000, 0xffff9003fff00000)
Heap add memory [0xffff9004f0000000, 0xffff900500000000)

     _____                                         __
                                                         / ___/ ____   ____ _ _____ _____ ___   ____ _ / /
                                                                                                              \__ \ / __ \ /




Version                       : 0.12.2
Platfrom                      : RK3588 OPi 5 Plus
Start CPU                     : 0x0
FDT                           : 0xffff9000021d7000
🐛 0.000ns    [sparreal_kernel::driver:16] add registers
🐛 0.000ns    [rdrive::probe::fdt:168] Probe [interrupt-controller@fe600000]->[GICv3]
🐛 0.000ns    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fe600000, 0xffff9000fe610000) -> [0xfe600000)🐛 0.000ns    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fe680000, 0xffff9000fe780000) -> [0xfe680000)🐛 0.000ns    [rdrive::probe::fdt:168] Probe [timer]->[ARMv8 Timer]
🐛 0.000ns    [sparreal_rt::arch::timer:78] ARMv8 Timer IRQ: IrqConfig { irq: 0x1e, trigger: LevelHigh, is_private: true }
🐛 0.000ns    [rdrive::probe::fdt:168] Probe [psci]->[ARM PSCI]
🐛 0.000ns    [sparreal_rt::arch::power:76] PCSI [Smc]
🐛 0.000ns    [sparreal_kernel::irq:39] [GICv3](405) open
🔍 0.000ns    [arm_gic_driver::version::v3:342] Initializing GICv3 Distributor@0xffff9000fe600000, security state: NonSecure..🔍 0.000ns    [arm_gic_driver::version::v3:356] GICv3 Distributor disabled
🔍 0.000ns    [arm_gic_driver::version::v3:865] CPU interface initialization for CPU: 0x0
🔍 0.000ns    [arm_gic_driver::version::v3:921] CPU interface initialized successfully
🐛 0.000ns    [sparreal_kernel::irq:64] [GICv3](405) init cpu: CPUHardId(0)
🐛 0.000ns    [sparreal_rt::arch::timer:30] ARMv8 Timer: Enabled
🐛 16.732s    [sparreal_kernel::irq:136] Enable irq 0x1e on chip 405
🐛 16.733s    [sparreal_kernel::hal_al::run:33] Driver initialized
🐛 17.358s    [rdrive:132] probe pci devices
begin test
Run test: test_all
🐛 17.514s    [test::tests:299] skip usb@fc000000 because dr_mode=otg
usb node: usb@fc400000
usb regs: [<0xfc400000, 0x400000>]
🐛 17.603s    [test::tests:373] power-domains for usb@fc400000: ctrl=0x61, domains=[31]
🐛 17.633s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fd8d8000, 0xffff9000fd8d9000) -> [0xfd8d8000)💡 17.635s    [test::tests:439] enabled rk3588 power domain PowerDomain(31)
💡 17.636s    [test::tests:439] enabled rk3588 power domain PowerDomain(32)
🐛 17.665s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fd7c0000, 0xffff9000fd81c000) -> [0xfd7c0000)🐛 17.667s    [rk3588_clk:752] Enabling USB gate_id 396
🐛 17.668s    [rk3588_clk:833] Getting USB gate status for gate_id 396
💡 17.669s    [rk3588_clk:839] gate_con42 value: 0x0
🐛 17.669s    [rk3588_clk:911] USB Gate 396 is enabled
💡 17.670s    [test::tests:526] USB clock 396 enabled successfully
🐛 17.671s    [rk3588_clk:752] Enabling USB gate_id 397
🐛 17.671s    [rk3588_clk:833] Getting USB gate status for gate_id 397
🐛 17.672s    [rk3588_clk:911] USB Gate 397 is enabled
💡 17.673s    [test::tests:526] USB clock 397 enabled successfully
🐛 17.674s    [rk3588_clk:752] Enabling USB gate_id 405
🐛 17.674s    [rk3588_clk:833] Getting USB gate status for gate_id 405
🐛 17.675s    [rk3588_clk:911] USB Gate 405 is enabled
💡 17.676s    [test::tests:526] USB clock 405 enabled successfully
🐛 17.676s    [rk3588_clk:752] Enabling USB gate_id 406
🐛 17.677s    [rk3588_clk:833] Getting USB gate status for gate_id 406
🐛 17.678s    [rk3588_clk:911] USB Gate 406 is enabled
💡 17.679s    [test::tests:526] USB clock 406 enabled successfully
🐛 17.679s    [rk3588_clk:752] Enabling USB gate_id 407
🐛 17.680s    [rk3588_clk:833] Getting USB gate status for gate_id 407
🐛 17.681s    [rk3588_clk:911] USB Gate 407 is enabled
💡 17.681s    [test::tests:526] USB clock 407 enabled successfully
🐛 17.682s    [rk3588_clk:752] Enabling USB gate_id 398
🐛 17.683s    [rk3588_clk:833] Getting USB gate status for gate_id 398
🐛 17.684s    [rk3588_clk:911] USB Gate 398 is enabled
💡 17.684s    [test::tests:526] USB clock 398 enabled successfully
🐛 17.685s    [rk3588_clk:752] Enabling USB gate_id 399
🐛 17.686s    [rk3588_clk:833] Getting USB gate status for gate_id 399
🐛 17.686s    [rk3588_clk:911] USB Gate 399 is enabled
💡 17.687s    [test::tests:526] USB clock 399 enabled successfully
🐛 17.688s    [rk3588_clk:752] Enabling USB gate_id 400
🐛 17.688s    [rk3588_clk:833] Getting USB gate status for gate_id 400
🐛 17.689s    [rk3588_clk:911] USB Gate 400 is enabled
💡 17.690s    [test::tests:526] USB clock 400 enabled successfully
🐛 17.691s    [rk3588_clk:752] Enabling USB gate_id 401
🐛 17.691s    [rk3588_clk:833] Getting USB gate status for gate_id 401
🐛 17.692s    [rk3588_clk:911] USB Gate 401 is enabled
💡 17.693s    [test::tests:526] USB clock 401 enabled successfully
🐛 17.894s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fec40000, 0xffff9000fec41000) -> [0xfec40000)💡 17.896s    [test::tests:579] vcc5v0_host enabled via gpio ctrl phandle 0x10e, pin 15
🐛 17.924s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fd5d0000, 0xffff9000fd5d4000) -> [0xfd5d0000)💡 17.926s    [test::tests:624] usb2phy-grf syscon@fd5d0000 active (CON3 suspend override set)
🐛 17.954s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fd5c8000, 0xffff9000fd5cc000) -> [0xfd5c8000)💡 17.956s    [test::tests:661] usbdpphy-grf syscon@fd5c8000 active (CON3 override/powerdown cleared)
🐛 17.985s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fd7c0000, 0xffff9000fd81c000) -> [0xfd7c0000)💡 17.987s    [test::tests:469] Checking USB PHY initialization status...
💡 17.988s    [test::tests:776] === Diagnosing USBDP PHY1 @ 0xfed90000 ===
🐛 17.989s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fed90000, 0xffff9000feda0000) -> [0xfed90000)💡 17.990s    [test::tests:785] LCPLL Done Register: 0x00000000
💡 17.991s    [test::tests:786]   - LCPLL Locked: NO ✗
💡 17.992s    [test::tests:791] PCS Ready Register: 0x00000000
💡 17.992s    [test::tests:792]   - PCS Ready: NO ✗
💡 17.993s    [test::tests:801] RefClk Config [0x0090]: 0x0 (expected: 0x68)
💡 17.994s    [test::tests:802] RefClk Config [0x0094]: 0x0 (expected: 0x68)
💡 17.995s    [test::tests:805]   - RefClk Configured: NO ✗
💡 17.995s    [test::tests:810] Init Config [0x0104]: 0x0 (expected: 0x44)
⚠️ 17.996s    [test::tests:820] ✗ PHY1 is NOT properly initialized
⚠️ 17.997s    [test::tests:822]   → RefClk registers not configured (needs 70-reg sequence)
⚠️ 17.998s    [test::tests:825]   → Init registers not configured (needs 74-reg sequence)
⚠️ 17.999s    [test::tests:828]   → LCPLL not locked (PHY clock not ready)
⚠️ 18.000s    [test::tests:831]   → PCS not ready (link training failed)
💡 18.001s    [test::tests:836] ========================================
🐛 18.001s    [somehal::arch::mem::mmu:181] Map `iomap       `: RW- | [0xffff9000fc400000, 0xffff9000fc800000) -> [0xfc400000)🐛 18.131s    [sparreal_kernel::irq:136] Enable irq 0xfd on chip 405
🐛 18.132s    [crab_usb::backend::xhci:203] Extended capabilities: 3
🐛 18.133s    [crab_usb::backend::xhci:215] legacy init
🐛 18.233s    [crab_usb::backend::xhci:228] claimed ownership from BIOS
🐛 18.234s    [crab_usb::backend::xhci:130] Reset begin ...
🐛 18.235s    [crab_usb::backend::xhci:139] Halted
🐛 18.235s    [crab_usb::backend::xhci:141] Wait for ready...
🐛 18.236s    [crab_usb::backend::xhci:145] Ready
🐛 18.237s    [crab_usb::backend::xhci:151] Reset HC
🐛 18.237s    [crab_usb::backend::xhci:157] Reset finish
🐛 18.238s    [crab_usb::backend::xhci:175] Max device slots: 64
🐛 18.241s    [crab_usb::backend::xhci::root:123] Disable interrupts
🐛 18.242s    [crab_usb::backend::xhci::root:99] DCBAAP: 23FF000
🐛 18.242s    [crab_usb::backend::xhci::root:109] CRCR: 23FC000
🐛 18.243s    [crab_usb::backend::xhci::root:143] ERDP: 23fd000
🐛 18.244s    [crab_usb::backend::xhci::root:151] ERSTZ: 1
🐛 18.245s    [crab_usb::backend::xhci::root:153] ERSTBA: 23FE000
🐛 18.245s    [crab_usb::backend::xhci::root:165] Enabling primary interrupter.
🐛 18.246s    [crab_usb::backend::xhci::root:193] Scratch buf count: 1
🐛 18.247s    [crab_usb::backend::xhci::root:205] Setting up 1 scratchpads, at 0x23fe040
🐛 18.248s    [crab_usb::backend::xhci::root:218] Start run
💡 18.299s    [crab_usb::backend::xhci::root:493] Running
🐛 18.400s    [crab_usb::backend::xhci::root:129] Enable interrupts
🐛 18.400s    [crab_usb::backend::xhci::root:283] Port 0 start reset
🐛 18.401s    [crab_usb::backend::xhci::root:283] Port 1 start reset
🐛 18.453s    [crab_usb::backend::xhci::root:319] Port 0 reset completed, checking status
🐛 18.454s    [crab_usb::backend::xhci::root:321] Port 0 status after reset: enabled=true, connected=true, speed=3
🐛 18.456s    [crab_usb::backend::xhci::root:319] Port 1 reset completed, checking status
🐛 18.457s    [crab_usb::backend::xhci::root:321] Port 1 status after reset: enabled=true, connected=true, speed=4
💡 18.558s    [test::tests:45] usb host init ok
💡 18.559s    [test::tests:46] usb cmd test
💡 18.559s    [crab_usb::backend::xhci:250] Port 0: Enabled: true, Connected: true, Speed 3, Power true
💡 18.561s    [crab_usb::backend::xhci:250] Port 1: Enabled: true, Connected: true, Speed 4, Power true
🐛 18.562s    [crab_usb::backend::xhci::root:570] New device on port 0
🔍 18.562s    [crab_usb::backend::xhci::ring:85] [CMD] >> EnableSlot(EnableSlot { slot_type: 0, cycle_bit: true }) @BusAddr(2)
🔍 18.564s    [usb_if::transfer::wait:73] WaitMap: try_wait_for_result called with id 23FC000, elem@0xffff9003ffe0bc00 false
🔍 18.565s    [crab_usb::backend::xhci::root:565] assigned slot id: 1
🐛 18.566s    [crab_usb::backend::xhci::root:572] Slot 1 assigned
🐛 18.567s    [crab_usb::backend::xhci::root:581] Creating new context for slot 1, 64-bit
🔍 18.569s    [crab_usb::backend::xhci::device:203] Initializing device with ID: 1
🔍 18.570s    [crab_usb::backend::xhci::device:273] Addressing device with ID: 1
🔍 18.571s    [crab_usb::backend::xhci::device:281] ctrl ring: BusAddr(6282000), port speed: 3, max packet size: 64, route st0
🔍 18.573s    [crab_usb::backend::xhci::device:351] Input context bus address: 0x6281000
🔍 18.573s    [crab_usb::backend::xhci::ring:85] [CMD] >> AddressDevice(AddressDevice { input_context_pointer: 103288832, bl )
🔍 18.575s    [usb_if::transfer::wait:73] WaitMap: try_wait_for_result called with id 23FC010, elem@0xffff9003ffe0bc30 false
🐛 18.577s    [crab_usb::backend::xhci::device:361] Address slot ok CommandCompletion { completion_code: Ok(Success), command}
🔍 18.579s    [crab_usb::backend::xhci::device:379] control_fetch_control_point_packet_size
🔍 18.580s    [crab_usb::backend::xhci::ring:96] [Transfer] >> SetupStage(SetupStage { interrupt_on_completion: false, reques)
🔍 18.582s    [crab_usb::backend::xhci::ring:96] [Transfer] >> DataStage(DataStage { interrupt_on_completion: false, data_buf)
🔍 18.586s    [crab_usb::backend::xhci::ring:96] [Transfer] >> StatusStage(StatusStage { interrupt_on_completion: true, inter)
🔍 18.588s    [crab_usb::backend::xhci::endpoint:75] trb : BusAddr(
                                                                      0x6282020,
                                                                                ), addr: 0xffff9003ffe0b900, len: 8, In
🔍 18.589s    [crab_usb::backend::xhci::endpoint:83] ring doorbell: slot 1, doorbell::Register { doorbell_target: 1, doorbell}🔍 18.591s    [crab_usb::backend::xhci::endpoint:86] ring doorbell done
🔍 18.592s    [crab_usb::backend::xhci::root:608] wait_for_transfer: BusAddr(103292960)
🔍 18.593s    [usb_if::transfer::wait:73] WaitMap: try_wait_for_result called with id 6282020, elem@0xffff9003ffe188d0 false

这个 PR(拉取请求)主要是使用 Claude Opus 4.5 通过 Claude Code 编写的,随后由我进行了人工复核。我对本 PR 中的所有更改负完全责任。我已尽力确保其符合我们的目标,但可能仍有一些细微的疏漏。如果发现任何不妥之处,请指出来,我会尽快修复。

@yueneiqi
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在此基础上还做了一些失败的尝试,没有新的进展。
因为目前精力有限,计划先搁置1~2周。1~2周之后会尝试先通过迁移 uboot 中 usb start 的逻辑,对 USB 驱动相关知识了解更深后,再进一步推进。
以上内容可供大家参考,希望有所帮助。

@yueneiqi
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yueneiqi commented Dec 7, 2025

uboot 中 usb start 关 xhci 的逻辑梳理
XHCI DWC3 Driver (u-boot/drivers/usb/host/xhci-dwc3.c:158)

static int xhci_dwc3_probe(struct udevice *dev)
{
    struct xhci_hcor *hcor;
    struct xhci_hccr *hccr;
    struct dwc3 *dwc3_reg;
    enum usb_dr_mode dr_mode;
    struct xhci_dwc3_plat *plat = dev_get_plat(dev);
    int ret;

    /* 1. Initialize resets */
    ret = xhci_dwc3_reset_init(dev, plat);
    if (ret)
        return ret;

    /* 2. Initialize clocks */
    ret = xhci_dwc3_clk_init(dev, plat);
    if (ret)
        return ret;

    /* 3. Map XHCI registers */
    hccr = (struct xhci_hccr *)((uintptr_t)dev_remap_addr(dev));
    hcor = (struct xhci_hcor *)((uintptr_t)hccr +
            HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

    /* 4. Setup PHY */
    ret = dwc3_setup_phy(dev, &plat->phys);
    if (ret && (ret != -ENOTSUPP))
        return ret;

    /* 5. Get DWC3 registers */
    dwc3_reg = (struct dwc3 *)((char *)(hccr) + DWC3_REG_OFFSET);

    /* 6. Core initialization */
    dwc3_core_init(dwc3_reg);  // ← Critical: resets and configures DWC3 core

    /* 7. Configure USB2 PHY */
    reg = readl(&dwc3_reg->g_usb2phycfg[0]);

    /* 8. Apply quirks and settings from device tree */
    if (dev_read_bool(dev, "snps,dis_enblslpm_quirk"))
        reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;

    if (dev_read_bool(dev, "snps,dis-u2-freeclk-exists-quirk"))
        reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;

    if (dev_read_bool(dev, "snps,dis_u2_susphy_quirk"))
        reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;

    writel(reg, &dwc3_reg->g_usb2phycfg[0]);

    /* 9. Set USB mode (OTG/Host) based on device tree */
    dr_mode = usb_get_dr_mode(dev_ofnode(dev));
    if (dr_mode == USB_DR_MODE_OTG &&
        dev_read_bool(dev, "usb-role-switch")) {
        dr_mode = usb_get_role_switch_default_mode(dev_ofnode(dev));
        if (dr_mode == USB_DR_MODE_UNKNOWN)
            dr_mode = USB_DR_MODE_OTG;
    }
    if (dr_mode == USB_DR_MODE_UNKNOWN)
        dr_mode = USB_DR_MODE_HOST;

    /* 10. Configure DWC3 mode */
    dwc3_set_mode(dwc3_reg, dr_mode);

    /* 11. Register XHCI controller */
    return xhci_register(dev, hccr, hcor);
}

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